JP3141938B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a trench-filled element isolation region of a semiconductor device.

[0002]

2. Description of the Related Art In forming a trench-buried element isolation region of a semiconductor device, an element isolation region having high flatness over the entire surface of a wafer is formed without depending on the size, shape, density, etc. of a pattern for separating elements. It is important to form.

For this reason, a chemical mechanical polishing method (CMP: Chemical Mechanic) having a high planarization property of an oxide film.
A method of flattening an element isolation region by using an electrical polishing method has been adopted.

However, in this method, there is a pattern dependency in which the polishing rate of the buried oxide film varies depending on the size, shape, density, etc. of the pattern separating the elements. As a result, unevenness occurs in the element isolation pattern in a chip or a wafer surface, which causes an increase in leakage current between elements and a deterioration in electrical characteristics such as a decrease in withstand voltage.
It cannot be said that it is sufficient as an element isolation region forming technique.

[0005] Therefore, for example, Proceeding o
f 1996 CMP-MIC Conference
e, pp. 249-255. (1996) discloses a method using a dummy pattern for the purpose of making the polishing rate of the entire buried oxide film uniform and suppressing the occurrence of unevenness in a polishing method in which pattern dependency is likely to occur. I have.

The prior art will be described below with reference to the drawings. FIG. 3 is a longitudinal sectional view showing this conventional technique in the order of manufacturing steps.

First, as shown in FIG. 3A, a stopper film 103 composed of an oxide film 102 having a thickness of 70 to 100.degree. And a nitride film having a thickness of 1500 to 2000.degree. .

Subsequently, as shown in FIG. 3B, the stopper film 103 and the oxide film 102 in a region to be an element isolation pattern later are selectively removed by a known method such as PR or dry etching, and further exposed. The silicon substrate 101 is etched to open an element isolation groove 105 having a predetermined depth. The region where the stopper film 103 and the oxide film 102 remain becomes an element formation region later, and includes a dummy diffusion layer 109 which is not related to the operation of the semiconductor device.

Subsequently, as shown in FIG. 3C, the side wall portion of the element isolation groove 105 is thermally oxidized to form a side wall oxide film 106, and further, the silicon substrate 101 including the element isolation groove 105 is formed.
A buried oxide film 107 is deposited on the entire surface by the CVD method to bury the element isolation trench 105.

Then, as shown in FIG. 3D, the buried oxide film 107 is polished and removed by chemical mechanical polishing (CMP) until the stopper film 103 is exposed, and the stopper film 103 and the oxide film 102 are further removed. Thus, the element formation region 108 is exposed in a predetermined region of the silicon substrate.

In this CMP, a pattern dependency occurs in which the polishing rate of the buried oxide film varies depending on the size, shape, density and the like of the pattern to be polished. It is said that this is due to the elastic deformation of the polishing pad and the fluidity of the abrasive particles in the slurry.

However, by arranging the dummy diffusion layer in advance in the pattern so that these dependencies can be reduced, the pattern dependency when polishing the buried oxide film 107 can be reduced. In this case, a certain effect is achieved in reducing unevenness generated in the element isolation pattern. However, this is not sufficient, and there is a drawback that a recess 110 typified by dishing or erosion is formed in the buried oxide film depending on the pattern.

[0013]

The prior art method of arranging a dummy diffusion layer in advance in this pattern acts as a positive factor with respect to process technology, such as an increase in process margin. On the other hand, on the other hand, it poses a problem that it acts as a negative factor in the design technical fields such as circuit layout and mask design. This is because if the miniaturization of the design rules and the increase in the capacity of the circuit and the reduction in the chip area are to be simultaneously satisfied, restrictions on the size, shape, and location of the dummy diffusion layer to be arranged in advance become large. This is because the circuit layout becomes complicated and difficult, and the man-hour required for mask design also increases.

Further, depending on the type of the semiconductor device, the CMP
However, since the size, shape, and arrangement location of the effective dummy diffusion layer are greatly different from each other, the load on the design technique is further increased.

Therefore, with the miniaturization of the semiconductor device, the arrangement of the dummy diffusion layer causes a problem that its application becomes difficult.

Accordingly, a main object of the present invention is to provide a method of grinding and polishing a buried oxide film having a high flattening property without depending on the size, shape, arrangement state (density) and the like of an element isolation pattern. It is in.

[0017]

A method of manufacturing a semiconductor device according to the present invention is based on the conventional technique that "a dummy diffusion layer for alleviating the pattern dependence of polishing is disposed in advance in the pattern". With respect to the structure of the method, "(1) a step of sequentially forming an oxide film and a stopper film on a semiconductor substrate;
(2) a step of forming an element region mask in a predetermined region on the stopper film which will later become an element formation region; and (3) a predetermined depth of the semiconductor substrate in a predetermined region of the oxide film and the stopper film. Opening an element isolation groove that reaches
(4) a step of oxidizing a side wall of the element isolation groove; and (5)
Burying the element isolation trench with a buried oxide film;
(6) a grindstone composed of a sintered body of cerium oxide;
Grinding and removing the buried oxide film by mechanical grinding using a slurry containing cerium oxide as a main component until the buried oxide film is planarized; (7) subsequently, the stopper film is formed by chemical mechanical polishing. Polishing and removing the buried oxide film until it is exposed; and (8) removing the stopper film and the oxide film to expose a surface of a predetermined region of the semiconductor substrate. That is the feature.

That is, in the present invention, the buried oxide film is removed in advance by a mechanical grinding method that hardly exhibits pattern dependency and has high flattening property before performing chemical mechanical polishing that tends to cause pattern dependency. And a step of flattening. This mechanical grinding step serves to prevent the dependence of polishing on the pattern by pre-planarizing the buried oxide film to make it the same state as polishing an oxide film without a pattern.

Therefore, the excellent effect of the present invention that flattening characteristics without unevenness can be obtained even in an element isolation pattern having any size, shape and arrangement state (density).

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In carrying out the method of the present invention, it is preferable that a stopper film is formed of either a nitride film or a polycrystalline silicon film.

Further, the mechanical grinding is preferably performed using a grindstone.

The mechanical grinding is preferably performed using a grindstone composed of a sintered body of cerium oxide and a slurry containing cerium oxide as a main component.

In the step of removing the buried oxide film by mechanical grinding, the grinding amount of the buried oxide film is 500 ° to 300 ° larger than the thickness of the deposited buried oxide film.
Preferably, it is less by 0 °.

In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in more detail by the following examples with reference to the accompanying drawings. It is not limited by these embodiments.

[0025]

[Embodiment 1] Referring to FIG. 1, there is shown a longitudinal sectional view showing a manufacturing process as an embodiment of the present invention in the order of the manufacturing process.

First, as shown in FIG. 1A, an oxide film 102 having a thickness of 100.degree. Is formed on a silicon substrate 101 by a thermal oxidation method, and a stopper film formed of a nitride film having a thickness of 1500.degree. 103 was formed by a CVD method. Then, an element region mask 10 is formed on the stopper film 103 by a PR method in a predetermined region to be an element formation region later.
4 was formed. Subsequently, the exposed stopper film 103 and oxide film 102 are selectively removed by a dry etching method, and the exposed silicon substrate 101 is etched to form a device isolation groove 1 having a depth of 3000 to 5000 °.
05 was opened. Stopper film 103 and oxide film 102
Are left, the region covered with the element region mask 104 is
The element formation region will be formed later, but does not include a dummy diffusion layer or the like.

Subsequently, as shown in FIG. 1B, after removing the device region mask 104, the side wall portion of the device isolation trench 105 is oxidized by a thermal oxidation method to a thickness of 100 to 200 ° to form the side surface oxide film 106. Then, a buried oxide film 107 was deposited on the entire surface of the silicon substrate 101 including the element isolation groove 105 by a CVD method to a thickness of 5000 to 7000 ° to fill the element isolation groove 105. As a result, the buried oxide film 107 has irregularities reflecting the underlying pattern.

Then, as shown in FIG. 1C, the buried oxide film 107 was ground and removed by a mechanical grinding method by a thickness of 4000 to 6000 ° to planarize the buried oxide film 107. For this mechanical grinding method, the same apparatus and method as those used for backside grinding of a silicon wafer are used. In this method, grinding is performed by a physical element. However, since the amount of elastic deformation of the grinding wheel is extremely small as compared with a polishing pad used in a chemical mechanical polishing method (CMP), there is little pattern dependency and a high level. Easy to obtain flatness. However, since the grinding wheel has high mechanical strength, scratches and the like are likely to occur depending on the grinding conditions.

Then, as shown in FIG. 1D, the remaining 1000 ° of the planarized buried oxide film 107 was polished by a chemical mechanical polishing method (CMP method) to expose the stopper film 103. Then, the stopper film 103 is heated with phosphoric acid, and the underlying oxide film 102 is treated with hydrofluoric acid.
Each of them was removed to expose the element formation region 108 in a predetermined region on the silicon substrate 101.

In this CMP, the underlying buried oxide film 1
07 is flattened, it is difficult for the polishing to depend on the pattern, and the polishing amount is small.
The problem of unevenness due to the pattern dependency, which has been a problem, can be overcome. Even if a defect such as a scratch occurs in the buried oxide film 107 in the grinding process, the scratch can be removed by the CMP process and the wet etching process in a later process.

[Embodiment 2] In the above embodiment, the stopper film can be formed by a method using polycrystalline silicon, and the step of grinding the buried oxide film using a slurry. FIG. 2 shows a configuration for that purpose as a second embodiment of the present invention.
This drawing shows a longitudinal sectional view showing an embodiment of a manufacturing process as a second embodiment of the present invention in the order of the manufacturing process. . First, as shown in FIG.
An oxide film 102 having a thickness of 100 ° was formed on the substrate 01 by a thermal oxidation method, and a stopper film 103 composed of a polycrystalline silicon film having a thickness of 1500 ° was formed thereon by a CVD method. Then, an element region mask 104 was formed on the stopper film 103 in a predetermined region to be an element formation region later by the PR method. Subsequently, the exposed stopper film 103 and the exposed oxide film 102 are formed by dry etching.
Is selectively removed, and the exposed silicon substrate 101 is further removed.
Was etched to open an element isolation groove 105 having a depth of 3000 to 5000 °. The region covered with the element region mask 104 where the stopper film 103 and the oxide film 102 remain becomes an element formation region later, and includes a dummy diffusion layer as in the case of the first embodiment. Not.

Subsequently, as shown in FIG. 2B, after removing the element region mask, the side wall of the element isolation groove 105 is oxidized by a thermal oxidation method to a thickness of 100 to 200.degree.
6 is formed, and a buried oxide film 107 is deposited on the entire surface of the silicon substrate 101 including the element isolation groove 105 by a CVD method so as to have a thickness of 5000 to 7000 °.
5 embedded. As a result, the buried oxide film 107 has irregularities reflecting the underlying pattern.

Then, as shown in FIG. 2C, the buried oxide film 107 was ground and removed by a mechanical grinding method by a thickness of 4000 to 6000 ° to planarize the buried oxide film 107. This mechanical grinding method uses cerium oxide (C
This is performed using a circular grindstone composed of a sintered body of eO) and a slurry containing CeO as a main component, while horizontally moving a rotation type grinding stage on which the silicon substrate 101 is set. And a circular grindstone rotating at 100 to 500 rpm, and a slurry containing CeO as a main component is supplied to the contact portion. In this method, grinding is performed by physical elements, and the amount of elastic deformation during grinding of the circular sintered wheel is extremely small as compared with the polishing pad used in the chemical mechanical polishing method (CMP method). In addition, pattern dependency is extremely small, and high flatness is easily obtained. In addition, there is an advantage that defects such as scratches hardly occur. However, in this method, since the selectivity of grinding (the ratio of the grinding speed of the buried oxide film to the stopper film) is not so high with respect to the stopper film, it is difficult to control the amount of grinding by the stopper film. Cost.

Further, as shown in FIG. 2D, the remaining 1000 ° of the planarized buried oxide film 107 is polished by a chemical mechanical polishing method (CMP method) to form a stopper film 10.
3 was exposed. Then, the stopper film 103 and the oxide film 102 under the stopper film 103 were removed by wet etching, respectively, to expose the element formation region 108 in a predetermined region on the silicon substrate 101.

In this CMP, the underlying buried oxide film 1
Since 07 is flat, it is unlikely to cause polishing pattern dependency, and since the polishing amount is small, it is possible to prevent the occurrence of unevenness due to pattern dependency, which is a problem of conventional CMP. Further, since the selectivity of polishing with respect to the lower stopper film is high, it is easy to control the polishing amount.
Thus, the object of the present invention is achieved.

[0036]

As described above, according to the present invention,
There is very little pattern dependency in oxide film removal, and its planarization is extremely high, but the controllability of removal amount is not very high. Based on the basic configuration that the chemical mechanical polishing method that depends on is properly used depending on the removal step of the buried oxide film, without using a dummy diffusion layer, an element isolation pattern having high flatness without pattern dependency,
Provided is a method for manufacturing a trench-buried element isolation region of a semiconductor device, which can be formed with high controllability. It should be noted that the present invention is not limited to the above embodiments, and it is obvious that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a manufacturing process in a first embodiment of the present invention, in which the order is shown from (a) to (d).

FIG. 2 is a longitudinal sectional view showing a manufacturing process according to a second embodiment of the present invention, in which the order is shown from (a) to (d).

FIG. 3 is a longitudinal sectional view showing a manufacturing process of a conventional invention.
The order is shown from (a) to (d).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Silicon substrate 102 Oxide film 103 Stopper film 104 Element region mask 105 Element isolation trench 106 Side wall oxide film 107 Embedded oxide film 108 Element formation region 109 Dummy diffusion layer 110 Depression

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/76 H01L 21/304 622 H01L 21/316

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: (1) a step of sequentially forming an oxide film and a stopper film on a semiconductor substrate; and (2) a predetermined region on the stopper film, which will be an element formation region later. Forming an element region mask; (3) opening an element isolation groove reaching a predetermined depth of the semiconductor substrate in a predetermined region of the oxide film and the stopper film; (5) a step of oxidizing a sidewall of the groove, (5) a step of burying the element isolation groove with a buried oxide film, and (6) a grindstone made of a sintered body of cerium oxide.
A step of grinding and removing the buried oxide film by mechanical grinding using a slurry containing cerium oxide as a main component until the buried oxide film is planarized; Polishing and removing the buried oxide film until it is exposed; and (8) removing the stopper film and the oxide film to expose a surface of a predetermined region of the semiconductor substrate in this order. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the stopper film is made of one of a nitride film and a polycrystalline silicon film. 3. The method according to claim 1, wherein in the step of removing the buried oxide film by the mechanical grinding, a grinding amount of the buried oxide film is smaller than a film thickness of the deposited buried oxide film by 500 ° to 3000 °. 13. The method for manufacturing a semiconductor device according to item 5.