CN109148290B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN109148290B
CN109148290B CN201710505666.6A CN201710505666A CN109148290B CN 109148290 B CN109148290 B CN 109148290B CN 201710505666 A CN201710505666 A CN 201710505666A CN 109148290 B CN109148290 B CN 109148290B
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fin
ion implantation
dielectric layer
metal layer
work function
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CN109148290A (en
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王楠
潘梓诚
洪中山
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The application discloses a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a substrate structure, the substrate structure comprising: a substrate; a fin on the substrate for a MOS device; isolation regions on the substrate and around the fins, wherein the upper surfaces of the isolation regions are lower than the upper surfaces of the fins; an interlayer dielectric layer on the isolation region and the fin, the interlayer dielectric layer having a trench exposing a portion of the fin; a gate dielectric layer on upper and side surfaces of the exposed portion of the fin, and a work function metal layer on the gate dielectric layer; and performing ion implantation on the work function metal layer to increase the threshold voltage of the MOS device. The reliability of the MOS device can be improved.

Description

Method for manufacturing semiconductor device
Technical Field
The present disclosure relates to semiconductor technologies, and more particularly, to a method for manufacturing a semiconductor device.
Background
With the reduction of the critical dimension of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Fin Field Effect transistors (finfets) with better gate control capability are gradually used to replace planar devices.
However, the inventors of the present application found that: when the FinFET works, electric field lines are intensively distributed in a region where a grid electrode and a source electrode are overlapped and the grid electrode and a drain electrode are overlapped, the density of the electric field lines at the top of the fin is particularly high, the electric field intensity of the region is high, the hot carrier effect is serious, and therefore the reliability of the FinFET is lower than that of a planar device.
For a planar device, the electric field strength of the gate and source and the gate and drain overlapped region can be reduced by a drain light doping (LDD) process, thereby improving the hot carrier effect. However, for the FinFET, this approach is not sufficient to reduce the electric field strength of the region where the gate and the source and the gate and the drain overlap to a desired degree, and thus the reliability of the FinFET is to be further improved.
Disclosure of Invention
It is an object of the present application to improve the reliability of MOS devices.
According to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, including: providing a substrate structure, the substrate structure comprising: a substrate; a fin on the substrate for a MOS device; isolation regions on the substrate and around the fins, wherein the upper surfaces of the isolation regions are lower than the upper surfaces of the fins; an interlayer dielectric layer on the isolation region and the fin, the interlayer dielectric layer having a trench exposing a portion of the fin; a gate dielectric layer on upper and side surfaces of the exposed portion of the fin, and a work function metal layer on the gate dielectric layer; and performing ion implantation on the work function metal layer to increase the threshold voltage of the MOS device.
In one embodiment, the ion implantation is performed on a work function metal layer on an upper surface of the exposed portion.
In one embodiment, the ion implantation is performed on the work function metal layer on the upper surface of the region of the exposed portion near the interlayer dielectric layer.
In one embodiment, the ion implantation is performed with the interlayer dielectric layer as a mask.
In one embodiment, the ion implantation has an implantation energy of less than 5 KeV.
In one embodiment, an angle between an implantation direction of the ion implantation and a normal of the interlayer dielectric layer is 0 to 20 degrees.
In one embodiment, the implantation direction of the ion implantation is parallel to the side of the fin.
In one embodiment, the MOS device is a PMOS device.
In one embodiment, the ion implantation implanted impurities include one or more of: al and Ga.
In one embodiment, the work function metal layer comprises one or more of: TiN, TaC, MoN.
In one embodiment, the MOS device is an NMOS device.
In one embodiment, the ion implantation implanted impurities include one or more of: n, F, C, As and La.
In one embodiment, the work function metal layer comprises one or more of: TiAl, TaC and Al.
According to another aspect of the present application, there is provided a method of manufacturing a semiconductor device, including: providing a substrate structure, the substrate structure comprising: a substrate; a first fin for a PMOS device and a second fin for an NMOS device on the substrate; an isolation region on the substrate around the first fin and the second fin, an upper surface of the isolation region being lower than upper surfaces of the first fin and the second fin; an interlayer dielectric layer on the isolation region, the first fin, and the second fin, the interlayer dielectric layer having a first trench exposing a first portion of the first fin and a second trench exposing a second portion of the second fin; a gate dielectric layer on upper surfaces and sides of the first and second portions; and a first work function metal layer on the gate dielectric layer; performing first ion implantation on the first work function metal layer to increase the threshold voltage of the PMOS device; removing the first work function metal layer on the upper surface and the side surface of the second part after the first ion implantation is performed; forming a second work function metal layer on the first work function metal layer on the upper surface and the side of the first portion and the gate dielectric layer on the upper surface and the side of the second portion; and performing second ion implantation on the second work function metal layer to increase the threshold voltage of the NMOS device.
In one embodiment, the first ion implantation is performed on a first workfunction metal layer on an upper surface of the first and second portions; performing the second ion implantation on a second work function metal layer on upper surfaces of the first and second portions.
In one embodiment, the first ion implantation is performed on a first work function metal layer on an upper surface of a region of the first portion and the second portion near the interlayer dielectric layer; and performing the second ion implantation on the second work function metal layer on the upper surface of the region of the first part and the second part close to the interlayer dielectric layer.
In one embodiment, the first ion implantation and the second ion implantation are performed with the interlayer dielectric layer as a mask.
In one embodiment, the implantation energy of the first and second ion implantations is less than 5 KeV.
In one embodiment, an angle between an implantation direction of the first ion implantation and a normal of the interlayer dielectric layer is 0-20 degrees; an angle between an implantation direction of the second ion implantation and a normal of the interlayer dielectric layer is 0-20 degrees.
In one embodiment, the implantation direction of the first ion implantation is parallel to the side faces of the first fins; the implantation direction of the second ion implantation is parallel to the side face of the second fin.
In one embodiment, the first ion implantation of impurities comprises one or more of: al, Ga; the second ion implantation implant impurities include one or more of: n, F, C, As and La.
In one embodiment, the first workfunction metal layer comprises one or more of: TiN, TaC, MoN; the second workfunction metal layer comprises one or more of: TiAl, TaC and Al.
In the manufacturing method of the embodiment of the application, after the work function metal layer is formed, the work function metal layer is subjected to ion implantation capable of increasing the threshold voltage of the MOS device, so that the electric field intensity of the MOS device in a fin during working is reduced, and the reliability of the MOS device is improved.
Other features, aspects, and advantages of the present application will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description, serve to explain the principles of the application, and in which:
FIG. 1 is a simplified flow diagram of a method of fabricating a semiconductor device according to one embodiment of the present application;
FIG. 2A shows a schematic view of a stage in forming a substrate structure according to one embodiment of the present application;
FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 2A;
FIG. 3A shows a schematic view of a stage in forming a substrate structure according to one embodiment of the present application;
FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 3A;
FIG. 4A shows a schematic view of a stage in forming a substrate structure according to one embodiment of the present application;
FIG. 4B is a cross-sectional view taken along line B-B' of FIG. 4A;
FIG. 5A shows a schematic view of a stage in forming a substrate structure according to one embodiment of the present application;
FIG. 5B is a cross-sectional view taken along line B-B' of FIG. 5A;
FIG. 6A shows a schematic view of a substrate structure according to one embodiment of the present application;
FIG. 6B is a cross-sectional view taken along line B-B' of FIG. 6A;
fig. 7 is a schematic view illustrating ion implantation of a work function metal layer in a method of manufacturing a semiconductor device according to an embodiment of the present application;
fig. 8 is a simplified flow diagram of a method of fabricating a semiconductor device according to another embodiment of the present application.
Detailed Description
Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present application unless specifically stated otherwise.
Further, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual scale, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of exemplary embodiments is merely illustrative and is not intended to limit the application and its applications or uses in any way.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification as applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
Fig. 1 is a simplified flow diagram of a method of fabricating a semiconductor device according to one embodiment of the present application. Fig. 2A-7 show schematic diagrams of stages of a method of manufacturing a semiconductor device according to an embodiment of the present application.
A method for manufacturing a semiconductor device according to an embodiment of the present application will be described in detail with reference to fig. 1 and fig. 2A to 7.
As shown in fig. 1, first, in step 102, a substrate structure is provided.
One implementation of forming the substrate structure is described below in conjunction with fig. 2A-6B.
As shown in fig. 2A and 2B, an initial substrate structure is provided. The initial substrate structure includes a substrate 201, a fin 202 on the substrate 201 for a MOS device, and an isolation region 203 on the substrate 201 around the fin 202, an upper surface of the isolation region 203 being lower than an upper surface of the fin 202. The MOS devices may be PMOS devices or NMOS devices.
The substrate 201 may be, for example, an elemental semiconductor substrate such as a silicon substrate or a germanium substrate, or a compound semiconductor substrate such as gallium arsenide. The material of the fin 202 may be the same semiconductor material as the material of the substrate 201 or may be a different semiconductor material than the material of the substrate 201. The material of the isolation region 203 may be, for example, a dielectric material such as silicon oxide.
As shown in fig. 3A and 3B, a dummy gate structure is formed on the initial substrate structure. The dummy gate structure includes a dummy gate dielectric layer 301 on a portion of the fin 202 and a dummy gate 302 on the dummy gate dielectric layer 301. For example, a dummy gate dielectric layer 301 may first be formed over a portion of the fin 202; a dummy gate material layer (not shown) is then formed on the dummy gate dielectric layer 301; then forming a patterned hard mask layer 203 on the dummy gate material layer; the dummy gate material layer is then patterned using the hard mask layer 203 as a mask to form a dummy gate 302. In one embodiment, the material of the dummy gate dielectric layer 301 may include silicon oxide, etc., and the material of the dummy gate 302 may include polysilicon, etc. The hard mask layer 303 may typically be silicon nitride or the like.
As shown in fig. 4A and 4B, an interlayer dielectric layer 401 is deposited, and then the deposited interlayer dielectric layer 401 is planarized to remove the hard mask layer 303 and expose the dummy gate 302.
As shown in fig. 5A and 5B, the dummy gate 302 and the dummy gate dielectric layer 301 are removed, thereby forming a trench 501, the trench 501 exposing a portion of the fin 202.
As shown in fig. 6A and 6B, a gate dielectric layer 601 and a work function metal layer 602 are sequentially deposited. In one embodiment, gate dielectric layer 601 may be a high-k dielectric layer, such as hafnium oxide or the like. In one embodiment, a cap layer, a barrier layer, or the like may also be formed between the gate dielectric layer 601 and the work function metal layer 602.
In one embodiment, the MOS device may be a PMOS device and the work function metal layer 602 may include one or more of TiN, TaC, and MoN. In another embodiment, the MOS device may be an NMOS device and the work function metal layer 602 may comprise one or more of TiAl, TaC, and Al. However, the application is not limited thereto, and the work function metal layer 602 may be other suitable materials capable of adjusting the work function of the gate structure of the device.
Referring to fig. 6A and 6B, a substrate structure may be formed that includes a substrate 201, a fin 202 for a MOS device on the substrate 201, and an isolation region 203 on the substrate 201 around the fin 202, an upper surface of the isolation region 203 being lower than an upper surface of the fin 202.
The substrate structure may further include an interlayer dielectric layer 401 over the isolation region 203 and the fins 202, the interlayer dielectric layer 401 having a trench 501 exposing a portion of the fins 202.
The substrate structure may also include a gate dielectric layer 601 on the top and sides of the exposed portions of fins 202 and a work function metal layer 602 on the gate dielectric layer 601. In one embodiment, there may be other material layers between the gate dielectric layer 601 and the work function metal layer 602, such as a cap layer, a barrier layer, and the like.
It is understood that there may also be a gate dielectric layer 601 and a work function metal layer 602 on the bottom and sidewalls of trench 501.
Returning to fig. 1, at step 104, the workfunction metal layer 602 is ion implanted to increase the threshold voltage of the MOS device, as shown in fig. 7. For example, the work function metal layer 602 on the upper surface and the side surface of the exposed portion of the fin 202 may be ion-implanted, or only the work function metal layer 602 on the upper surface of the exposed portion of the fin 202 may be ion-implanted.
Preferably, the ion implantation may be performed only on the work function metal layer 602 on the upper surface of the exposed portion of the fin 202 to reduce the electric field strength at the top of the fin 202 during operation of the MOS device. More preferably, the work function metal layer 602 on the upper surface of the region of the exposed portion of the fin 202 close to the interlayer dielectric layer 401 (i.e., the overlapping region of the gate and the source/drain region formed later) may be ion implanted to reduce the electric field strength of the overlapping region of the gate and the source/drain region when the MOS device is in operation. In one embodiment, ion implantation may be performed using the interlayer dielectric layer 401 as a mask, so as to better perform ion implantation of the work function metal layer 602 on the upper surface of the region of the exposed portion of the fin 202 close to the interlayer dielectric layer 401.
Preferably, the implantation energy of the ion implantation is relatively small, such as less than 5KeV, e.g., 2KeV, 4KeV, etc. Preferably, an angle between an implantation direction of the ion implantation and a normal line of the interlayer dielectric layer 401 may be 0 to 20 degrees, for example, 5 degrees, 10 degrees, 15 degrees, or the like. More preferably, the angle between the implantation direction of the ion implantation and the normal line of the interlayer dielectric layer 401 is 0 to 20 degrees, and the implantation direction of the ion implantation is substantially parallel to the side surface of the fin 202, so that only the work function metal layer 602 on the upper surface of the fin 202 is implanted as much as possible, and the work function metal layer 602 on the side surface of the fin 202 is not implanted or implanted with a small amount of impurities.
For NMOS devices, the ion implanted impurities may include one or more of the following: n, F, C, As and La. For PMOS devices, the ion implanted impurities may include one or more of Al and Ga. However, it should be understood that the present application is not limited to the examples of the impurities given above as long as the impurities implanted by the ion implantation can increase the threshold voltage of the NMOS device or the PMOS device.
After ion implantation, a metal gate may be formed on the work function metal layer 602.
The method of manufacturing a semiconductor device according to one embodiment of the present application is described above. In the manufacturing method of the embodiment, after the work function metal layer is formed, the work function metal layer is subjected to ion implantation capable of increasing the threshold voltage of the MOS device, so that the electric field intensity of the MOS device in a fin during operation is reduced, and the reliability of the MOS device is improved.
The method for adjusting the threshold voltage of the device by ion implantation of the work function metal layer provided by the embodiment is suitable for both NMOS devices and PMOS devices. In addition, for the process of simultaneously manufacturing the NMOS device and the PMOS device, the threshold voltages of the NMOS device and the PMOS device may also be adjusted in the above manner. This is explained below with reference to the embodiment shown in fig. 8.
Fig. 8 is a simplified flow diagram of a method of fabricating a semiconductor device according to another embodiment of the present application.
First, in step 802, a substrate structure is provided.
The substrate structure may include a substrate, a first fin for a PMOS device and a second fin for an NMOS device on the substrate, and an isolation region on the substrate around the first fin and the second fin, an upper surface of the isolation region being lower than an upper surface of the first fin and the second fin.
The substrate structure may also include an interlayer dielectric layer over the isolation region and the first and second fins. The inter-level dielectric layer has a first trench exposing a first portion of the first fin and a second trench exposing a second portion of the second fin.
The substrate structure may further include a gate dielectric layer on upper surfaces and sides of the first and second portions and a first work function metal layer on the gate dielectric layer. The gate dielectric layer is preferably a high-k dielectric layer. The first workfunction metal layer may comprise one or more of: TiN, TaC, MoN.
The gate dielectric layer and the first work function metal layer may be provided on the bottom and the sidewall of the first trench and the second trench.
Next, at step 804, a first ion implantation is performed on the first workfunction metal layer to increase the threshold voltage of the PMOS device. The impurity implanted by the first ion implantation may include one or more of Al and Ga.
Preferably, the first ion implantation is performed only to the first work function metal layer on the upper surfaces of the first and second portions. More preferably, the first ion implantation is performed on the first work function metal layer on the upper surface of the region of the first portion and the second portion near the interlayer dielectric layer (i.e., the region overlapping the source/drain regions). In one embodiment, the first ion implantation may be performed with the interlayer dielectric layer as a mask.
Preferably, the implantation energy of the first ion implantation may be less than 5KeV, such as 2KeV, 4KeV, or the like. Preferably, the angle between the implantation direction of the first ion implantation and the normal of the interlayer dielectric layer may be 0-20 degrees, for example, 5 degrees, 10 degrees, 15 degrees, etc. More preferably, the angle between the implantation direction of the first ion implantation and the normal of the interlayer dielectric layer is 0-20 degrees, and the implantation direction of the first ion implantation is substantially parallel to the side surfaces of the first fins, so that only the first work function metal layers on the upper surfaces of the first fins and the second fins can be implanted as far as possible, and the first work function metal layers on the side surfaces of the first fins and the second fins are not implanted or implanted with a small amount of impurities.
Then, at step 806, after the first ion implantation is performed, the first work function metal layer on the upper surface and the side surface of the second portion is removed, thereby exposing the gate dielectric layer on the second portion.
Thereafter, at step 808, a second work function metal layer is formed on the first work function metal layer on the upper surface and sides of the first portion and the gate dielectric layer on the upper surface and sides of the second portion. The second workfunction metal layer may comprise one or more of: TiAl, TaC and Al.
Thereafter, at step 810, a second ion implantation is performed on the second workfunction metal layer to increase the threshold voltage of the NMOS device. The impurities implanted by the second ion implantation may include one or more of the following: n, F, C, As and La.
Thereafter, the first trench and the second trench may be filled with a metal gate, thereby forming a gate for an NMOS device and a gate for a PMOS device.
Preferably, the second ion implantation is performed only to the second work function metal layer on the upper surfaces of the first and second portions. More preferably, the second ion implantation is performed on the second work function metal layer on the upper surface of the region where the first portion and the second portion are close to the interlayer dielectric layer. In one embodiment, the second ion implantation may be performed with the interlayer dielectric layer as a mask.
Preferably, the implantation energy of the second ion implantation may be less than 5KeV, e.g., 2KeV, 4KeV, etc. Preferably, the angle between the implantation direction of the second ion implantation and the normal of the interlayer dielectric layer may be 0-20 degrees, such as 5 degrees, 10 degrees, 15 degrees, and the like. More preferably, the angle between the injection direction of the second ion injection and the normal of the interlayer dielectric layer is 0-20 degrees, and the injection direction of the second ion injection is basically parallel to the side surface of the second fin, so that only the second work function metal layer on the upper surface of the first fin and the second fin can be injected as far as possible, and the second work function metal layer on the side surface of the first fin and the second fin is not injected or is injected with little impurity.
In the above embodiment, after the first work function metal layer is formed, the first work function metal layer is subjected to first ion implantation capable of increasing the threshold voltage of the PMOS device, so that the electric field intensity of the PMOS device in the first fin during operation is reduced, and the reliability of the PMOS device is improved. In addition, after the second work function metal layer is formed, second ion implantation capable of increasing the threshold voltage of the NMOS device is carried out on the second work function metal layer, so that the electric field intensity of the NMOS device in the first fin during working is reduced, and the reliability of the NMOS device is improved.
So far, the method of manufacturing the semiconductor device according to the embodiment of the present application has been described in detail. Some details which are well known in the art have not been described in order to avoid obscuring the concepts of the present application, and it will be fully apparent to those skilled in the art from the above description how the technical solutions disclosed herein may be implemented. In addition, the embodiments taught by the present disclosure can be freely combined. It will be appreciated by persons skilled in the art that numerous modifications may be made to the embodiments described above without departing from the spirit and scope of the present application as defined by the appended claims.

Claims (22)

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate structure, the substrate structure comprising:
a substrate, a first electrode and a second electrode,
a fin for a MOS device on the substrate,
isolation regions on the substrate surrounding the fins, an upper surface of the isolation regions being lower than an upper surface of the fins,
an interlayer dielectric layer on the isolation region and the fin, the interlayer dielectric layer having a trench exposing a portion of the fin,
a gate dielectric layer on the upper surface and sides of the exposed portion of the fin, an
A work function metal layer on the gate dielectric layer; and
and performing ion implantation on the work function metal layer to increase the threshold voltage of the MOS device, so that the electric field intensity of the MOS device in the fin during working is reduced.
2. The method of claim 1, wherein said ion implanting is performed on a workfunction metal layer on an upper surface of said exposed portion.
3. The method of claim 2, wherein said ion implanting is performed on a work function metal layer on an upper surface of an area of said exposed portion proximate to said interlevel dielectric layer.
4. The method of claim 1, wherein the ion implantation is performed with the inter-level dielectric layer as a mask.
5. The method of claim 1, wherein said ion implantation has an implantation energy of less than 5 KeV.
6. The method of claim 1, wherein an angle between an implantation direction of the ion implantation and a normal of the interlayer dielectric layer is 0-20 degrees.
7. The method of claim 6, wherein the ion implantation is performed in a direction parallel to the sides of the fins.
8. The method of claim 1, wherein the MOS device is a PMOS device.
9. The method of claim 8, wherein the ion implantation implanted impurities comprise one or more of: al and Ga.
10. The method of claim 8, wherein the work function metal layer comprises one or more of: TiN, TaC, MoN.
11. The method of claim 1, wherein the MOS device is an NMOS device.
12. The method of claim 11, wherein the ion implantation implanted impurities comprise one or more of: n, F, C, As and La.
13. The method of claim 11, wherein the work function metal layer comprises one or more of: TiAl, TaC and Al.
14. A method for manufacturing a semiconductor device, comprising:
providing a substrate structure, the substrate structure comprising:
a substrate, a first electrode and a second electrode,
a first fin for a PMOS device and a second fin for an NMOS device on the substrate,
an isolation region on the substrate surrounding the first fin and the second fin, an upper surface of the isolation region being lower than an upper surface of the first fin and the second fin,
an interlayer dielectric layer over the isolation region, the first fin, and the second fin, the interlayer dielectric layer having a first trench exposing a first portion of the first fin and a second trench exposing a second portion of the second fin,
a gate dielectric layer on upper surfaces and side surfaces of the first and second portions, an
A first work function metal layer on the gate dielectric layer;
performing first ion implantation on the first work function metal layer to increase the threshold voltage of the PMOS device, so as to reduce the electric field intensity of the PMOS device in the first fin during operation;
removing the first work function metal layer on the upper surface and the side surface of the second part after the first ion implantation is performed;
forming a second work function metal layer on the first work function metal layer on the upper surface and the side of the first portion and the gate dielectric layer on the upper surface and the side of the second portion; and
and performing second ion implantation on the second work function metal layer to increase the threshold voltage of the NMOS device, so that the electric field intensity of the NMOS device in the second fin is reduced when the NMOS device works.
15. The method of claim 14,
performing the first ion implantation to the first work function metal layer on the upper surfaces of the first and second portions;
performing the second ion implantation on a second work function metal layer on upper surfaces of the first and second portions.
16. The method of claim 15,
performing the first ion implantation on the first work function metal layer on the upper surface of the region of the first part and the second part close to the interlayer dielectric layer;
and performing the second ion implantation on the second work function metal layer on the upper surface of the region of the first part and the second part close to the interlayer dielectric layer.
17. The method of claim 14, wherein the first ion implantation and the second ion implantation are performed with the interlayer dielectric layer as a mask.
18. The method of claim 14 wherein the first and second ion implantations have an implantation energy of less than 5 KeV.
19. The method of claim 14,
an angle between an injection direction of the first ion injection and a normal of the interlayer dielectric layer is 0-20 degrees;
an angle between an implantation direction of the second ion implantation and a normal of the interlayer dielectric layer is 0-20 degrees.
20. The method of claim 19,
the injection direction of the first ion injection is parallel to the side face of the first fin;
the implantation direction of the second ion implantation is parallel to the side face of the second fin.
21. The method of claim 14,
the first ion implantation of impurities comprises one or more of the following: al, Ga;
the second ion implantation implant impurities include one or more of: n, F, C, As and La.
22. The method of claim 14,
the first workfunction metal layer comprises one or more of: TiN, TaC, MoN;
the second workfunction metal layer comprises one or more of: TiAl, TaC and Al.
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