CN106601741A - Semiconductor device, preparation method thereof and electronic device - Google Patents
Semiconductor device, preparation method thereof and electronic device Download PDFInfo
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- CN106601741A CN106601741A CN201510673706.9A CN201510673706A CN106601741A CN 106601741 A CN106601741 A CN 106601741A CN 201510673706 A CN201510673706 A CN 201510673706A CN 106601741 A CN106601741 A CN 106601741A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000009792 diffusion process Methods 0.000 claims abstract description 32
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 184
- 238000000576 coating method Methods 0.000 claims description 104
- 239000011248 coating agent Substances 0.000 claims description 103
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 27
- 239000003292 glue Substances 0.000 claims description 15
- 239000011241 protective layer Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 9
- 238000009434 installation Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical group NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims 2
- 150000002500 ions Chemical class 0.000 abstract description 18
- 230000006870 function Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 239000010703 silicon Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 239000012212 insulator Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000003467 diminishing effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a semiconductor device, a preparation method thereof and an electronic device. The method comprises the steps that S1) a semiconductor substrate is provided, a PMOS and a memory NMOS are formed on the semiconductor substrate, grooves which are formed by removing virtual grids surrounding fins are formed in the PMOS and the memory NMOS respectively; S2) a high K dielectric layer and a first cover layer are formed on the fins, exposed out of the grooves, of the PMOS and the memory NMOS; S3) a second cover layer and a first work function layer are formed on the first cover layer of the PMOS; and S4) diffusion stopping ion implantation is carried out on the first cover layer of the memory NMOS to form a diffusion stop layer and prevent ions from diffusion. According to the method, Al in the memory NMOS is prevented from diffusing to the grid of the PMOS, and the performance and yield rate of the semiconductor device are improved.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor devices and its preparation
Method, electronic installation.
Background technology
The raising of performance of integrated circuits mainly passes through the size for constantly reducing IC-components to improve it
Speed realizing.At present, it is special because semi-conductor industry has advanced to nanometer technology process node
It is not when dimensions of semiconductor devices drops to 22nm or following, from manufacture and the challenge of design aspect
Jing result in the development of three dimensional design such as FinFET (FinFET).
Relative to existing planar transistor, the FinFET is in raceway groove control and reduces shallow channel
The aspects such as effect have more superior performance；Planar gate is arranged above the raceway groove, and
Grid described in FinFET is arranged around the fin, therefore can control electrostatic from three faces, in electrostatic
The performance of control aspect is also more prominent.
In FinFET generally with lower channel ion injection with strengthen the mobility of device with
And Random Dopant Fluctuation (RDF) performance, work-function layer is extremely important for the regulation of device, prepares in device
During generally from rear grid technique formed work-function layer, in order to meet the demand of device, for NMOS
Need to remove coating TiN/TAN and depositing Ti AL is used as work-function layer, but for SRAM devices
Part, due to the diffusion of Al, the mismatch performance of the PMOS area device for SRAM is further degenerated,
Reduce device performance and yield.
Therefore at present there is above-mentioned many drawbacks in methods described, need to be improved methods described, so as to
Eliminate the problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be in specific embodiment
Further describe in part.The Summary of the present invention is not meant to attempt to limit institute
The key feature and essential features of claimed technical scheme, does not more mean that attempting determination wants
Seek the protection domain of the technical scheme of protection.
The present invention is in order to overcome the problem of presently, there are, there is provided a kind of preparation method of semiconductor devices, bag
Include：
Step S1：Semiconductor substrate is provided, PMOS and memory are formed with the semiconductor substrate
NMOS, is formed with the virtual grid removed around fin in the PMOS and the memory NMOS
The groove formed after pole；
Step S2：The PMOS exposed in the groove and the institute of the memory NMOS
State and formed on fin high k dielectric layer and the first coating；
Step S3：The second coating and the first work content are formed on first coating of the PMOS
Several layers；
Step S4：Stopping ion note is diffused to first coating of the memory NMOS
Enter, to form diffusion stop layer, prevent the diffusion of ion.
Alternatively, methods described is still further comprised：
Step S5：The PMOS the first work-function layer and the memory NMOS described
The second work-function layer and glue line are formed on one coating；
Step S6：Conductive material is deposited on the glue line, to form metal gates.
Alternatively, in step S4, to the memory NMOS in first coating
Si ion implantation is performed, to form siliceous diffusion stop layer.
Alternatively, step S3 includes：
Step S31：Formed on first coating of the PMOS and memory NMOS
Second coating and first work-function layer；
Step S32：Protective layer is formed in first work-function layer of the PMOS, to cover
State second coating and first work-function layer in PMOS；
Step S33：Remove the memory NMOS described first supratectal described second covers
Layer and first work-function layer, to expose first coating；
Step S34：Remove the protective layer.
Alternatively, in step S1, NMOS is also formed with the Semiconductor substrate, it is described to deposit
Reservoir NMOS is located between the NMOS and the PMOS；
In step S2, formed on the fin of the NMOS high k dielectric layer and
First coating；
Step S31 includes：
Step S311：The shape on first coating of the PMOS and memory NMOS
While into second coating and first work-function layer, on the fin of the NMOS
Form second coating and first work-function layer；
Step S312：The second protective layer is formed on the memory NMOS and PMOS, with
Cover the memory NMOS and PMOS；
Step S313：Remove first work-function layer on the NMOS, second coating and
First coating, to expose the high k dielectric layer.
Alternatively, in step S32, form described on the NMOS and the PMOS
Protective layer, to cover the NMOS and PMOS.
Alternatively, first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
Present invention also offers a kind of semiconductor devices, including：
Semiconductor substrate；
PMOS and memory NMOS, positioned at the top of the Semiconductor substrate；
Wherein, the grid of the memory NMOS includes that the high k dielectric layer for stacking gradually, first cover
Layer and the second work-function layer；The high k dielectric layer that the grid of the PMOS includes stacking gradually, the
One coating, the second coating, the first work-function layer and the second work-function layer；
Wherein, ion is stopped doped with diffusion in first coating of the memory NMOS,
Using as diffusion stop layer.
Alternatively, the grid of the PMOS and the memory NMOS is still further comprised positioned at described
Glue line and conductive material in second work-function layer.
Alternatively, the semiconductor devices still further comprises NMOS, and the memory NMOS is located at
Between the NMOS and the PMOS；
The grid of the NMOS includes high k dielectric layer and the second work-function layer being sequentially depositing.
Alternatively, first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
Alternatively, the diffusion stop layer is TiSiN.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor devices.
The present invention is in order to solve problems of the prior art, there is provided a kind of semiconductor devices and its system
Preparation Method, adjusted by adjusting the composition of the gate stack in the process the logic area and
The threshold voltage of the device in the active area, wherein, the memory NMOS gate lamination includes bag
Include high k dielectric layer, the first coating (TiN), the second work-function layer (TiAl), the bonding for stacking gradually
Glue-line (TiN) and conductive layer (W)；The grid of the PMOS includes that the described high K for stacking gradually is situated between
Electric layer, the first coating (TiN), the second coating (TaN), the first work-function layer (TiN), second
Work-function layer (TiN), the second work-function layer (TiAl), glue line (TiN) and conductive layer (W).
Wherein, ion is stopped doped with diffusion in first coating of the memory NMOS, to make
For diffusion stop layer, to prevent the memory NMOS in Al diffuse to the PMOS grids,
To improve the performance and yield of semiconductor devices.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Show in accompanying drawing
Embodiments of the invention and its description are gone out, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1 a-1j are the preparation process schematic diagram of semiconductor devices described in the present invention one is specifically implemented；
Fig. 2 is the process chart of the preparation of semiconductor devices described in the present invention one is specifically implemented.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without the need for one
Or multiple these details and be carried out.In other examples, in order to avoid obscuring with the present invention,
For some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and should not be construed as being limited to this
In propose embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will be originally
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He areas
Size and relative size may be exaggerated.From start to finish same reference numerals represent identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to "
When other elements or layer, its can directly on other elements or layer, it is adjacent thereto, connection or couple
To other elements or layer, or there may be element between two parties or layer.Conversely, when element is referred to as " directly
... on ", " with ... direct neighbor ", " being directly connected to " or when " being directly coupled to " other elements or layer, then
There is no element between two parties or layer.Although it should be understood that can be retouched using term first, second, third, etc.
Various elements, part, area, floor and/or part are stated, these elements, part, area, floor and/or part are not
Should be limited by these terms.These terms are used merely to distinguish element, part, area, floor or a portion
Divide and another element, part, area, floor or part.Therefore, without departing from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part, area,
Layer or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ...
On ", " above " etc., can describe for convenience here and by using so as to describe shown in figure
Individual element or feature and other elements or the relation of feature.It should be understood that except the orientation shown in figure with
Outward, spatial relationship term is intended to also include the different orientation of the device in using and operating.For example, if
Device upset in accompanying drawing, then, is described as " below other elements " or " under it " or " under it "
Element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term " ... below "
" ... under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other take
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limit of the present invention
System.When here is used, " one " of singulative, " one " and " described/should " be also intended to include plural form,
Unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " including ", when at this
When used in specification, the presence of the feature, integer, step, operation, element and/or part is determined,
But it is not excluded for one or more other features, integer, step, operation, element, part and/or group
Exist or add.When here is used, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed step and detailed knot will be proposed in following description
Structure, to explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
The present invention is in order to solve problems of the prior art, there is provided a kind of new semiconductor devices
Preparation method, is further described below in conjunction with the accompanying drawings to the method for the invention.
Wherein, Fig. 1 a-1j are the preparation process signal of semiconductor devices described in the present invention one is specifically implemented
Figure, left side figure is the profile along fin bearing of trend in Fig. 1 a-1j, and right figure is vertical
In the profile of fin bearing of trend；Fig. 2 is semiconductor devices described in the present invention one is specifically implemented
The process chart of preparation.
Execution step 101, there is provided Semiconductor substrate 101 simultaneously performs ion implanting, to form trap.
Specifically, as shown in Figure 1a, in this step the Semiconductor substrate following can be previously mentioned
At least one in material：Silicon (SSOI), absolutely is laminated on silicon, silicon-on-insulator (SOI), insulator
SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator are laminated on edge body
(GeOI) etc..
In this embodiment Semiconductor substrate 101 selects silicon.
Wherein described Semiconductor substrate can include logic area and active area, wherein, the active area can be with
Various memory devices are formed, for example, can form SRAM, formed in the active area in this embodiment
There are SRAM NMOS, in the both sides of the SRAM NMOS conventional NMOS and PMOS is formed with.
Then pad oxide skin(coating) (Pad oxide) is formed on the semiconductor substrate, wherein the pad oxidation
The forming method of nitride layer (Pad oxide) can be formed by the method for depositing, such as chemical vapor deposition,
The methods such as ald, can also be formed by the surface of Semiconductor substrate described in thermal oxide, and here is not
Repeat again.
Further, the step of performing ion implanting can also be further included in this step, with described
Trap is formed in Semiconductor substrate, wherein the ionic species for injecting and method for implanting can be normal in this area
Method, here is not repeated one by one.
Methods described can further include following steps：
Step 1011：
Multiple fins are formed on a semiconductor substrate, and the width of fin is all identical, or fin is divided into tool
There are multiple fins groups of different in width.
Specifically, the forming method of the fin is not limited to a certain kind, is given below a kind of exemplary
Forming method：Hard mask layer (not shown) is formed on a semiconductor substrate, forms the hard mask
Layer can adopt the various suitable technique that those skilled in the art are familiar with, such as chemical vapor deposition work
Skill, the hard mask layer can be the oxide skin(coating) and silicon nitride layer being laminated from bottom to top；Patterning is described
Hard mask layer, formed for etch Semiconductor substrate to be formed on fin it is multiple be isolated from each other cover
Film, in one embodiment, using patterning process described in self-aligned double patterning case (SADP) process implementing；
Etch Semiconductor substrate to be formed on fin structure.
Step 1012：
Depositing isolation material layer, to cover the fin structure.
Specifically, depositing isolation material layer, with the gap being filled up completely between fin structure.In a reality
In applying example, the deposition is implemented using the chemical vapor deposition method with flowable.Spacer material layer
Material can be with selective oxidation thing, such as HARP.
Then spacer material layer described in etch-back, to the object height of the fin.Specifically, etch-back
The spacer material layer, with fin described in exposed portion, and then forms the fin with certain height.
Step 1013：
Dummy gate oxide skin(coating) 104 and dummy gate 103 are formed on the spacer material layer, to cover
Cover the fin.
Specifically, as shown in Figure 1a, dummy gate oxide skin(coating) and dummy gate material are deposited in this step
The bed of material.
Wherein, the dummy gate oxide skin(coating) can select conventional oxide, such as SiO2, it is described
Dummy gate material layer can select semi-conducting material commonly used in the art, for example, can select polysilicon etc.,
It is not limited to a certain kind, here will not enumerate,
The deposition process of the gate material layers can be from the side such as chemical vapor deposition or ald
Method.
Then the dummy gate oxide skin(coating) and gate material layers are patterned, to be formed around the fin
Dummy gate.Specifically, photoresist layer is formed in the dummy gate material layer, then exposes aobvious
Shadow, to form opening, then with the photoresist layer as mask etch described in dummy gate material layer, with
NMOS dummy gates are formed in the logic area NMOS and active area NMOS, is had described
PMOS dummy gates are formed in source region PMOS.
Step 1014：
Skew side wall and clearance wall are formed on the side wall of the dummy gate structure.
Specifically, methods described may further include the NMOS dummy gates and PMOS is virtual
The both sides of grid form offset side wall (offset spacer).The material of the offset side wall is, for example, silicon nitride,
The insulating materials such as silica or silicon oxynitride.With further diminishing for device size, the raceway groove of device
Length is less and less, and the particle of source-drain electrode injection depth is also less and less, the effect of offset side wall be with
The channel length of the transistor for being formed is improved, the heat for reducing short-channel effect and causing due to short-channel effect
Carrier effect.The technique for forming offset side wall in grid structure both sides can be chemical vapor deposition, this
In embodiment, the thickness of the offset side wall may diminish to 80 angstroms.
Alternatively, the NMOS dummy gates and PMOS dummy gates both sides perform LDD from
Sub- implantation step is simultaneously activated.
Alternatively, it is inclined with the PMOS dummy gates on the clearance wall of the NMOS dummy gates
Move on side wall and form clearance wall.
Specifically, clearance wall (Spacer) is formed on the offset side wall for being formed, the clearance wall can be with
Constitute for a kind of in silica, silicon nitride, silicon oxynitride or their combinations.As the one of the present embodiment
Middle embodiment, the clearance wall is silica, silicon nitride is collectively constituted, and concrete technology is：Partly leading
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on body substrate, then using erosion
Carving method forms clearance wall.
Step 1015：
The injection of source and drain LDD is performed, and in the both sides epitaxial growth of semiconductor material layer of the dummy gate,
To form lifting source and drain.
Specifically, the method that ability is commonly used can be used in this step to perform the injection of source and drain LDD, here
Repeat no more.
Alternatively, the first groove is formed in the Semiconductor substrate of the PMOS dummy gates both sides,
Alternatively, first groove is " ∑ " connected in star, in this step can be from described in dry etching
PMOS source drain region, can select CF in the dry etching4、CHF3, in addition plus N2、CO2、
O2In one kind as etching atmosphere, wherein gas flow be CF410-200sccm,
CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure is
30-150mTorr, etching period is 5-120s.
Then, the stressor layers of epitaxial growth first in first groove, to form PMOS source leakage.
Further, in the present invention first stressor layers select SiGe, and in the present invention the extension can
With from reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy, molecular beam epitaxy
In one kind.
Further, the second groove is formed in the Semiconductor substrate of the NMOS dummy gates both sides,
And in second groove stressor layers of epitaxial growth second, to form NMOS source and drain.
Second stressor layers can select SiC layer, can select reduced pressure epitaxy, low-temperature epitaxy, selection
One kind in extension, liquid phase epitaxy, hetero-epitaxy, molecular beam epitaxy forms second stressor layers.
Additionally, methods described still further comprises the step of forming contact etch stop layer, the formation
Method can select various methods commonly used in the art, will not be described here.
Alternatively, can also again perform ion implanting step and carry out rapid thermal annealing.
Depth and the horizontal proliferation of impurity can be suppressed again in order to demonstrate,prove activator impurity in the present invention, institute has been performed
State and carry out after ion implanting rapid thermal annealing, alternatively, the rapid thermal annealing temperature is 1000-1050
℃。
Step 1016：
Deposit the interlayer dielectric layer 102 and planarize, to fill the gap between the dummy gate.
Specifically, interlevel dielectric deposition 102 and planarize, planarize it is described to interlayer dielectric layer to institute
State the top of dummy gate.
Wherein, the interlayer dielectric layer can select dielectric material commonly used in the art, such as various oxygen
Compound etc., in this embodiment interlayer dielectric layer 102 can select SiO2, its thickness is not limited to certain
One numerical value.
The non-limiting examples of the planarization process include that mechanical planarization method and chemically mechanical polishing are flat
Smoothization method.
Execution step 102, removes the dummy gate oxide skin(coating) 104 and the dummy gate 103, with
Formed in the logic area NMOS, the active area NMOS and the active area PMOS respectively
The groove.
Specifically, as shown in Figure 1 b, the dummy gate 103 and institute can be simultaneously removed in this step
State dummy gate oxide skin(coating) 104, it is also possible to first remove the dummy gate 103, it is then described virtual again
Gate oxide level 104.
In this embodiment, the dummy gate 103 is removed first.
Specifically, as shown in Figure 1 b, the dummy gate is removed, forms groove.The method of the removal
Can be photoetching and etching.Gas used includes HBr in etching process, and it is used as main etch gas
Body；Also include the O as etching make-up gas2Or Ar, it can improve the quality of etching.
Then the dummy gate oxide skin(coating) 104 is removed from the method for SiCoNi, to expose the fin
Piece.Remove during the dummy gate oxide skin(coating) to other materials layer to reduce in this step
Damage, be no longer etched from HF, but select selective higher SiCoNi processing procedures, by institute
State method and remove the dummy gate oxide skin(coating), device will not be caused to damage.
Alternatively, the dummy gate oxide skin(coating) 102 is removed from SiCoNi processing procedures, wherein, it is described
The various parameters of SiCoNi processing procedures can select conventional parameter.
Execution step 103, forms boundary layer, high K and is situated between in the Semiconductor substrate and the groove
The coating 106 of electric layer 105 and first.
In this step, boundary layer is formed on the surface of the fin by the method for chemical oxidation.
Specifically, as illustrated in figure 1 c, in this step the method for the chemical oxidation can be oxygen containing
Heated in atmosphere, to aoxidize the Semiconductor substrate exposed, formed on the semiconductor substrate
Oxide skin(coating), using as boundary layer.
Alternatively, the oxygen-containing atmosphere can be pure oxygen, air, oxygen-enriched air or ozone, not limit to
In a certain kind.
In this embodiment, chemical oxidation is carried out to the Semiconductor substrate 101 from ozone, forms boundary
Surface layer.
Further, the temperature and time of the chemical oxide is not limited to a certain scope, can select
Conventional parameter.
High k dielectric layer 105 is formed in the boundary layer.Specifically, as illustrated in figure 1 c, first described
High k dielectric layer 105 is deposited in virtual opening, wherein the high k dielectric layer can select commonly used in the art
Dielectric material, such as in Hf02It is middle to introduce the elements such as Si, Al, N, La, Ta and optimize each element
Ratio is come hafnium for obtaining etc..The method for forming the high k dielectric layer can be physical vapour deposition (PVD)
Technique or atom layer deposition process.
In an embodiment of the present invention, Hf0 is formed in a groove2Dielectric layer, its thickness is 15 to 60 angstroms.
Alternatively, first coating selects TiN.
In this step, the institute of NMOS, PMOS and SRAM NMOS described in the groove
State and formed on fin the high k dielectric layer and first coating
Execution step 104, on first coating of the PMOS the second coating 107 is formed
With the first work-function layer 108.
Specifically, it is formed with NMOS, SRAM NMOS on the semiconductor substrate in this embodiment
And PMOS, only form the second coating and on the fin of the PMOS in this step
One work-function layer.
Specifically, it is described that the second coating and the first work content are only formed on the fin of the PMOS
Several layers of method includes：
Step A1：Formed on first coating of the PMOS and memory NMOS
Second coating 107 and first work-function layer 108, as shown in Figure 1 f；
Step A2：Protective layer is formed in first work-function layer of the PMOS, it is described to cover
Second coating 107 and first work-function layer 108 described in PMOS on fin, such as schemes
Shown in 1g；
Step A3：Remove the memory NMOS described first supratectal described second covers
Layer and first work-function layer, to expose first coating；
Step A4：Remove the protective layer.
Alternatively, the second coating and are only formed on the fin of the PMOS in this step
The method of one work-function layer can also select following methods：
Step B1：Described is formed on the fin of the PMOS and the memory NMOS
While two coatings and first work-function layer, form described on the fin of the NMOS
Second coating and first work-function layer, as shown in Figure 1 d；
Step B2：The second protective layer is formed on the memory NMOS and PMOS, to cover
The memory NMOS and PMOS is covered, as shown in fig. le；
Step B3：Remove first work-function layer on the NMOS, second coating and
First coating, to expose the high k dielectric layer, as shown in fig. le.
Step B4：Protective layer is formed on the fin of the PMOS and NMOS,
To cover second coating 107 and first work-function layer described in the PMOS on fin
108, as shown in Figure 1 g；
Step B5：Remove second coating and the institute on the fin of the memory NMOS
The first work-function layer is stated, to expose first coating；
Step B6：Remove the protective layer.
Execution step 105, first coating of the memory NMOS is diffused stopping from
Son injection, to form diffusion stop layer, prevents the boundary of the PMOS and the memory NMOS
The diffusion of ion.
Specifically, as shown in figure 1h, the region in this step beyond the memory NMOS is formed
Protective layer, only exposes first coating of the memory NMOS, then performs diffusion and stops ion note
Enter, to form diffusion stop layer.
Specifically, border performs Si ion implantation in first coating of the NMOS, with described
Siliceous diffusion stop layer is formed in first coating.
In this step the position of the Si ion implantation is located at first coating of the NMOS, described
Ion implantation energy needs are sufficiently large, and the silicon atom for enabling reaches the position of desired depth, alternatively,
In this step the energy of the ion implanting is 20～30KeV.
Wherein, first coating selects TiN, then perform the expansion formed after Si ion implantation
Scattered stop-layer is TiSiN.
The present invention stops ion in first coating of the memory NMOS doped with diffusion,
Using as diffusion stop layer, to prevent the memory NMOS in Al diffuse to the PMOS grid
Pole, to improve the performance and yield of semiconductor devices.
Execution step 106, the second work-function layer in the NMOS, in first work(of the PMOS
The second work-function layer 109 is formed on first coating of function layer and the memory NMOS
With glue line 110.
Specifically, as shown in figure 1i, wherein, second work-function layer 109 selects TiAl, described viscous
Gum deposit layer 110 selects TiN.
Execution step 107, on the glue line conductive material is deposited, to cover the glue line
Fill the groove simultaneously.
Specifically, as shown in fig. ij, in this step the glue line selects TiN, the conduction material
Material selects metal, such as W.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Upper
After stating step, other correlation steps can also be included, here is omitted.Also, except above-mentioned step
Outside rapid, the preparation method of the present embodiment can be among above-mentioned each step or between different step
Including other steps, these steps can be realized by various techniques of the prior art, herein not
Repeat again.
Execution step 105,
With reference to Fig. 2, the process chart that the present invention prepares the semiconductor devices is illustrated therein is, be used for
The flow process of whole manufacturing process is schematically illustrated, is comprised the following steps：
Step S1：Semiconductor substrate is provided, PMOS and memory are formed with the semiconductor substrate
NMOS, is formed with the virtual grid removed around fin in the PMOS and the memory NMOS
The groove formed after pole；
Step S2：The PMOS exposed in the groove and the institute of the memory NMOS
State and formed on fin high k dielectric layer and the first coating；
Step S3：The second coating and the first work content are formed on first coating of the PMOS
Several layers；
Step S4：Stopping ion note is diffused to first coating of the memory NMOS
Enter, to form diffusion stop layer, prevent the diffusion of ion.
Embodiment two
Present invention also offers a kind of semiconductor devices, the semiconductor devices is from described in embodiment one
It is prepared by method.
Semiconductor substrate；
PMOS and memory NMOS, positioned at the top of the Semiconductor substrate, wherein, the storage
The grid of device NMOS includes high k dielectric layer, the first coating and the second work-function layer for stacking gradually；
The grid of the PMOS includes that the high k dielectric layer for stacking gradually, the first coating, second cover
Layer, the first work-function layer and the second work-function layer；
Wherein, ion is stopped doped with diffusion in first coating of the memory NMOS,
Using as diffusion stop layer.
Alternatively, the grid of the PMOS and the memory NMOS is still further comprised positioned at described
Glue line and conductive material in second work-function layer.
Alternatively, the semiconductor devices still further comprises NMOS, and the memory NMOS is located at
Between the NMOS and the PMOS；
The grid of the NMOS includes high k dielectric layer and the second work-function layer being sequentially depositing.
Alternatively, first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
Alternatively, the diffusion stop layer selects TiCAl.
Wherein, the semiconductor devices include Semiconductor substrate 101, the Semiconductor substrate can be with
Under at least one in the material that is previously mentioned：Silicon is laminated on silicon, silicon-on-insulator (SOI), insulator
(SSOI), on insulator be laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) with
And germanium on insulator (GeOI) etc..In this embodiment Semiconductor substrate 101 selects silicon.
Specifically, multiple fins are formed with a semiconductor substrate, and the width of fin is all identical, or
Fin is divided into the multiple fins groups with different in width.
The semiconductor devices still further comprises the metal gate structure arranged around the fin, described
Formed on the side wall of metal-gate structures and offset side wall and clearance wall.
The material of the offset side wall is, for example, the insulating materials such as silicon nitride, silica or silicon oxynitride.
With further diminishing for device size, the channel length of device is less and less, the particle injection of source-drain electrode
Depth is also less and less, and the effect of offset side wall is to improve the channel length of the transistor of formation, subtract
Little short-channel effect and the hot carrier's effect caused due to short-channel effect.
Clearance wall (Spacer) is formed with the offset side wall for being formed, the clearance wall can be oxidation
A kind of or their combinations in silicon, silicon nitride, silicon oxynitride are constituted.
Lifting source and drain is formed with the both sides of the grid structure.Wherein, PMOS source leakage selects SiGe,
The NMOS source and drain selects SiC layer.
The grid structure includes boundary layer, in the present invention from ozone to the Semiconductor substrate 101
Chemical oxidation is carried out, boundary layer is formed.
Wherein, the memory NMOS gate lamination includes stacking gradually high k dielectric layer,
One coating (TiN), the second work-function layer (TiAl), glue line (TiN) and conductive layer (W)；
The grid of the PMOS include stack gradually the high k dielectric layer, the first coating (TiN),
Second coating (TaN), the first work-function layer (TiN), the second work-function layer (TiAl), glue line
And conductive layer (W) (TiN).
The grid of the NMOS includes the high k dielectric layer and the second work-function layer for stacking gradually
(TiAl), glue line (TiN) and conductive layer (W).
The present invention stops ion in first coating of the memory NMOS doped with diffusion,
Using as diffusion stop layer, to prevent the memory NMOS in Al diffuse to the PMOS grid
Pole, to improve the performance and yield of semiconductor devices.
Embodiment three
Present invention also offers a kind of electronic installation, including the semiconductor devices described in embodiment two.Wherein,
Semiconductor devices is the semiconductor devices described in embodiment two, or the preparation method according to embodiment one
The semiconductor devices for obtaining.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book,
Game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, MP3,
Any electronic product such as MP4, PSP or equipment, alternatively any centre including the semiconductor devices
Product.The electronic installation of the embodiment of the present invention, due to having used above-mentioned semiconductor devices, thus has
Better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
Citing and descriptive purpose are only intended to, and are not intended to limit the invention to described scope of embodiments
It is interior.In addition it will be appreciated by persons skilled in the art that the invention is not limited in above-described embodiment, root
More kinds of variants and modifications can also be made according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention is by the appended claims and its waits
Effect scope is defined.
Claims (13)
1. a kind of preparation method of semiconductor devices, including：
Step S1：Semiconductor substrate is provided, PMOS and memory are formed with the semiconductor substrate
NMOS, is formed with the virtual grid removed around fin in the PMOS and the memory NMOS
The groove formed after pole；
Step S2：The PMOS exposed in the groove and the institute of the memory NMOS
State and formed on fin high k dielectric layer and the first coating；
Step S3：The second coating and the first work content are formed on first coating of the PMOS
Several layers；
Step S4：Stopping ion note is diffused to first coating of the memory NMOS
Enter, to form diffusion stop layer, prevent the diffusion of ion.
2. method according to claim 1, it is characterised in that methods described is still further comprised：
Step S5：The PMOS the first work-function layer and the memory NMOS described
The second work-function layer and glue line are formed on one coating；
Step S6：Conductive material is deposited on the glue line, to form metal gates.
3. method according to claim 1, it is characterised in that in step S4, to institute
First coating stated in memory NMOS performs Si ion implantation, is stopped with forming siliceous diffusion
Layer.
4. method according to claim 1, it is characterised in that step S3 includes：
Step S31：Formed on first coating of the PMOS and memory NMOS
Second coating and first work-function layer；
Step S32：Protective layer is formed in first work-function layer of the PMOS, to cover
State second coating and first work-function layer in PMOS；
Step S33：Remove the memory NMOS described first supratectal described second covers
Layer and first work-function layer, to expose first coating；
Step S34：Remove the protective layer.
5. method according to claim 4, it is characterised in that described in step S1
It is also formed with NMOS in Semiconductor substrate, the memory NMOS is located at the NMOS and described
Between PMOS；
In step S2, formed on the fin of the NMOS high k dielectric layer and
First coating；
Step S31 includes：
Step S311：The shape on first coating of the PMOS and memory NMOS
While into second coating and first work-function layer, on the fin of the NMOS
Form second coating and first work-function layer；
Step S312：The second protective layer is formed on the memory NMOS and PMOS, with
Cover the memory NMOS and PMOS；
Step S313：Remove first work-function layer on the NMOS, second coating and
First coating, to expose the high k dielectric layer.
6. method according to claim 5, it is characterised in that in step S32, in institute
State and form the protective layer on the NMOS and PMOS, to cover the NMOS and described
PMOS。
7. method according to claim 1, it is characterised in that first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
8. a kind of semiconductor devices, including：
Semiconductor substrate；
PMOS and memory NMOS, positioned at the top of the Semiconductor substrate；
Wherein, the grid of the memory NMOS includes that the high k dielectric layer for stacking gradually, first cover
Layer and the second work-function layer；The high k dielectric layer that the grid of the PMOS includes stacking gradually, the
One coating, the second coating, the first work-function layer and the second work-function layer；
Wherein, ion is stopped doped with diffusion in first coating of the memory NMOS,
Using as diffusion stop layer.
9. semiconductor devices according to claim 8, it is characterised in that the PMOS and institute
State glue line that the grid of memory NMOS still further comprised in second work-function layer and
Conductive material.
10. semiconductor devices according to claim 8, it is characterised in that the semiconductor devices
Still further comprise NMOS, the memory NMOS be located at the NMOS and PMOS it
Between；
The grid of the NMOS includes high k dielectric layer and the second work-function layer being sequentially depositing.
11. semiconductor devices according to claim 8, it is characterised in that first coating
From TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
12. semiconductor devices according to claim 8 or 11, it is characterised in that the diffusion stops
Only layer is TiSiN.
A kind of 13. electronic installations, including the semiconductor devices described in one of claim 8 to 12.
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| CN109087893A (en) * | 2017-06-13 | 2018-12-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN109148290A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor device |
| CN111293118A (en) * | 2018-12-10 | 2020-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN104810368A (en) * | 2014-01-28 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Cmos transistor and forming method thereof |
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| CN104752447A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
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| CN109087893B (en) * | 2017-06-13 | 2021-06-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
| CN109148290A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor device |
| CN109148290B (en) * | 2017-06-28 | 2020-12-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN111293118A (en) * | 2018-12-10 | 2020-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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