CN109087893B - Semiconductor device, preparation method thereof and electronic device - Google Patents
Semiconductor device, preparation method thereof and electronic device Download PDFInfo
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- CN109087893B CN109087893B CN201710444083.7A CN201710444083A CN109087893B CN 109087893 B CN109087893 B CN 109087893B CN 201710444083 A CN201710444083 A CN 201710444083A CN 109087893 B CN109087893 B CN 109087893B
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- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device. The method comprises the following steps: providing a substrate, and forming a high-K dielectric layer on the substrate; performing nitridation treatment on the high-K dielectric layer to form a first nitride layer on the surface of the high-K dielectric layer; forming a first capping layer on the first nitride layer; performing nitridation treatment on the first covering layer to form a second nitridation layer on the surface of the first covering layer; and forming a second capping layer on the second nitride layer. The high-temperature operation life failure of the semiconductor device is reduced from 600ppm to less than 10 ppm.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.
Background
In the field of integrated circuit manufacturing, with the continuous shrinkage of MOS transistors, especially in processes below 32nm, various secondary effects due to the physical limits of devices are inevitable, and the scaling of the feature size of the devices becomes difficult, wherein the MOS transistor devices and the circuit manufacturing field thereof are prone to the problem of leakage from the gate to the substrate.
The solution of the current technology is to use a high-K gate material and a metal gate, wherein a Static Random Access Memory (SRAM) of the high-K metal gate becomes an indispensable important component of the on-chip Memory due to its advantages of low power consumption and high speed. The SRAM can store data as long as power is supplied to the SRAM, and the SRAM does not need to be refreshed continuously.
The reliability of SRAM is critical to ensure stable and safe operation for electrical applications, and High Temperature Operating Life (HTOL) is a commonly accepted test method to characterize the shift in threshold voltage of SRAM during stress.
The problem in the preparation of the High-K metal gate SRAM is that the High Temperature Operating Life (HTOL) performance is reduced or even fails, which becomes a biggest problem restricting the mass production of 28 HKMG.
Therefore, various disadvantages exist in the prior art, and the disadvantages become problems to be solved so as to further improve the performance and yield of the device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the defects of the prior art, the invention provides a preparation method of a semiconductor device, which comprises the following steps:
providing a substrate, and forming a high-K dielectric layer on the substrate;
performing nitridation treatment on the high-K dielectric layer to form a first nitride layer on the surface of the high-K dielectric layer;
forming a first capping layer on the first nitride layer;
performing nitridation treatment on the first covering layer to form a second nitridation layer on the surface of the first covering layer;
and forming a second capping layer on the second nitride layer.
Optionally, a soaking annealing step is performed after the nitridation treatment of the high-K dielectric layer and before the formation of the first capping layer.
Optionally, the temperature of the soaking annealing is 100-500 ℃ and the time is not more than 100 s.
Optionally, the high-K dielectric layer is subjected to a nitriding treatment in an atmosphere containing nitrogen in an amount of not more than 30%, the nitriding treatment time being not more than 500 seconds, so as to form the first nitride layer.
Optionally, the first capping layer has a thickness of 5 angstroms to 15 angstroms.
Optionally, a soaking annealing step is performed after the nitridation treatment of the first capping layer and before the formation of the second capping layer.
Optionally, the temperature of the soaking annealing is 100-500 ℃ and the time is not more than 100 s.
Optionally, the first capping layer is subjected to nitriding treatment in an atmosphere having a nitrogen content of not more than 30%, and the nitriding treatment time is not more than 500 seconds, to form the second nitride layer.
Optionally, the second capping layer has a thickness of 15 angstroms to 25 angstroms.
Optionally, the substrate includes a pull-up transistor region and a pull-down transistor region, wherein the high-K dielectric layer and the first capping layer in the pull-up transistor region are nitrided.
The present invention also provides a semiconductor device including:
a substrate;
a high-K dielectric layer on the substrate, wherein the high-K dielectric layer includes a first nitride layer on a top surface;
a first capping layer on the first nitride layer, wherein the first capping layer includes a second nitride layer on a top surface;
a second capping layer on the second nitride layer.
Optionally, the first capping layer has a thickness of 5 angstroms to 15 angstroms;
the thickness of the second covering layer is 15-25 angstroms.
The invention also provides an electronic device comprising the semiconductor device.
In summary, in the semiconductor device of the present invention, the high-K dielectric layer is subjected to a nitridation process before the formation of the capping layer in the manufacturing process to form a first nitride layer on the surface of the high-K dielectric layer, and the nitridation process can greatly reduce the high-K dielectric layer (e.g., HfO)2) The probability of extracting the covering layer by the medium O atoms is improved, and the performance of the covering layer is improved. The stability and reliability of the device are improved. And the cover layer is formed by two stepsAnd adding nitridation treatment between the two steps to enable the covering layer to form a structure similar to a sandwich structure, so that the stability of the covering layer is further improved. Wherein the High Temperature Operating Life (HTOL) failure of the semiconductor device is reduced from 600ppm to less than 10 ppm.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 is a flow chart illustrating a process for fabricating a semiconductor device according to an embodiment of the present invention;
FIGS. 2A to 2E are schematic cross-sectional views showing structures obtained by implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The problem of the prior art in the preparation of the SRAM including the High-K metal gate is that the performance of the High Temperature Operating Life (HTOL) is reduced or even fails, which becomes the biggest problem restricting the mass production of 28 HKMG.
To solve this problem, the applicant analyzed the cause of the performance degradation of a High Temperature Operating Life (HTOL) in which a pull-up transistor and a pull-down transistor are included in an SRAM device, which causes the High Temperature Operating Life (HTOL) performance degradation due to an excessively High threshold voltage in the pull-up transistor. Through further analysis and experiments, the reason for the overhigh threshold voltage in the pull-up transistor is found to be that: after the formation of the High-K dielectric layer and the capping layer, defects are caused in the capping layer due to extraction of oxygen atoms in the High-K dielectric layer by nitrogen in the capping layer, thereby causing a reduction in High Temperature Operating Life (HTOL) performance, resulting in a reduction in performance and yield of the entire device.
In order to solve the foregoing technical problem, the present invention provides a method for manufacturing a semiconductor device, the method including:
providing a substrate, and forming a high-K dielectric layer on the substrate;
performing nitridation treatment on the high-K dielectric layer to form a first nitride layer on the surface of the high-K dielectric layer;
forming a first capping layer on the first nitride layer;
performing nitridation treatment on the first covering layer to form a second nitridation layer on the surface of the first covering layer;
and forming a second capping layer on the second nitride layer.
In addition, the present invention also provides a semiconductor device including:
a substrate;
a high-K dielectric layer on the substrate, wherein the high-K dielectric layer includes a first nitride layer on a top surface;
a first capping layer on the high-K dielectric layer, wherein the first capping layer includes a second nitride layer on a top surface;
a second cover layer on the first cover layer.
In summary, in the semiconductor device of the present invention, the high-K dielectric layer is subjected to a nitridation process before the formation of the capping layer in the manufacturing process to form a first nitride layer on the surface of the high-K dielectric layer, and the nitridation process can greatly reduce the high-K dielectric layer (e.g., HfO)2) The probability of extracting the covering layer by the medium O atoms is improved, and the performance of the covering layer is improved. The stability and reliability of the device are improved. And the covering layer is formed by two steps and a nitridation treatment is added between the two steps, so that the covering layer forms a structure similar to a sandwich structure, and the covering layer is further improvedAnd (4) stability. Wherein the High Temperature Operating Life (HTOL) failure of the semiconductor device is reduced from 600ppm to less than 10 ppm.
Example one
A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings, and fig. 1 shows a flow chart of a manufacturing process of the semiconductor device according to the present invention; fig. 2A to 2E are schematic cross-sectional views showing structures obtained by implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention.
The invention provides a preparation method of a semiconductor device, which comprises the following steps of:
step S1: providing a substrate, and forming a high-K dielectric layer on the substrate;
step S2: performing nitridation treatment on the high-K dielectric layer to form a first nitride layer on the surface of the high-K dielectric layer;
step S3: forming a first capping layer on the first nitride layer;
step S4: performing nitridation treatment on the first covering layer to form a second nitridation layer on the surface of the first covering layer;
step S5: and forming a second capping layer on the second nitride layer.
The method for manufacturing the semiconductor device will be further described with reference to the accompanying drawings.
First, step one is performed to provide a substrate 201 on which a high-K dielectric layer 203 is formed.
The semiconductor device in this application includes an SRAM memory cell, and certainly, other elements may be further included in addition to the SRAM memory cell, which is not further described herein.
The SRAM memory cell of the invention can be a six-unit transistor (6T) which comprises six metal oxide semiconductor transistors. The 6T SRAM cell includes two identical and cross-coupled inverters forming a latch circuit, e.g., the output of one inverter is connected to the input of the other inverter. The latch circuit is connected between a power supply and ground.
Wherein each inverter comprises an NMOS pull-down transistor and a PMOS pull-up transistor, for example wherein the left inverter comprises an NMOS pull-down transistor PDL and a PMOS pull-up transistor PUL; the inverter on the left side includes an NMOS pull-down transistor PDR and a PMOS pull-up transistor PUR.
The output of the inverter serves as two storage nodes. The complementary bit line pair is coupled to the storage node through a pair of transmission gate NMOS transistors.
The improvements in the present invention are made to the pull-up transistor, and of course the pull-down transistor can be made with the same improvements, as described in detail below.
Specifically, as shown in fig. 2A, the substrate 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like.
The substrate 201 may include a pull-up transistor region, a pull-down transistor region, and a pass-gate transistor region, each of which may be formed with a different type of transistor.
The preparation of the pull-up transistor, the pull-down transistor and the transmission gate transistor can be carried out simultaneously, only the pull-up transistor region and the transmission gate transistor region are covered in the nitridation step, and the nitridation treatment can be carried out completely.
Optionally, doped regions and/or isolation structures, which are Shallow Trench Isolation (STI) structures or local oxidation of silicon (LOCOS) isolation structures, and other active devices, may be formed in the substrate 201.
The pull-up transistor, the pull-down transistor and the transmission gate transistor use metal gates, wherein a back gate process can be selected as a forming method of the metal gates, and the preparation process comprises the following steps: a dummy gate layer is formed on the substrate.
In particular, the dummy gate layer includes, but is not limited to, silicon, polysilicon, doped polysilicon, and polysilicon-germanium alloy materials (i.e., having a doping concentration of from about 1 x 1018 to about 1 x 1022 doping atoms per cubic centimeter), and polysilicon metal silicide (polycide) materials (doped polysilicon/metal silicide stack materials).
The forming method of the polysilicon gate material can select a Low Pressure Chemical Vapor Deposition (LPCVD) process. The process conditions for forming the polysilicon layer include: the reaction gas is silane (SiH4), and the flow rate of the silane can be 100-200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature in the reaction cavity can be 700-750 ℃; the pressure in the reaction chamber can be 250-350 mTorr, such as 300 mTorr; the reaction gas may further include a buffer gas, the buffer gas may be helium (He) or nitrogen, and the flow rate of the helium and the nitrogen may range from 5 to 20 liters per minute (slm), such as 8slm, 10slm, or 15 slm.
And patterning the virtual gate layer to form a virtual gate.
Specifically, in the embodiment of the present invention, a patterned photoresist layer is first formed on the gate material layer, where the photoresist layer defines the shape and the critical dimension of the virtual gate, the gate material layer is etched using the photoresist layer as a mask, a pattern is transferred to the gate material layer, and then the photoresist layer is removed to form the virtual gate, where the removal method of the photoresist layer may be an oxidation ashing method, or may be other methods commonly used in the art, and details are not repeated here.
Further, optionally, offset sidewalls and spacers may also be formed on the dummy gate.
Specifically, a material layer of offset sidewalls is conformally deposited (conformal deposition) on the dummy gate, and after the substrate and the material layer of the offset sidewalls on the level of the dummy gate are removed by etching, the offset sidewalls are formed, wherein the offset sidewalls are made of an oxide, such as silicon oxide, and the oxide is formed by an Atomic Layer Deposition (ALD) method.
Forming a spacer on the offset sidewall, wherein the gate spacer may be SiO2SiN, SiOCN, or a combination thereof. Optionally, the gate spacerThe silicon oxide and the silicon nitride are jointly formed, and the specific process comprises the following steps: and depositing a silicon oxide layer and a silicon nitride layer, and then forming a gate gap wall by adopting an etching method. The thickness of the gate spacer is 5-50 nm.
Depositing an interlayer dielectric layer and flattening the interlayer dielectric layer to the virtual grid.
The interlayer dielectric layer is made of an oxide, such as silicon dioxide, ethyl orthosilicate, and the like, but not limited to one.
Optionally, the interlayer dielectric layer is formed by FCVD (fluid chemical vapor deposition).
Then, the interlayer dielectric layer is planarized until the dummy gate is exposed, and the planarization method may be a method commonly used in the art.
And removing the dummy gate to form a groove.
Specifically, dry etching or wet etching is selected to remove the dummy gate:
when dry etching is selected, HBr may be selected as the main etching gas; and further comprises O as an etching supplementary gas2Or Ar, which may improve the quality of the etch. Or wet etching is selected.
When wet etching is selected, one or more of KOH and tetramethylammonium hydroxide (TMAH) are selected, KOH is selected for etching in the invention, KOH with the mass fraction of 5-50% can be selected for etching in the invention, and the temperature of the etching process is strictly controlled, wherein the etching temperature in the step is 20-60 ℃.
An interfacial layer 202 is then formed, wherein the interfacial layer may be formed by a rapid thermal annealing oxidation process (RTO) or by a deposition process to form SiON. In this embodiment the interface layer is formed in the recess.
Such as a rapid thermal annealing oxidation (RTO) method to oxidize the substrate. Specifically, the rapid thermal oxidation step may be performed by using a conventional rapid thermal oxidation method, and in one embodiment of the present invention, O is used2Or contain O2Is carried out at a temperature of 800-150 DEG CAnd at 0 ℃, 1100 ℃ and 1200 ℃ optionally, the treatment time is 2-30min, and an oxide layer with a certain thickness is formed on the substrate through the treatment.
Then, a high-K dielectric layer 203 is formed on the interfacial layer 202, as shown in fig. 2A, wherein the high-K dielectric layer 203 is selected from HfZrOx or HfO2。
The high-K dielectric layer 203 may be deposited by one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) using Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like. Chemical Vapor Deposition (CVD) is preferred in the present invention.
And performing a second step of performing nitridation treatment on the high-K dielectric layer to form a first nitride layer 204 on the surface of the high-K dielectric layer.
Specifically, as shown in fig. 2B, the high-K dielectric layer is subjected to a nitridation treatment, in the present invention, only the high-K dielectric layer in the PMOS pull-up transistor is subjected to a nitridation treatment through covering of a mask layer during the preparation process, so as to form a first nitride layer 204 on the surface of the high-K dielectric layer, and the first nitride layer 204 can prevent oxygen in the high-K dielectric layer from being extracted by the capping layer formed in the subsequent process, thereby preventing the threshold voltage of the PMOS pull-up transistor from becoming large.
The method for performing nitridation treatment on the high-K dielectric layer to achieve the purpose comprises the following steps:
forming a patterned mask layer to cover the region where the NMOS pull-down transistor and the transmission gate NMOS transistor are formed and expose the region of the PMOS pull-up transistor;
in the invention, the high-K dielectric layer in the exposed PMOS pull-up transistor region is subjected to nitridation treatment.
Wherein, an ion implantation mask is used in the nitridation treatment, and only one ion implantation mask needs to be added, so that the process manufacturing cost is not increased.
In this step, the high-K dielectric layer is subjected to nitriding treatment in an atmosphere having a nitrogen content of 30% or less, wherein the nitriding treatment time is not more than 500 seconds, to form the first nitride layer.
In order to better form the first nitride layer, an annealing process may be further performed after the nitridation process and before the first capping layer is formed.
For example, a soak anneal (soak anneal) step may be performed after the nitridation process is performed on the high-K dielectric layer and before the first capping layer is formed.
Wherein the temperature of soaking annealing is 100-500 ℃, and the time is not more than 100 s.
Step three is performed to form a first capping layer 205 on the first nitride layer.
Specifically, as shown in fig. 2C, a first capping layer is formed on the high-K dielectric layer in this step, and the material of the first capping layer includes titanium nitride or tantalum nitride, and the capping layer is formed to prevent diffusion of the metal material in the metal gate structure into the high-K dielectric layer, so as to adjust the threshold voltage of the semiconductor device.
The deposition of the first capping layer may be one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like. Chemical Vapor Deposition (CVD) is preferred in the present invention.
Optionally, the first capping layer has a thickness of 5 angstroms to 15 angstroms.
Step four is executed to perform nitridation processing on the first cladding layer, so as to form a second nitride layer 206 on the surface of the first cladding layer.
Specifically, as shown in fig. 2D, the first capping layer is subjected to a nitridation process, and in the present invention, only the first capping layer in the PMOS pull-up transistor is subjected to a nitridation process through the coverage of a mask layer during the manufacturing process, so as to form a second nitride layer 206 on the surface of the first capping layer, and the second nitride layer 206 can prevent oxygen in any material layer above the second nitride layer from being extracted by the capping layer formed in a subsequent process, so as to prevent the threshold voltage of the PMOS pull-up transistor from becoming large.
The method for performing nitridation treatment on the first covering layer to achieve the above object comprises the following steps:
forming a patterned mask layer to cover the region where the NMOS pull-down transistor and the transmission gate NMOS transistor are formed and expose the region of the PMOS pull-up transistor;
in the present invention, the first capping layer in the exposed region of the PMOS pull-up body transistor is nitrided.
Wherein, an ion implantation mask is used in the nitridation treatment, and only one ion implantation mask needs to be added, so that the process manufacturing cost is not increased.
In this step, the first capping layer is subjected to nitriding treatment in an atmosphere having a nitrogen content of 30% or less, wherein the nitriding treatment time is not more than 500 seconds, to form the second nitride layer.
In order to better form the second nitride layer, an annealing process may be further performed after the nitridation process and before the second capping layer is formed.
For example, a soaking annealing (soak annealing) step is performed after the nitridation process is performed on the first capping layer and before the second capping layer is formed.
Wherein the temperature of soaking annealing is 100-500 ℃, and the time is not more than 100 s.
Step five is executed to form a second cover layer 207 on the first cover layer.
Specifically, as shown in fig. 2E, a second capping layer, the constituent material of which includes titanium nitride or tantalum nitride, is formed on the first capping layer in this step.
The second capping layer may be deposited by one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) using Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like. Chemical Vapor Deposition (CVD) is preferred in the present invention.
Optionally, the second capping layer has a thickness of 15 angstroms to 25 angstroms.
In addition, the method further comprises the step of forming a metal gate, for example:
forming a work function layer on the second capping layer;
and forming a diffusion barrier layer and a conductive layer on the work function layer to form a metal gate structure.
Optionally, the diffusion barrier layer comprises one or more of TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN.
Non-limiting examples of methods of forming the deposited barrier layer include Chemical Vapor Deposition (CVD) such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD). The diffusion barrier layer is formed to a thickness of between 10-100 angstroms.
Optionally, the diffusion barrier layer is a TiN layer.
The conductive layer may be selected from conductive materials commonly used in the art, such as copper or tungsten layers. In this embodiment, the conductive layer is formed using tungsten, which may be deposited by CVD or PVD methods.
Further, after the conductive layer is formed, annealing is performed at a temperature of 300-500 degrees celsius, for example, the time for reaction in a nitrogen-containing atmosphere is 10-60 minutes. Finally, the conducting layer is flattened to remove the conducting layer outside the groove to form the metal gate.
Thus, the description of the steps related to the fabrication of the semiconductor device of the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.
In summary, in the manufacturing process of the semiconductor device of the present invention, the high-K dielectric layer is subjected to a nitridation process before the formation of the capping layer, so as to form a first nitride layer on the surface of the high-K dielectric layer, and the high-K dielectric layer (for example, the high-K dielectric layer) can be greatly reduced by the nitridation processHfO2) The probability of extracting the covering layer by the medium O atoms is improved, and the performance of the covering layer is improved. The stability and reliability of the device are improved. And the capping layer is formed in two steps with a nitridation process added between the two steps to form the capping layer into a nearly sandwich structure. Wherein the High Temperature Operating Life (HTOL) failure of the semiconductor device is reduced from 600ppm to less than 10 ppm.
Example two
The present invention also provides a semiconductor device, as shown in fig. 2E, including:
a substrate 201;
a high-K dielectric layer 203 on the substrate, wherein the high-K dielectric layer comprises a first nitride layer 204 on a top surface;
a first capping layer 205 on the high-K dielectric layer, wherein the first capping layer includes a second nitride layer 206 on a top surface;
a second cover layer 207 on the first cover layer.
The semiconductor device in this application includes an SRAM memory cell, and certainly, other elements may be further included in addition to the SRAM memory cell, which is not further described herein.
The SRAM memory cell of the invention can be a six-unit transistor (6T) which comprises six metal oxide semiconductor transistors. The 6T SRAM cell includes two identical and cross-coupled inverters forming a latch circuit, e.g., the output of one inverter is connected to the input of the other inverter. The latch circuit is connected between a power supply and ground.
Wherein each inverter comprises an NMOS pull-down transistor and a PMOS pull-up transistor, for example wherein the left inverter comprises an NMOS pull-down transistor PDL and a PMOS pull-up transistor PUL; the inverter on the left side includes an NMOS pull-down transistor PDR and a PMOS pull-up transistor PUR.
The output of the inverter serves as two storage nodes. The complementary bit line pair is coupled to the storage node through a pair of transmission gate NMOS transistors.
The improvements in the present invention are made to the pull-up transistor, and of course the pull-down transistor can be made with the same improvements, as described in detail below.
Specifically, the substrate 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like.
The substrate 201 may include a pull-up transistor region, a pull-down transistor region, and a pass-gate transistor region, each of which may be formed with a different type of transistor.
The preparation of the pull-up transistor, the pull-down transistor and the transmission gate transistor can be carried out simultaneously, only the pull-up transistor region and the transmission gate transistor region are covered in the nitridation step, and the nitridation treatment can be carried out completely.
Optionally, doped regions and/or isolation structures, which are Shallow Trench Isolation (STI) structures or local oxidation of silicon (LOCOS) isolation structures, and other active devices, may be formed in the substrate 201.
The pull-up transistor, the pull-down transistor, and the pass-gate transistor use metal gates.
The metal gate includes an interface layer 202 on the substrate.
Then, a high-K dielectric layer 203 is formed on the interfacial layer 202, as shown in fig. 2A, wherein the high-K dielectric layer 203 is selected from HfZrOx or HfO2。
The high-K dielectric layer 203 may be deposited by one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) using Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like. Chemical Vapor Deposition (CVD) is preferred in the present invention.
A first nitride layer 204 is formed on the surface of the high-K dielectric layer.
A first nitride layer 204 is formed on the surface of the high-K dielectric layer, and the first nitride layer 204 can prevent oxygen in the high-K dielectric layer from being extracted by the capping layer formed in a subsequent process, thereby preventing the threshold voltage of the PMOS pull-up transistor from becoming large.
A first capping layer 205 is formed on the high-K dielectric layer.
The first covering layer is made of titanium nitride or tantalum nitride, and the covering layer is formed to prevent the diffusion of metal materials in the metal gate structure to the high-k dielectric layer so as to adjust the threshold voltage of the semiconductor device.
Optionally, the first capping layer has a thickness of 5 angstroms to 15 angstroms.
A second nitride layer 206 is formed on the surface of the first clad layer.
The second nitride layer 206 may prevent oxygen in any material layer above it from being extracted by the capping layer formed in a subsequent process, thereby preventing the threshold voltage of the PMOS pull-up transistor from becoming large.
A second cover layer 207 is formed on the first cover layer.
The constituent material of the second capping layer includes titanium nitride or tantalum nitride.
Optionally, the second capping layer has a thickness of 15 angstroms to 25 angstroms.
In addition, the method further comprises the step of forming a metal gate, for example:
forming a work function layer on the second capping layer;
and forming a diffusion barrier layer and a conductive layer on the work function layer to form a metal gate structure.
Optionally, the diffusion barrier layer comprises one or more of TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN.
Non-limiting examples of methods of forming the deposited barrier layer include Chemical Vapor Deposition (CVD) such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD). The diffusion barrier layer is formed to a thickness of between 10-100 angstroms.
Optionally, the diffusion barrier layer is a TiN layer.
The conductive layer may be selected from conductive materials commonly used in the art, such as copper or tungsten layers. In this embodiment, the conductive layer is formed using tungsten, which may be deposited by CVD or PVD methods.
EXAMPLE III
Another embodiment of the present invention provides an electronic device, which includes a semiconductor device, wherein the semiconductor device is the semiconductor device in the second embodiment or the semiconductor device manufactured by the method of manufacturing the semiconductor device in the first embodiment.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor, for example: a mobile phone mainboard with the integrated circuit, and the like.
Wherein figure 3 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset includes the aforementioned semiconductor device, the semiconductor device including: a substrate; a high-K dielectric layer on the substrate, wherein the high-K dielectric layer includes a first nitride layer on a top surface; a first capping layer on the high-K dielectric layer, wherein the first capping layer includes a second nitride layer on a top surface; a second cover layer on the first cover layer.
In summary, in the semiconductor device manufacturing process of the present invention, the first nitride layer is formed on the surface of the high-K dielectric layer before the capping layer is formed, and the nitridation process can greatly reduce the high-K dielectric layer (e.g., HfO)2) The probability of extracting the covering layer by the medium O atoms is improved, and the performance of the covering layer is improved. The stability and reliability of the device are improved. And the capping layer is formed in two steps with a nitridation process added between the two steps,so that the cover layer forms an approximately sandwich structure. Wherein the High Temperature Operating Life (HTOL) failure of the semiconductor device is reduced from 600ppm to less than 10 ppm.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate, and forming a high-K dielectric layer on the substrate, wherein the high-K dielectric layer is positioned in a groove for forming a metal gate;
performing nitridation treatment on the high-K dielectric layer to form a first nitride layer on the surface of the high-K dielectric layer, wherein the first nitride layer prevents oxygen in the high-K dielectric layer from being extracted by a covering layer formed in a subsequent process;
forming a first capping layer on the first nitride layer;
performing nitridation treatment on the first covering layer to form a second nitridation layer on the surface of the first covering layer;
and forming a second covering layer on the second nitride layer, wherein the first covering layer, the second nitride layer and the second covering layer form a sandwich-like structure.
2. The method of claim 1, wherein a soaking anneal step is performed after the nitridation process to the high-K dielectric layer and before the first capping layer is formed.
3. The method according to claim 2, wherein the soaking annealing is performed at a temperature of 100 ℃ to 500 ℃ for a time of not more than 100 s.
4. The method of claim 1, wherein the high-K dielectric layer is nitrided in an atmosphere having a nitrogen content of not more than 30% for a time of not more than 500 seconds to form the first nitride layer.
5. The method of claim 1, wherein the first capping layer has a thickness of 5 angstroms to 15 angstroms.
6. The method of claim 1, wherein a soaking anneal step is performed after the nitridation process is performed on the first capping layer and before the second capping layer is formed.
7. The method according to claim 6, wherein the soaking annealing is performed at a temperature of 100 ℃ to 500 ℃ for a time of not more than 100 s.
8. The method according to claim 1, wherein the first capping layer is subjected to nitriding treatment in an atmosphere having a nitrogen content of not more than 30% for not more than 500 seconds to form the second nitride layer.
9. The method of claim 1, wherein the second capping layer has a thickness of 15-25 angstroms.
10. The method of claim 1, wherein the substrate comprises a pull-up transistor region and a pull-down transistor region, and wherein the high-K dielectric layer and the first capping layer in the pull-up transistor region are nitrided.
11. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate having a metal gate formed thereon, the metal gate comprising:
the high-K dielectric layer is positioned on the substrate and comprises a first nitride layer positioned on the top surface, and the first nitride layer prevents oxygen in the high-K dielectric layer from being extracted by a covering layer formed in a subsequent process;
a first capping layer on the first nitride layer, wherein the first capping layer includes a second nitride layer on a top surface;
and the second covering layer is positioned on the second nitriding layer, and the first covering layer, the second nitriding layer and the second covering layer form a sandwich-like structure.
12. The semiconductor device according to claim 11, wherein a thickness of the first cap layer is 5 to 15 angstroms;
the thickness of the second covering layer is 15-25 angstroms.
13. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 11 to 12.
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