CN109087893A - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN109087893A CN109087893A CN201710444083.7A CN201710444083A CN109087893A CN 109087893 A CN109087893 A CN 109087893A CN 201710444083 A CN201710444083 A CN 201710444083A CN 109087893 A CN109087893 A CN 109087893A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic device.The described method includes: providing substrate, it is formed with high k dielectric layer on the substrate；Nitrogen treatment is carried out to the high k dielectric layer, to form the first nitration case on the surface of the high k dielectric layer；The first coating is formed on first nitration case；Nitrogen treatment is carried out to first coating, to form the second nitration case on the surface of first coating；The second coating is formed on second nitration case.The high-temperature operation life failure of the semiconductor devices is decreased to less than 10ppm by 600ppm.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
In IC manufacturing field, with the continuous diminution of MOS transistor, especially in 32nm technique below,
Second-order effect brought by the various physics limits because of device is inevitable, and the characteristic size of device is scaled to become tired
Difficulty, wherein MOS transistor device and its circuit manufacturing field are easy to appear the electrical leakage problems from grid to substrate.
The solution of current process is the method using high-K gate material and metal gate, wherein high-K metal gate
SRAM (Static Random Access Memory, static random access memory) is become with the advantages of its low-power consumption, high speed
Indispensable important component in on-chip memory.As long as SRAM can be reserved for data for its power supply, without constantly to it
Refreshed.
It is vital, high temperature behaviour for the operation of stabilization and safety of the reliability of SRAM for guaranteeing electrical application
Making the service life (High Temperature Operating Life, HTOL) is to be generally accepted a kind of test method, is used to table
Levy the offset of the SRAM threshold voltage in stress path.
It is high-temperature operation service life (High Temperature in the problem of preparation of the SRAM of high-K metal gate
Operating Life, HTOL) performance decline even failure, become the biggest problem for restricting 28HKMG volume production.
Therefore, various drawbacks are existed in the prior art, the problem of above-mentioned drawback becomes urgent need to resolve, to further increase device
The performance and yield of part.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of preparation methods of semiconductor devices, which comprises
Substrate is provided, is formed with high k dielectric layer on the substrate；
Nitrogen treatment is carried out to the high k dielectric layer, to form the first nitration case on the surface of the high k dielectric layer；
The first coating is formed on first nitration case；
Nitrogen treatment is carried out to first coating, to form the second nitration case on the surface of first coating；
The second coating is formed on second nitration case.
Optionally, soaking is executed to after high k dielectric layer progress nitrogen treatment, before forming first coating
Annealing steps.
Optionally, the temperature of the equal thermal annealing is 100 DEG C -500 DEG C, and the time is no more than 100s.
Optionally, nitrogen treatment, the nitridation are carried out to the high k dielectric layer in atmosphere of the nitrogen content no more than 30%
Handling the time is no more than 500 seconds, to form first nitration case.
Optionally, first coating with a thickness of 5 angstroms -15 angstroms.
Optionally, equal to being executed after first coating progress nitrogen treatment, before forming second coating
Thermal anneal step.
Optionally, the temperature of the equal thermal annealing is 100 DEG C -500 DEG C, and the time is no more than 100s.
Optionally, nitrogen treatment, and institute are carried out to first coating in atmosphere of the nitrogen content no more than 30%
Stating the nitrogen treatment time is no more than 500 seconds, to form second nitration case.
Optionally, second coating with a thickness of 15 angstroms -25 angstroms.
Optionally, the substrate includes pull up transistor region and pull-down transistor region, wherein to the upper crystal pulling
The high k dielectric layer and first coating in the domain of area under control carry out nitrogen treatment.
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes:
Substrate；
High k dielectric layer is located in the substrate, wherein the high k dielectric layer includes the first nitridation positioned at top surface
Layer；
First coating is located on first nitration case, wherein first coating includes being located at top surface
Second nitration case；
Second coating is located on second nitration case.
Optionally, first coating with a thickness of 5 angstroms -15 angstroms；
Second coating with a thickness of 15 angstroms -25 angstroms.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
In conclusion semiconductor devices of the present invention is during the preparation process situated between to the high K before forming coating
Electric layer carries out nitrogen treatment, can be big by the nitrogen treatment to form the first nitration case on the surface of the high k dielectric layer
It is big to reduce high k dielectric layer (such as HfO2) in O atom be coated cap rock extraction probability, improve the performance of coating.Improve device
The stability and reliability of part.And the coating is formed by two steps and increases nitrogen treatment between two steps, so that
The coating forms the structure of approximate sandwich, further increases the stability of the coating.The wherein semiconductor device
High-temperature operation service life (High Temperature Operating Life, the HTOL) failure of part is decreased to less than by 600ppm
10ppm。
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the preparation technology flow chart of semiconductor devices described in one embodiment of the invention；
The preparation method that Fig. 2A -2E shows semiconductor device described in one embodiment of the invention implements obtained structure
Diagrammatic cross-section；
Fig. 3 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention
Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge
Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
Technique is high-temperature operation service life (High in the problem of preparation of the SRAM including high-K metal gate at present
Temperature Operating Life, HTOL) performance decline even failure, become a maximum for restricting 28HKMG volume production
Problem.
In order to solve this problem, applicant to the high-temperature operation service life (High Temperature Operating Life,
HTOL the reason of) performance declines is analyzed, and includes pulling up transistor and pull-down transistor, and cause height in SRAM device
The reason of warm operation lifetime (High Temperature Operating Life, HTOL) performance declines is in pulling up transistor
Threshold voltage is excessively high.The excessively high reason of middle threshold voltage that pulls up transistor is caused by further analyzing and testing discovery
It is then: after forming high k dielectric layer and coating, since the oxygen atom in high k dielectric layer is coated the nitrogen extraction in cap rock,
Defect is caused in the coating, thus cause the high-temperature operation service life (High Temperature Operating Life,
HTOL) performance declines, and reduces the performance of entire device and yield.
In order to solve aforementioned technical problem, the present invention provides a kind of preparation method of semiconductor devices, the method packet
It includes:
Substrate is provided, is formed with high k dielectric layer on the substrate；
Nitrogen treatment is carried out to the high k dielectric layer, to form the first nitration case on the surface of the high k dielectric layer；
The first coating is formed on first nitration case；
Nitrogen treatment is carried out to first coating, to form the second nitration case on the surface of first coating；
The second coating is formed on second nitration case.
In addition, the present invention also provides a kind of semiconductor devices, the semiconductor devices includes:
Substrate；
High k dielectric layer is located in the substrate, wherein the high k dielectric layer includes the first nitridation positioned at top surface
Layer；
First coating is located on the high k dielectric layer, wherein first coating includes being located at top surface
Second nitration case；
Second coating is located on first coating.
In conclusion semiconductor devices of the present invention is during the preparation process situated between to the high K before forming coating
Electric layer carries out nitrogen treatment, can be big by the nitrogen treatment to form the first nitration case on the surface of the high k dielectric layer
It is big to reduce high k dielectric layer (such as HfO2) in O atom be coated cap rock extraction probability, improve the performance of coating.Improve device
The stability and reliability of part.And the coating is formed by two steps and increases nitrogen treatment between two steps, so that
The coating forms the structure of approximate sandwich, further increases the stability of the coating.The wherein semiconductor device
High-temperature operation service life (HighTemperature Operating Life, the HTOL) failure of part is decreased to less than by 600ppm
10ppm。
Embodiment one
Below with reference to the accompanying drawings the preparation method of semiconductor devices of the invention is described in detail, Fig. 1 shows the present invention
The preparation technology flow chart of the semiconductor devices；Fig. 2A -2E shows semiconductor device described in one embodiment of the invention
Preparation method implement the diagrammatic cross-section of obtained structure.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the preparation method of the semiconductor devices
Include:
Step S1: substrate is provided, is formed with high k dielectric layer on the substrate；
Step S2: carrying out nitrogen treatment to the high k dielectric layer, to form the first nitrogen on the surface of the high k dielectric layer
Change layer；
Step S3: the first coating is formed on first nitration case；
Step S4: carrying out nitrogen treatment to first coating, to form second on the surface of first coating
Nitration case；
Step S5: the second coating is formed on second nitration case.
The preparation method of the semiconductor devices is further described with reference to the accompanying drawing.
Firstly, executing step 1, substrate 201 is provided, is formed with high k dielectric layer 203 on the substrate.
Wherein, the semiconductor devices includes SRAM memory cell in this application, except of course that SRAM storage is single
Member can further include other elements, no longer further be repeated herein.
SRAM memory cell of the present invention can be six cell transistors (6T) comprising six metal oxides are partly led
Body transistor.6T sram cell includes two identical and the coupling that intersects phase inverters, and phase inverter forms latch cicuit, such as
The output of one phase inverter is connected with the input of another phase inverter.The latch cicuit is connected between power supply and ground.
Wherein, each phase inverter includes NMOS pull-down transistor and PMOS pull-up transistor, such as wherein left side is anti-
Phase device includes NMOS pull-down transistor PDL and PMOS pull-up transistor PUL；The phase inverter in left side includes NMOS pull-down transistor
PDR and PMOS pull-up transistor PUR.
The output of phase inverter is as two memory nodes.Paratope line is coupled to by a pair of of transmission gate NMOS transistor
On memory node.
Described in the present invention to improve for the progress that pulls up transistor, certain pull-down transistor can carry out together
The improvement of sample is described in detail to done in pulling up transistor below.
Specifically, as shown in Figure 2 A, the substrate 201 can be following at least one of the material being previously mentioned: silicon, absolutely
Silicon (SOI) on edge body is laminated silicon (SSOI), SiGe (S-SiGeOI) and germanium on insulator is laminated on insulator on insulator
SiClx (SiGeOI) etc..
It wherein, may include pull up transistor region, pull-down transistor region and transmission gate crystal in the substrate 201
Area under control domain will form different types of transistor in each area.
It is wherein described pull up transistor, the preparation of pull-down transistor and transmission gate transistor can be while carry out,
Only pull up transistor described in covering in nitriding step region and transmission gate transistor region, naturally it is also possible to all be nitrogenized
Processing.
Optionally, doped region and/or isolation structure be could be formed in the substrate 201, the isolation structure is
Shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure and other active devices.
It is described pull up transistor, pull-down transistor and transmission gate transistor are using metal gates, wherein the metal gate
Grid technique after the forming method of pole can be selected, preparation process include: to form dummy gate layer on the substrate.
Specifically, the dummy gate layer is closed including but not limited to silicon, polysilicon, the polysilicon of doping and polycrystalline silicon-germanium
Golden material (that is, the doping concentration with the foreign atom from per cubic centimeter about 1 × 1018 to about 1 × 1022) and more
Crystal silicon metal silicide (polycide) material (polysilicon of doping/metal silicide laminated material).
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of the polysilicon gate material.Form institute
It is silane (SiH4) that the process conditions for stating polysilicon layer, which include: reaction gas, and the range of flow of the silane can be 100~200
Cc/min (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；React cavity pressure
It can be 250~350mTorr, such as 300mTorr；It may also include buffer gas in the reaction gas, the buffer gas can be
The range of flow of helium (He) or nitrogen, the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or
15slm。
The dummy gate layer is patterned, to form dummy gate.
Specifically, in an embodiment of the present invention, patterned photoresist layer is formed in the gate material layers first,
The photoresist layer defines the shape and critical size of the dummy gate, using the photoresist layer as described in mask etch
Gate material layers, transfer a pattern in the gate material layers, then remove the photoresist layer, form dummy gate, institute
The minimizing technology for stating photoresist layer can select oxidative ashing method, can also select other methods commonly used in the art, herein
It repeats no more.
Further, optionally, offset side wall and clearance wall can also be formed on the dummy gate.
Specifically, on the dummy gate conformal deposited (conformal deposition) offset side wall material
Layer forms offset side wall, deviates side after the material layer of the offset side wall on etching removal substrate and dummy gate horizontal plane
Wall selects oxide, such as silica, the oxide to be formed by the method for atomic layer deposition (ALD).
Clearance wall is formed on the offset side wall, the grid gap wall can be SiO2, it is a kind of in SiN, SiOCN or
Their combinations of person are constituted.Optionally, the grid gap wall is silica, silicon nitride collectively constitutes, specifically comprises the processes of: deposition oxygen
Then SiClx layer, silicon nitride layer form grid gap wall using engraving method.The grid gap wall with a thickness of 5-50nm.
Interlevel dielectric deposition is simultaneously planarized to the dummy gate.
Wherein, the interlayer dielectric layer selects oxide, such as silica, ethyl orthosilicate etc., not limitation and certain
It is a kind of.
Optionally, the method that the interlayer dielectric layer selects FCVD (fluid chemistry vapor deposition) is formed.
Then the interlayer dielectric layer is planarized to the dummy gate, until exposing the dummy gate, planarization
Method can select method commonly used in the art.
The dummy gate is removed, to form groove.
Specifically, dry etching or wet etching is selected to remove the dummy gate:
When selecting dry etching, HBr can be selected as main etch gas；It further include as etching make-up gas
O2Or Ar, the quality of etching can be improved.Or select wet etching.
When selecting wet etching, one or more of KOH and tetramethyl aqua ammonia (TMAH) are selected, in the present invention
It selects KOH to be etched, mass fraction can be selected to be etched for the KOH of 5-50% in the present invention, while strict control
The temperature of the etching process, etch temperature is 20-60 DEG C in this step.
Then boundary layer 202 is formed, wherein the boundary layer can be formed by rapid thermal annealing method for oxidation (RTO),
Or SiON is formed by deposition method.The boundary layer is formed in the groove in this embodiment.
Such as rapid thermal annealing method for oxidation (RTO) aoxidizes the substrate.Specifically, the rapid thermal oxidation step can be with
It selects conventional rapid thermal oxidation process to carry out, selects O in a specific embodiment of the invention2Or contain O2Atmosphere
The device is heat-treated, the heat treatment temperature is chosen as 1100-1200 DEG C at 800-1500 DEG C, and the processing time is
2-30min, being formed on the substrate by the processing has certain thickness oxide skin(coating).
Then high k dielectric layer 203 is formed on the boundary layer 202, as shown in Figure 2 A, wherein the high k dielectric layer
203 select HfZrOx or HfO2。
The deposition of the high k dielectric layer 203 can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method
Or low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selection of the formation such as atomic layer deposition (ALD) method
One of epitaxial growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
Step 2 is executed, nitrogen treatment is carried out to the high k dielectric layer, to form the on the surface of the high k dielectric layer
One nitration case 204.
Specifically, as shown in Figure 2 B, nitrogen treatment is carried out to the high k dielectric layer, in the present invention during the preparation process
Nitrogen treatment only is carried out to the high k dielectric layer in the PMOS pull-up transistor by the covering of mask layer, to be situated between in the high K
The surface of electric layer forms the first nitration case 204, and first nitration case 204 can stop the oxygen in the high k dielectric layer rear
The coating extraction formed in continuous technique, to prevent the PMOS pull-up transistor threshold voltage from becoming larger.
Include: to the method for high k dielectric layer progress nitrogen treatment to achieve the goals above
Patterned mask layer is formed, the NMOS pull-down transistor and the transmission gate NMOS transistor are formed with covering
Region, and expose the region of PMOS pull-up transistor；
The high k dielectric layer in the PMOS pull-up transistor region of exposing is carried out at nitridation in the present invention
Reason.
Wherein, ion implantation mask is used in the nitrogen treatment, it is only necessary to increase the ion implantation mask
, not will increase technique cost of manufacture.
In this step, nitrogen treatment is carried out to the high k dielectric layer in atmosphere of the nitrogen content less than or equal to 30%,
Wherein, the nitrogen treatment time is no more than 500 seconds, to form first nitration case.
In order to preferably form first nitration case, after the nitrogen treatment, formed first coating it
Before can also further execute annealing.
Such as after carrying out nitrogen treatment to the high k dielectric layer, execute soaking before forming first coating and move back
Fiery (soak anneal) step.
Wherein, the temperature of the equal thermal annealing is 100 DEG C -500 DEG C, and the time is no more than 100s.
Step 3 is executed, forms the first coating 205 on first nitration case.
Specifically, as shown in Figure 2 C, the first coating is formed on the high k dielectric layer in this step, constitutes material
Material includes titanium nitride or tantalum nitride, and the effect for forming coating is to prevent metal material in metal gate structure to high k dielectric
The diffusion of layer, to adjust the threshold voltage of the semiconductor devices.
Wherein, the deposition of first coating can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD)
(PVD) low-pressure chemical vapor deposition (LPCVD) of the formation such as method or atomic layer deposition (ALD) method, laser ablation deposition (LAD) with
And one of selective epitaxy growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
Optionally, first coating with a thickness of 5 angstroms -15 angstroms.
Step 4 is executed, nitrogen treatment is carried out to first coating, is formed with the surface in first coating
Second nitration case 206.
Specifically, as shown in Figure 2 D, nitrogen treatment is carried out to first coating, in the present invention during the preparation process
Nitrogen treatment only is carried out to the first coating in the PMOS pull-up transistor by the covering of mask layer, described first
The surface of coating forms the second nitration case 206, and second nitration case 206 can prevent in any material layer above it
The coating extraction that oxygen is formed in subsequent technique, to prevent the PMOS pull-up transistor threshold voltage from becoming larger.
Include: to the method for first coating progress nitrogen treatment to achieve the goals above
Patterned mask layer is formed, the NMOS pull-down transistor and the transmission gate NMOS transistor are formed with covering
Region, and expose the region of PMOS pull-up transistor；
First coating in the PMOS pull-up transistor region of exposing is carried out at nitridation in the present invention
Reason.
Wherein, ion implantation mask is used in the nitrogen treatment, it is only necessary to increase the ion implantation mask
, not will increase technique cost of manufacture.
In this step, first coating is carried out at nitridation in atmosphere of the nitrogen content less than or equal to 30%
Reason, wherein the nitrogen treatment time is no more than 500 seconds, to form second nitration case.
In order to preferably form second nitration case, after the nitrogen treatment, formed second coating it
Before can also further execute annealing.
Such as after carrying out nitrogen treatment to first coating, execute soaking before forming second coating and move back
Fiery (soak anneal) step.
Wherein, the temperature of the equal thermal annealing is 100 DEG C -500 DEG C, and the time is no more than 100s.
Step 5 is executed, forms the second coating 207 on first coating.
Specifically, as shown in Figure 2 E, the second coating is formed on first coating in this step, constitutes material
Material includes titanium nitride or tantalum nitride.
Wherein, the deposition of second coating can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD)
(PVD) low-pressure chemical vapor deposition (LPCVD) of the formation such as method or atomic layer deposition (ALD) method, laser ablation deposition (LAD) with
And one of selective epitaxy growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
Optionally, second coating with a thickness of 15 angstroms -25 angstroms.
In addition, the method also includes forming metal gates, such as:
Work-function layer is formed on second coating；
Diffusion barrier layer and conductive layer are formed, in the work-function layer to form metal gate structure.
Optionally, the diffusion barrier layer include one of TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or
It is a variety of.
The forming method non-limiting example on the deposition barrier layer includes chemical vapour deposition technique (CVD), such as low temperature
Learn vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasmarized
Learn vapor deposition (PECVD).The thickness of diffusion barrier layer is formed by between 10-100 angstroms.
Optionally, the diffusion barrier layer selects TiN layer.
The conductive layer can select conductive material commonly used in the art, such as copper or tungsten layer.It uses in this embodiment
Tungsten forms the conductive layer, can be deposited with the method for CVD or PVD.
Further, it after conductive layer formation, anneals under 300-500 degree celsius temperature, for example, it is nitrogenous
The time reacted in environment is 10-60 minutes.The planarization of conductive layer is finally carried out, the shape to remove conductive layer other than groove
At metal gates.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
It afterwards, can also include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
In conclusion being situated between before forming coating to the high K in the semiconductor devices preparation process of the invention
Electric layer carries out nitrogen treatment, can be big by the nitrogen treatment to form the first nitration case on the surface of the high k dielectric layer
It is big to reduce high k dielectric layer (such as HfO2) in O atom be coated cap rock extraction probability, improve the performance of coating.Improve device
The stability and reliability of part.And the coating is formed by two steps and increases nitrogen treatment between two steps, so that
The coating forms the structure of approximate sandwich.The wherein high-temperature operation service life (High of the semiconductor devices
Temperature Operating Life, HTOL) failing is decreased to less than 10ppm by 600ppm.
Embodiment two
The present invention also provides a kind of semiconductor devices, and as shown in Figure 2 E, the semiconductor devices includes:
Substrate 201；
High k dielectric layer 203 is located in the substrate, wherein the high k dielectric layer includes positioned at the first of top surface
Nitration case 204；
First coating 205 is located on the high k dielectric layer, wherein first coating includes being located at top surface
The second nitration case 206；
Second coating 207 is located on first coating.
Wherein, the semiconductor devices includes SRAM memory cell in this application, except of course that SRAM storage is single
Member can further include other elements, no longer further be repeated herein.
SRAM memory cell of the present invention can be six cell transistors (6T) comprising six metal oxides are partly led
Body transistor.6T sram cell includes two identical and the coupling that intersects phase inverters, and phase inverter forms latch cicuit, such as
The output of one phase inverter is connected with the input of another phase inverter.The latch cicuit is connected between power supply and ground.
Wherein, each phase inverter includes NMOS pull-down transistor and PMOS pull-up transistor, such as wherein left side is anti-
Phase device includes NMOS pull-down transistor PDL and PMOS pull-up transistor PUL；The phase inverter in left side includes NMOS pull-down transistor
PDR and PMOS pull-up transistor PUR.
The output of phase inverter is as two memory nodes.Paratope line is coupled to by a pair of of transmission gate NMOS transistor
On memory node.
Described in the present invention to improve for the progress that pulls up transistor, certain pull-down transistor can carry out together
The improvement of sample is described in detail to done in pulling up transistor below.
Specifically, the substrate 201 can be following at least one of the material being previously mentioned: silicon, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) and germanium on insulator SiClx are laminated on insulator
(SiGeOI) etc..
It wherein, may include pull up transistor region, pull-down transistor region and transmission gate crystal in the substrate 201
Area under control domain will form different types of transistor in each area.
It is wherein described pull up transistor, the preparation of pull-down transistor and transmission gate transistor can be while carry out,
Only pull up transistor described in covering in nitriding step region and transmission gate transistor region, naturally it is also possible to all be nitrogenized
Processing.
Optionally, doped region and/or isolation structure be could be formed in the substrate 201, the isolation structure is
Shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure and other active devices.
It is described pull up transistor, pull-down transistor and transmission gate transistor are using metal gates.
The metal gates include the boundary layer 202 in the substrate.
Then it is formed with high k dielectric layer 203 on the boundary layer 202, as shown in Figure 2 A, wherein the high k dielectric layer
203 select HfZrOx or HfO2。
The deposition of the high k dielectric layer 203 can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method
Or low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the selection of the formation such as atomic layer deposition (ALD) method
One of epitaxial growth (SEG).Preferred chemical vapor deposition (CVD) method in the present invention.
The first nitration case 204 is formed on the surface of the high k dielectric layer.
It is formed with the first nitration case 204 on the surface of the high k dielectric layer, first nitration case 204 can stop institute
The coating extraction that the oxygen in high k dielectric layer is formed in subsequent technique is stated, to prevent the PMOS pull-up transistor
Threshold voltage becomes larger.
The first coating 205 is formed on the high k dielectric layer.
The constituent material at the first coating includes titanium nitride or tantalum nitride, and the effect for forming coating is to prevent gold
Belong to diffusion of the metal material in gate structure to high k dielectric layer, to adjust the threshold voltage of the semiconductor devices.
Optionally, first coating with a thickness of 5 angstroms -15 angstroms.
The second nitration case 206 is formed on the surface of first coating.
The institute that second nitration case 206 can prevent the oxygen in any material layer above it from being formed in subsequent technique
Coating extraction is stated, to prevent the PMOS pull-up transistor threshold voltage from becoming larger.
The second coating 207 is formed on first coating.
The constituent material of second coating includes titanium nitride or tantalum nitride.
Optionally, second coating with a thickness of 15 angstroms -25 angstroms.
In addition, the method also includes forming metal gates, such as:
Work-function layer is formed on second coating；
It is formed with diffusion barrier layer and conductive layer, in the work-function layer to form metal gate structure.
Optionally, the diffusion barrier layer include one of TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or
It is a variety of.
The forming method non-limiting example on the deposition barrier layer includes chemical vapour deposition technique (CVD), such as low temperature
Learn vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasmarized
Learn vapor deposition (PECVD).The thickness of diffusion barrier layer is formed by between 10-100 angstroms.
Optionally, the diffusion barrier layer selects TiN layer.
The conductive layer can select conductive material commonly used in the art, such as copper or tungsten layer.It uses in this embodiment
Tungsten forms the conductive layer, can be deposited with the method for CVD or PVD.
Embodiment three
Another embodiment of the present invention provides a kind of electronic devices comprising semiconductor devices, the semiconductor devices are
Semiconductor devices in previous embodiment two, or half obtained by the preparation method of the semiconductor devices according to embodiment one
Conductor device.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, are also possible to have
The intermediate products of above-mentioned semiconductor, such as: the cell phone mainboard etc. with the integrated circuit.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein the mobile phone handsets include semiconductor devices above-mentioned, and the semiconductor devices includes: substrate；High K
Dielectric layer is located in the substrate, wherein the high k dielectric layer includes the first nitration case positioned at top surface；First covering
Layer is located on the high k dielectric layer, wherein first coating includes the second nitration case positioned at top surface；Second covers
Cap rock is located on first coating.
In conclusion being situated between before forming coating to the high K in the semiconductor devices preparation process of the invention
The surface of electric layer is formed with the first nitration case, can substantially reduce high k dielectric layer (such as HfO by the nitrogen treatment2) in O
Atom is coated the probability of cap rock extraction, improves the performance of coating.Improve the stability and reliability of device.And it is described to cover
Cap rock is formed by two steps and increases nitrogen treatment between two steps, so that the coating forms the knot of approximate sandwich
Structure.Wherein high-temperature operation service life (High Temperature Operating Life, the HTOL) failure of the semiconductor devices
10ppm is decreased to less than by 600ppm.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of preparation method of semiconductor devices, which is characterized in that the described method includes:
Substrate is provided, is formed with high k dielectric layer on the substrate；
Nitrogen treatment is carried out to the high k dielectric layer, to form the first nitration case on the surface of the high k dielectric layer；
The first coating is formed on first nitration case；
Nitrogen treatment is carried out to first coating, to form the second nitration case on the surface of first coating；
The second coating is formed on second nitration case.
2. the method according to claim 1, wherein to the high k dielectric layer carry out nitrogen treatment after, formed
Equal thermal anneal step is executed before first coating.
3. according to the method described in claim 2, it is characterized in that, the temperature of the equal thermal annealing be 100 DEG C -500 DEG C, the time
For no more than 100s.
4. the method according to claim 1, wherein to the high K in atmosphere of the nitrogen content no more than 30%
Dielectric layer carries out nitrogen treatment, and the nitrogen treatment time is no more than 500 seconds, to form first nitration case.
5. the method according to claim 1, wherein first coating with a thickness of 5 angstroms -15 angstroms.
6. the method according to claim 1, wherein to first coating carry out nitrogen treatment after, shape
Equal thermal anneal step is executed before at second coating.
7. according to the method described in claim 6, it is characterized in that, the temperature of the equal thermal annealing be 100 DEG C -500 DEG C, the time
For no more than 100s.
8. the method according to claim 1, wherein to described first in atmosphere of the nitrogen content no more than 30%
Coating carries out nitrogen treatment, and the nitrogen treatment time is no more than 500 seconds, to form second nitration case.
9. the method according to claim 1, wherein second coating with a thickness of 15 angstroms -25 angstroms.
10. the method according to claim 1, wherein the substrate includes pull up transistor region and lower crystal pulling
Body area under control domain, wherein in the region that pulls up transistor the high k dielectric layer and first coating carry out at nitridation
Reason.
11. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes:
Substrate；
High k dielectric layer is located in the substrate, wherein the high k dielectric layer includes the first nitration case positioned at top surface；
First coating is located on first nitration case, wherein first coating includes positioned at the second of top surface
Nitration case；
Second coating is located on second nitration case.
12. semiconductor devices according to claim 11, which is characterized in that first coating with a thickness of 5 angstrom -15
Angstrom；
Second coating with a thickness of 15 angstroms -25 angstroms.
13. a kind of electronic device, which is characterized in that the electronic device includes semiconductor described in one of claim 11 to 12
Device.
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| CN106601741A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof and electronic device |
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