CN114373681A - Manufacturing method of MOS transistor - Google Patents

Manufacturing method of MOS transistor Download PDF

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Publication number
CN114373681A
CN114373681A CN202210279755.4A CN202210279755A CN114373681A CN 114373681 A CN114373681 A CN 114373681A CN 202210279755 A CN202210279755 A CN 202210279755A CN 114373681 A CN114373681 A CN 114373681A
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China
Prior art keywords
semiconductor substrate
channel region
layer
source
mos transistor
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CN202210279755.4A
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Chinese (zh)
Inventor
陈维邦
吴志楠
郑志成
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Jingxincheng Beijing Technology Co Ltd
Nexchip Semiconductor Corp
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Jingxincheng Beijing Technology Co Ltd
Nexchip Semiconductor Corp
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Priority to CN202210279755.4A priority Critical patent/CN114373681A/en
Publication of CN114373681A publication Critical patent/CN114373681A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention provides a manufacturing method of an MOS transistor. The manufacturing method of the MOS transistor comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises source and drain regions and a channel region positioned between the source and drain regions, a gate insulating layer and a dummy gate which are stacked from bottom to top are formed on the semiconductor substrate, and the gate insulating layer and the dummy gate cover the channel region and expose the source and drain regions; and performing an ion implantation process, and forming a stress layer on the top of the semiconductor substrate in the channel region to increase the stress of the channel region. The stress layer formed on the top of the semiconductor substrate in the channel region can increase the stress of the channel region, and further the electrical property of the MOS transistor is improved.

Description

Manufacturing method of MOS transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an MOS transistor.
Background
With the development of Semiconductor technology, the size of MOS (Metal-Oxide-Semiconductor) transistors is continuously reduced, and the speed of devices and systems is increased. When the channel region of the MOS transistor is shortened to a certain extent, electrical performance problems such as a short channel effect occur in the channel region.
In an advanced process, in order to improve the electrical performance of the MOS transistor, one method is to form the MOS transistor in an epitaxial structure, but the channel region under the metal gate of the MOS transistor in the epitaxial structure has insufficient stress, and the effect of improving the electrical performance of the MOS transistor is insufficient. Another common method is to improve the electrical performance of the MOS transistor by stressing the channel region with the source and drain regions of the MOS transistor, but the electrical performance of the MOS transistor cannot be improved to a large extent.
Disclosure of Invention
The invention provides a manufacturing method of an MOS transistor, which can increase the stress of a channel region of the MOS transistor and is beneficial to improving the electrical property of the MOS transistor.
In order to achieve the above object, the method for manufacturing a MOS transistor according to the present invention includes: providing a semiconductor substrate, wherein the semiconductor substrate comprises source and drain regions and a channel region positioned between the source and drain regions, a gate insulating layer and a dummy gate which are stacked from bottom to top are formed on the semiconductor substrate, and the gate insulating layer and the dummy gate cover the channel region and expose the source and drain regions; and performing an ion implantation process, and forming a stress layer on the top of the semiconductor substrate of the channel region to increase the stress of the channel region.
Optionally, the method for performing an ion implantation process and forming a stress layer on the top of the semiconductor substrate in the channel region includes: performing an ion implantation process, and obliquely implanting dopants into the top of the semiconductor substrate of the channel region from the positions of the source and drain regions, which are close to the gate insulating layer and the dummy gate; and carrying out heat treatment, wherein the dopant is diffused and the stress layer is formed at the top of the semiconductor substrate of the channel region.
Optionally, the implantation angle of the ion implantation process is 30 ° -60 °.
Optionally, the method for performing an ion implantation process and forming a stress layer on the top of the semiconductor substrate in the channel region includes: forming a protective layer, wherein the protective layer covers the source drain region, and the upper surface of the protective layer is flush with the upper surface of the dummy grid; removing the dummy gate to expose the gate insulating layer; and performing an ion implantation process, and implanting a dopant into the top of the channel region to form the stress layer on the top of the semiconductor substrate of the channel region.
Optionally, the dopant is implanted vertically into the channel region.
Optionally, the dopant includes at least one of carbon, germanium, and tin.
Optionally, after forming the stress layer, the method for manufacturing the MOS transistor further includes: forming a protective layer, wherein the protective layer covers the source drain region, and the upper surface of the protective layer is flush with the upper surface of the dummy grid; removing the dummy gate and the gate insulating layer to expose the surface of the semiconductor substrate in the channel region; forming a high dielectric constant material layer on the channel region; forming a work function material layer on the high dielectric constant material layer; a metal gate is formed on the work function material layer.
Optionally, the material of the work function material layer includes at least one of titanium nitride, tantalum nitride, and a titanium-aluminum-based alloy.
Optionally, the method for providing the semiconductor substrate includes: forming a gate insulating layer and a dummy gate which are stacked from bottom to top on the semiconductor substrate, wherein the gate insulating layer and the dummy gate cover a channel region of the semiconductor substrate and expose a source-drain forming region of the semiconductor substrate; etching the semiconductor substrate of the source-drain forming region to form a groove by taking the dummy gate as a mask; and forming an epitaxial material layer in the groove, and carrying out doping treatment on the epitaxial material layer to form the source and drain regions, wherein the source and drain regions apply stress to the channel region.
Optionally, the MOS transistor is P-type.
According to the manufacturing method of the MOS transistor, provided semiconductor substrates comprise source and drain regions and channel regions located between the source and drain regions, gate insulating layers and dummy gates which are overlapped from bottom to top are formed on the semiconductor substrates, the gate insulating layers and the dummy gates cover the channel regions and expose the source and drain regions, then an ion implantation process is carried out, and stress layers are formed on the top of the semiconductor substrates of the channel regions, and can increase the stress of the channel regions, so that the electrical property of the MOS transistor is improved.
Furthermore, a groove is formed in a source-drain forming region of the semiconductor substrate, an epitaxial material layer is formed in the groove, the epitaxial material layer is doped to form a source-drain region, and the source-drain region applies stress to the channel region, so that the electrical property of the MOS transistor is further improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a MOS transistor according to an embodiment of the invention.
Fig. 2 to 8 are schematic views of the step-by-step structure of the method for manufacturing a MOS transistor according to an embodiment of the invention.
Description of reference numerals: 10-a semiconductor substrate; 101-a channel region; 102-source drain forming regions; 102 a-source drain regions; 11-a gate insulating layer; 12-a dummy gate; 13-a stress layer; 14-a groove; 15-a protective layer; 16-a layer of high dielectric constant material; 17-a work function material layer; 18-metal gate.
Detailed Description
The following describes a method for fabricating a MOS transistor according to the present invention in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to increase the stress of the channel region of the MOS transistor and improve the electrical performance of the MOS transistor, the present embodiment provides a method for manufacturing the MOS transistor. Fig. 1 is a flowchart of a method for manufacturing a MOS transistor according to an embodiment of the invention. As shown in fig. 1, the method for manufacturing the MOS transistor includes:
s1, providing a semiconductor substrate, wherein the semiconductor substrate comprises source and drain regions and a channel region located between the source and drain regions, a gate insulating layer and a dummy gate which are stacked from bottom to top are formed on the semiconductor substrate, and the gate insulating layer and the dummy gate cover the channel region and expose the source and drain regions;
and S2, performing an ion implantation process, and forming a stress layer on the top of the semiconductor substrate of the channel region to increase the stress of the channel region.
Fig. 2 to 8 are schematic views of the step-by-step structure of the method for manufacturing a MOS transistor according to an embodiment of the invention. A method for manufacturing a MOS transistor according to this embodiment will be described below with reference to fig. 1 to 8.
As shown in fig. 2 to 4, the semiconductor substrate 10 includes source and drain regions 102a and a channel region 101 located between the source and drain regions 102a, a gate insulating layer 11 and a dummy gate 12 stacked from bottom to top are formed on the semiconductor substrate 10, and the gate insulating layer 11 and the dummy gate 12 cover the channel region 101 and expose the source and drain regions 102 a.
In this embodiment, the semiconductor substrate 10 may be a silicon substrate. In some embodiments, the semiconductor substrate 10 may further include an epitaxial layer (EPI layer), and the semiconductor substrate 10 may be subjected to strain in order to enhance the electrical performance of the MOS transistor. In some embodiments, the semiconductor substrate 10 may comprise a silicon-on-insulator (SOI) substrate.
In this embodiment, the method for providing the semiconductor substrate 10 may include: as shown in fig. 2, a gate insulating layer 11 and a dummy gate 12 stacked from bottom to top are formed on the semiconductor substrate 10, the gate insulating layer 11 and the dummy gate 12 cover a channel region 101 of the semiconductor substrate and expose a source/drain formation region 102 of the semiconductor substrate; as shown in fig. 3, with the dummy gate 12 as a mask, etching the semiconductor substrate of the source/drain formation region 102 to form a groove 14; as shown in fig. 4, an epitaxial material layer is formed in the groove 14, and doping processing is performed on the epitaxial material layer to form the source/drain region 102a, and the source/drain region 102a may apply stress to the channel region 101.
In order that the source drain regions 102a may apply stress to the channel region 101, the material of the epitaxial material layer may include germanium (Ge); alternatively, the material of the epitaxial material layer may be a silicon material doped with germanium and/or carbon. The epitaxial material layer may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE).
In the height direction (or referred to as the thickness direction) of the semiconductor substrate 10, the height difference between the upper surface of the source/drain region 102a and the upper surface of the semiconductor substrate of the channel region 101 may be within a set range, or the upper surface of the source/drain region 102a may be close to the height of the upper surface of the semiconductor substrate of the channel region 101.
The material of the gate insulating layer 11 may include silicon oxide (SiO)2). The material of the dummy gate 12 may include polysilicon. In order to avoid forming an epitaxial material layer on the dummy gate 12, a covering material layer (not shown) may be formed on the dummy gate 12, and the covering material layer may be removed after forming the source and drain regions 102 a.
In one embodiment, the method for forming a stress layer on top of the semiconductor substrate in the channel region by performing an ion implantation process may include: as shown in fig. 5, performing an ion implantation process to implant dopants obliquely from the source-drain region 102a near the gate insulating layer 11 and the dummy gate 12 to the top of the semiconductor substrate of the channel region 101; and then carrying out heat treatment, wherein the dopant is diffused, and the stress layer 13 is formed on the top of the semiconductor substrate in the channel region, so that the stress of the channel region 101 can be increased by the stress layer 13, and the electrical property of the MOS transistor can be further improved.
By injecting dopants into the top of the semiconductor substrate of the channel region 101 in an inclined manner from the source-drain region 102a near the gate insulating layer 11 and the dummy gate 12, and performing a heat treatment after the dopant injection to form the stress layer 13, the stress of the channel region 101 can be increased without increasing a photomask, and the electrical performance of the MOS transistor can be improved. The heat treatment may include rapid thermal annealing (RTP) or laser annealing. In order to increase the amount of dopants implanted into the channel region 101, the ion implantation process may have an implantation angle of 30 ° -60 °. But not limited thereto, the implantation angle of the ion implantation process may be adjusted according to actual situations.
After forming the stress layer 13, the method for manufacturing the MOS transistor may further include: referring to fig. 6, forming a protection layer 15, where the protection layer 15 covers the source and drain regions 102a, and an upper surface of the protection layer 15 is flush with an upper surface of the dummy gate 12; removing the dummy gate 12 and the gate insulating layer 11 to expose the surface of the semiconductor substrate in the channel region 101; referring to fig. 8, a high dielectric constant material layer 16 is formed on the channel region 101; forming a work function material layer 17 on the high dielectric constant material layer 16; and forming a metal gate 18 on the work function material layer 17.
In another embodiment, the method of performing an ion implantation process to form a stress layer on the top of the semiconductor substrate in the channel region 101 may include: as shown in fig. 6, forming a protection layer 15, where the protection layer 15 covers the source and drain regions 102a, and an upper surface of the protection layer 15 may be flush with an upper surface of the dummy gate 12; as shown in fig. 7, the dummy gate 12 is removed to expose the gate insulating layer 11; and performing an ion implantation process, and implanting a dopant into the top of the semiconductor substrate of the channel region 101 to form the stress layer 13 on the top of the semiconductor substrate of the channel region 101. In this embodiment, when the stress layer 13 is formed, the protective layer 15 may be used as a mask for ion implantation, which is helpful to save a photomask and reduce the manufacturing cost of the MOS transistor; in addition, the stress layer 13 formed in this way is distributed more uniformly in the channel region 101, so that the stress distribution of the channel region 101 is more uniform, which is beneficial to improving the electrical performance of the MOS transistor. In this embodiment, the dopant may be vertically implanted into the channel region 101, which is beneficial to improving the distribution uniformity of the formed stress layer 13 in the channel region 101. But is not limited thereto, the dopant may also be implanted obliquely into the channel region 101.
Note that the material of the protective layer 15 may include silicon oxide. The method of forming the protective layer 15 may include: forming a protective material layer (not shown in the figure) on the semiconductor substrate 10, wherein the protective material layer covers the source drain region 102a and the dummy gate 12; the protection material layer is planarized (e.g., chemical mechanical polishing) and stops on the upper surface of the dummy gate 12, the remaining protection material layer is used as the protection layer 15, and the upper surface of the protection layer 15 is flush with the upper surface of the dummy gate 12.
In some embodiments, the dopant may include at least one of carbon (C), germanium (Ge), and tin (Sn).
After forming the stress layer 13, the method for manufacturing the MOS transistor may further include: referring to fig. 7, the gate insulating layer 11 is removed to expose the surface of the semiconductor substrate of the channel region 101; referring to fig. 8, a high dielectric constant material layer 16 is formed on the channel region 101; forming a work function material layer 17 on the high dielectric constant material layer 16; a metal gate 18 is formed on the work function material layer 17.
It should be noted that the gate structure of the MOS transistor formed in the present embodiment includes the high dielectric constant material layer 16, the work function material layer 17, and the metal gate 18, which is helpful for improving the electrical performance of the MOS transistor, relative to the dummy gate structure composed of the gate insulating layer and the polysilicon layer.
In this embodiment, the material of the high-k material layer 16 may include hafnium oxide (HfO)2). In other embodiments, the material of the high-k material layer 16 may further include Al2O3、ZrO2、La2O3And TiO2 At least one of (1).
The work function material layer 17 may be a multilayer structure in which different material layers are stacked. The material of the work function material layer 17 may include at least one of titanium nitride (TiN), tantalum nitride (TaN), and titanium aluminum based alloy (TiAl). In some embodiments, the work-function material layer 17 may further include TaC, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax、NiTax、MoNx、TiSiN、TiCN、TaAlC、TiAlN、PtSix、Ni3Si, HfRu and RuOxAnd the like. The work function material layer 17 may be formed using an atomic layer deposition process. But not limited thereto, the work function material layer 17 may also be formed by other methods known in the art.
The material of the metal gate 18 may include tungsten (W). But not limited thereto, the material of the metal gate 18 may also be other metals such as aluminum (Al) or copper (Cu). The metal gate 18 may be formed using methods known in the art.
In an embodiment, after the stress layer 13 is formed on the top of the semiconductor substrate in the channel region 101, the gate insulating layer 11 may not be removed, and the work function material layer 17 and the metal gate 18 may be directly formed on the gate insulating layer 11 to form the gate structure of the MOS transistor.
In this embodiment, the MOS transistor may be a P-type. Research shows that the stress layer 13 is formed on the top of the semiconductor substrate of the channel region 101 of the P-type MOS transistor, so that the electron mobility of the channel region 101 can be improved by 10% -25%, and the improvement of the electrical performance of the MOS transistor is facilitated. But not limited thereto, the MOS transistor may also be of N-type.
In the manufacturing method of the MOS transistor in this embodiment, the provided semiconductor substrate 10 includes source and drain regions 102a and a channel region 101 located between the source and drain regions 102a, a gate insulating layer 11 and a dummy gate 12 which are stacked from bottom to top are formed on the semiconductor substrate 10, the gate insulating layer 11 and the dummy gate 12 cover the channel region 101 and expose the source and drain regions 102a, then an ion implantation process is performed, and a stress layer 13 is formed on the top of the semiconductor substrate of the channel region 101, and the stress layer 13 can increase the stress of the channel region 101, thereby facilitating the improvement of the electrical performance of the MOS transistor.
It should be appreciated that reference throughout this application to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of ordinary skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments without conflict.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims (10)

1. A method for manufacturing a MOS transistor is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises source and drain regions and a channel region positioned between the source and drain regions, a gate insulating layer and a dummy gate which are stacked from bottom to top are formed on the semiconductor substrate, and the gate insulating layer and the dummy gate cover the channel region and expose the source and drain regions; and
and performing an ion implantation process, and forming a stress layer on the top of the semiconductor substrate of the channel region to increase the stress of the channel region.
2. The method of claim 1, wherein the performing an ion implantation process to form a stress layer on top of the semiconductor substrate in the channel region comprises:
performing an ion implantation process, and obliquely implanting dopants into the top of the semiconductor substrate of the channel region from the positions of the source and drain regions, which are close to the gate insulating layer and the dummy gate;
and carrying out heat treatment, wherein the dopant is diffused and the stress layer is formed at the top of the semiconductor substrate of the channel region.
3. The method of claim 2, wherein the ion implantation process has an implantation angle of 30 ° -60 °.
4. The method of claim 1, wherein the performing an ion implantation process to form a stress layer on top of the semiconductor substrate in the channel region comprises:
forming a protective layer, wherein the protective layer covers the source drain region, and the upper surface of the protective layer is flush with the upper surface of the dummy grid;
removing the dummy gate to expose the gate insulating layer;
and performing an ion implantation process, and implanting a dopant into the top of the semiconductor substrate of the channel region to form the stress layer on the top of the semiconductor substrate of the channel region.
5. The method of claim 4, wherein the dopant is implanted vertically into the channel region.
6. The method of claim 2 or 4, wherein the dopant comprises at least one of carbon, germanium, and tin.
7. The method of fabricating the MOS transistor according to claim 1, wherein after forming the stress layer, the method of fabricating the MOS transistor further comprises:
forming a protective layer, wherein the protective layer covers the source drain region, and the upper surface of the protective layer is flush with the upper surface of the dummy grid;
removing the dummy gate and the gate insulating layer to expose the surface of the semiconductor substrate in the channel region;
forming a high dielectric constant material layer on the channel region;
forming a work function material layer on the high dielectric constant material layer; and
a metal gate is formed on the work function material layer.
8. The method of claim 7, wherein the material of the work function material layer comprises at least one of titanium nitride, tantalum nitride, and titanium aluminum based alloy.
9. The method of fabricating a MOS transistor according to claim 1, wherein the method of providing the semiconductor substrate comprises:
forming a gate insulating layer and a dummy gate which are stacked from bottom to top on the semiconductor substrate, wherein the gate insulating layer and the dummy gate cover a channel region of the semiconductor substrate and expose a source-drain forming region of the semiconductor substrate;
etching the semiconductor substrate of the source-drain forming region to form a groove by taking the dummy gate as a mask;
and forming an epitaxial material layer in the groove, and carrying out doping treatment on the epitaxial material layer to form the source and drain regions, wherein the source and drain regions apply stress to the channel region.
10. The method of claim 1, wherein the MOS transistor is P-type.
CN202210279755.4A 2022-03-22 2022-03-22 Manufacturing method of MOS transistor Pending CN114373681A (en)

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CN104681436A (en) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 Forming method of PMOS (P-channel metal oxide semiconductor) transistor
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CN104934324A (en) * 2014-03-18 2015-09-23 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591803A (en) * 2003-08-28 2005-03-09 国际商业机器公司 Strained silicon-channel MOSFET using a damascene gate process
CN103426737A (en) * 2012-05-14 2013-12-04 中芯国际集成电路制造(上海)有限公司 Method for manufacturing Damascus metal grid
CN103915387A (en) * 2013-01-08 2014-07-09 中芯国际集成电路制造(上海)有限公司 CMOS transistor forming method
US20150093871A1 (en) * 2013-09-27 2015-04-02 Semiconductor Manufacturing International (Shanghai) Corporation Enhanced stress memorization technique for metal gate transistors
CN104681436A (en) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 Forming method of PMOS (P-channel metal oxide semiconductor) transistor
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CN104701234A (en) * 2015-03-16 2015-06-10 上海华力微电子有限公司 Manufacturing method of semiconductor device

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