CN105023953A - Vertical field effect diode and manufacture method thereof - Google Patents
Vertical field effect diode and manufacture method thereof Download PDFInfo
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- CN105023953A CN105023953A CN201510402695.0A CN201510402695A CN105023953A CN 105023953 A CN105023953 A CN 105023953A CN 201510402695 A CN201510402695 A CN 201510402695A CN 105023953 A CN105023953 A CN 105023953A
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- 230000005669 field effect Effects 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 11
- 238000000407 epitaxy Methods 0.000 description 18
- 238000005468 ion implantation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007634 remodeling Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a vertical field effect diode and a manufacture method thereof and belongs to the field of semiconductor device manufacture. The vertical field effect diode is characterized in that the vertical field effect diode comprises a substrate; an epitaxial layer, which is of the same type with the substrate, is arranged on the substrate; the upper end surface of the epitaxial layer is downwardly provided with a plurality of grooves (9) in a separated manner; the grooves (9) are filled with filling mediums which form P-N junctions with the juncture surfaces of the epitaxial layer; the lower portion of the substrate and the upper portion of the grooves (9) are provided with a bottom metal layer (5) serving as a negative electrode and a top metal layer (1) serving as a positive electrode respectively; and a heavy doping-type region is arranged between the two adjacent grooves (9) as well as the outer sides of the grooves (9) at the two ends respectively, wherein the heavy doping-type regions are of the same type with the epitaxial layer, are arranged on the upper end of the epitaxial layer and are flush with the upper ends of the grooves (9). The vertical field effect diode adopts a structure of a field-effect transistor, so that, compared with a conventional semiconductor diode, the vertical field effect diode has the advantages of extremely-low dead zone voltage, quick conduction speed and high switching frequency.
Description
Technical field
A kind of vertical field-effect diode and manufacture method, belong to field of manufacturing semiconductor devices.
Background technology
Diode is one of the most common components and parts of semiconductor applications, has extensive use in electron trade and industry.In the prior art, mainly have following two kinds of diodes: with silicon, germanium for etc. the semiconductor diode made of semiconductor material, and take Schottky diode as the metal-semiconductor diode of representative.Semiconductor diode, when forward conduction, has higher dead zone voltage, is approximately 0.5V ~ 0.8V, and when forward voltage exceedes dead zone voltage, diode just meeting conducting, therefore switch efficiency is lower, and it is high to consume energy.Schottky diode has lower dead zone voltage, is approximately 0.2V, and conducting speed, but Schottky diode cannot be high pressure resistant, is not suitable for being applied in high pressure occasion.
Summary of the invention
The technical problem to be solved in the present invention is: overcome the deficiencies in the prior art, provides a kind of and has extremely low conducting voltage, and conducting speed is fast, simultaneously can high voltage bearing vertical field-effect diode and manufacture method.
The technical solution adopted for the present invention to solve the technical problems is: this vertical field-effect diode, it is characterized in that: comprise substrate, types of flexure is the epitaxial loayer identical with substrate type, the downward interval, upper surface of epitaxial loayer has multiple groove, be filled with the filled media forming P-N junction with the interface of epitaxial loayer in groove, be respectively arranged with the bottom metal layer as negative electrode and the top layer metallic layer as anode in the bottom of substrate and the top of groove; Between two adjacent described grooves and the outside of the groove being positioned at two ends be also provided with heavy doping type district, heavy doping type district is identical with epitaxial loayer type, is positioned at the upper end of epitaxial loayer and concordant with groove upper end.
Preferably, described filled media comprises the polysilicon be filled in groove and the monocrystalline silicon layer be arranged between polysilicon and groove inside edge.
Preferably, described filled media is the monocrystalline silicon be filled in groove.
A manufacture method for vertical field-effect diode, is characterized in that: comprise the steps:
Step 1, first forms epitaxial loayer on substrate top, then on epitaxial loayer, forms heavily doped region and oxide layer successively;
Step 2, carries out equally spaced etching to heavily doped region and oxide layer;
Step 3, using the oxide layer do not etched as hard mask, above epitaxial loayer, interval etches multiple groove;
Step 4, fills the filled media forming P-N junction with the interface of epitaxial loayer in groove by fill process;
Step 5, removes the unnecessary filled media in top and oxide layer;
Step 6, makes top layer metallic layer and bottom metal layer respectively at chip upper/lower terminal.
Preferably, the fill process described in step 4, comprises the steps:
Step 4-1, generates monocrystalline silicon layer at grooved inner surface;
Step 4-2, fills polysilicon in groove.
Preferably, the fill process described in step 4, comprises the steps:
Step 4-1, fills monocrystalline silicon in groove.
Compared with prior art, the beneficial effect that the present invention has is:
1, this vertical field-effect diode, owing to adopting the structure of field effect transistor, to compare traditional semiconductor diode, there is not the dead zone voltage that conventional P-N junction diode is existing when conducting, after being loaded with forward voltage, the conducting immediately of this vertical field-effect pipe, therefore has the advantage improving forward conduction efficiency.
2, this vertical field-effect diode, the injection not having the many sons opened and turn off of common P-N junction diode and few son and the process taken away, so switching speed significantly improves, switching frequency can significantly promote, and switching loss also can reduce.
3, above epitaxial loayer, carry out heavy doping, form heavily doped region, and between metal level, achieve good ohmic contact.
4, the thickness of epitaxial loayer can voltage withstand class according to actual needs regulate, and Schottky diode of therefore comparing can be applicable to the higher occasion of voltage.
5, to when filling in groove, preferably first form monocrystalline silicon layer by the form of ion implantation, then fill polysilicon, with the means of ion implantation, compare and directly fill the means of monocrystalline silicon, the reliability that monocrystalline silicon layer is formed is higher, lower to technological requirement.
Accompanying drawing explanation
Fig. 1 is vertical field-effect diode embodiment 1 structural representation.
Fig. 2 ~ Fig. 9 is vertical field-effect diode embodiment 1 manufacture method schematic flow sheet.
Figure 10 is vertical field-effect diode embodiment 2 structural representation.
Figure 11 ~ Figure 12 is vertical field-effect diode embodiment 2 manufacture method schematic flow sheet.
Figure 13 is vertical field-effect diode embodiment 3 structural representation.
Figure 14 is vertical field-effect diode embodiment 4 structural representation.
Wherein: 1, top layer metallic layer 2, N+ type layer 3, P type polysilicon 4, p type single crystal silicon layer 5, bottom metal layer 6, N-type substrate 7, N-type epitaxy layer 8, oxide layer 9, groove 10, p type single crystal silicon 11, N-type polycrystalline silicon 12, n type single crystal silicon layer 13, P type epitaxial loayer 14, P type substrate 15, P+ type layer 16, n type single crystal silicon.
Embodiment
Fig. 1 ~ 9 are most preferred embodiments of the present invention, and below in conjunction with accompanying drawing 1 ~ 14, the present invention will be further described.
Embodiment 1:
As shown in Figure 1, a kind of vertical field-effect diode, comprise N-type substrate 6, it is N-type epitaxy layer 7 above N-type substrate 6, multiple groove 9 is arranged at intervals with downwards from the upper end of N-type epitaxy layer 7, groove 9 is provided with p type single crystal silicon layer 4 with the interface of N-type epitaxy layer 7, is filled with P type polysilicon 3 in groove 9.Between adjacent two grooves 9 and the outside of groove 9 being positioned at two ends be also provided with heavily doped N+ type layer 2, N+ type layer 2 and be positioned at the upper end of N-type epitaxy layer 7 and concordant with groove 9 upper end, good ohmic contact can be realized by heavily doped N+ type layer 2.Bottom metal layer 5 and top layer metallic layer 1 is respectively arranged with on the top of the bottom of N-type substrate 6 and groove 9 and N+ type layer 2, P type polysilicon 3 in groove 9 and N+ type layer 2 connect by top layer metallic layer 1 simultaneously, when reality uses, top layer metallic layer 1 is as the anode of this vertical field-effect pipe, and bottom metal layer 5 is as the negative electrode of this vertical field-effect pipe.
As shown in Fig. 2 ~ 9, the manufacturing process of this vertical field-effect pipe, comprises the steps:
Step a, forms N-type epitaxy layer 7 and N+ type layer 2.
First form N-type epitaxy layer 7 on the top of N-type substrate 6, make N+ type layer 2 at the top layer of N-type epitaxy layer 7, as shown in Figure 2.
N-type epitaxy layer 7 is monocrystalline silicon layer, and its thickness regulates according to the voltage withstand class of this vertical field-effect pipe, and traditional Schottky diode of therefore comparing, has good high pressure resistant property, can be applicable to high pressure occasion.Be positioned at N-type epitaxy layer 7 top side N+ type layer 2 to generate by the mode of ion implantation.
Step b, forms oxide layer 8 at N+ type layer 2 disposed thereon, as shown in Figure 3.
Step c, carries out equally spaced etching by modes such as photoetching to oxide layer 8, as shown in Figure 4.
Steps d, forms groove 9 on N-type epitaxy layer 7 top.
Using the oxide layer 8 do not etched as hard mask, above N-type epitaxy layer 7, interval etches multiple vertical trench 9, as shown in Figure 5.
Step e, generates p type single crystal silicon layer 4 in groove 9.
Utilize P-type dopant in all grooves 9, to generate p type single crystal silicon layer 4 with the form of ion implantation, form P-N junction structure, as shown in Fig. 6 ~ 7.
Step f, fills polysilicon;
P type polysilicon 3 is filled, as shown in Figure 8 in the groove 9 defining p type single crystal silicon layer 4.
In step e ~ f, preferably first form p type single crystal silicon layer 4 by the form of ion implantation, then fill P type polysilicon 3, compare and directly fill the means of monocrystalline silicon, the reliability that p type single crystal silicon layer 4 is formed is higher, lower to technological requirement.
Step g, removes the unnecessary P type polysilicon 3 in top and oxide layer 8.
The mode of chemical corrosion or physics polishing is utilized the oxide layer 8 not carrying out etching in P type polysilicon 3 unnecessary for top and step c to be removed, chip top is made to expose N+ type layer 2 and the p type single crystal silicon layer 4 concordant with N+ type layer 2 and P type polysilicon 3, as shown in Figure 9.
Step h, makes top layer metallic layer 1 and bottom metal layer 5 respectively at chip upper/lower terminal, completes vertical field-effect diode as described in Figure 1.
The course of work and the operation principle of this vertical field-effect pipe are as follows:
When the applying forward voltage to this vertical field-effect pipe, (namely positive pole connects top layer metallic layer 1, negative pole connects bottom metal layer 5) time, because N+ type layer 2, N-type epitaxy layer 7 and N-type substrate 6 are conductor, therefore electric current is passed down through by top layer metallic layer 1 current channel that N+ type layer 2, N-type epitaxy layer 7 and N-type substrate 6 form successively and flow to bottom metal layer 5, now, this vertical field-effect diode forward conducting.
When the applying reverse voltage to this vertical field-effect pipe, (namely positive pole connects bottom metal layer 5, negative pole connects top layer metallic layer 1) time, due to electric voltage reverse-connection, start to occur exhaustion region between p type single crystal silicon layer 4 in adjacent two grooves 9, along with the increase gradually of voltage, when magnitude of voltage rises to cut-ff voltage, exhaustion region now between adjacent two grooves 9 is connected, the passage of electric current is blocked, now electric current circulates and is restricted between negative electrode (bottom metal layer 5) and anode (top layer metallic layer 1), i.e. this vertical field-effect diode reverse cut-off.
Due to this vertical field-effect diode due to during forward conduction because jointed anode (top layer metallic layer 1) and negative electrode (bottom metal layer 5) are semi-conducting material, its resistance can raise and conducting with voltage, so there is not conventional diode (as silicon diode, germanium diode, the Schottky diode) dead zone voltage existing when conducting, after being loaded with forward voltage, the conducting immediately of this vertical field-effect pipe, therefore has the advantage improving forward conduction efficiency.
Because between anode and negative electrode be the resistance of semi-conducting material, so there is no the many sons opened and turn off of common P-N junction diode and the injection lacking son and the process taken away, so switching speed significantly improves, switching frequency can significantly promote, and switching loss also can reduce.
Embodiment 2:
As shown in Figure 10, in the present embodiment, vertical field-effect pipe, comprising N-type substrate 6, is N-type epitaxy layer 7 above N-type substrate 6, is arranged at intervals with multiple groove 9 downwards from the upper end of N-type epitaxy layer 7, p type single crystal silicon 10 is filled with in groove 9, between adjacent two grooves 9 and the outside of groove 9 being positioned at two ends be also provided with heavily doped N+ type layer 2, N+ type layer 2 and be positioned at the upper end of N-type epitaxy layer 7 and concordant with groove 9 upper end, good ohmic contact can be realized by heavily doped N+ type layer 2.Be respectively arranged with bottom metal layer 5 and top layer metallic layer 1 on the top of the bottom of N-type substrate 6 and groove 9 and N+ type layer 2, the p type single crystal silicon layer 4 in groove 9 and N+ type layer 2 connect by top layer metallic layer 1 simultaneously.Identical with embodiment 1, top layer metallic layer 1 is as the anode of this vertical field-effect pipe, and bottom metal layer 5 is as the negative electrode of this vertical field-effect pipe.
In the present embodiment, the manufacturing process of vertical field-effect pipe, comprises the steps:
Wherein step a ~ steps d is identical with embodiment 1, respectively as shown in Fig. 2 ~ 5, does not repeat them here;
Step e, fills p type single crystal silicon 10 in groove 9, makes in groove 9 and form P-N junction structure between the N-type epitaxy layer 7 of groove 9 outside, as shown in figure 11.
Step f, removes the unnecessary p type single crystal silicon 10 in top and oxide layer 8.
Utilize the mode of chemical corrosion or physics polishing the oxide layer 8 not carrying out etching in p type single crystal silicon 10 unnecessary for top and step c to be removed, make chip top expose N+ type layer 2 and the p type single crystal silicon 10 concordant with N+ type layer 2, as shown in figure 12.
Step g, makes top layer metallic layer 1 and bottom metal layer 5 respectively at chip upper/lower terminal respectively, completes vertical field-effect diode as described in Figure 10.
Embodiment 3:
Embodiment 3 is with the difference of embodiment 1: in embodiment 3, N-type material and P section bar matter are exchanged, as shown in figure 13, vertical field-effect diode, comprise P type substrate 14, be P type epitaxial loayer 13 above P type substrate 14, be arranged at intervals with multiple groove 9 downwards from the upper end of P type epitaxial loayer 13, groove 9 is provided with n type single crystal silicon layer 12 with the interface of P type epitaxial loayer 7, is filled with N-type polycrystalline silicon 11 in groove 9.Between adjacent two grooves 9 and the outside of groove 9 being positioned at two ends be also provided with heavily doped P+ type layer 15, P+ type layer 15 and be positioned at the upper end of P type epitaxial loayer 13 and concordant with groove 9 upper end, good ohmic contact can be realized by heavily doped P+ type layer 15.Be respectively arranged with bottom metal layer 5 and top layer metallic layer 1 on the top of the bottom of P type substrate 14 and groove 9 and P+ type layer 15, the N-type polycrystalline silicon 11 in groove 9 and P+ type layer 15 connect by top layer metallic layer 1 simultaneously.Identical with embodiment 1, top layer metallic layer 1 is as the anode of this vertical field-effect pipe, and bottom metal layer 5 is as the negative electrode of this vertical field-effect pipe.
The manufacturing process of embodiment 3 is identical with embodiment 1, just N-type material and P section bar matter is exchanged during fabrication, does not repeat them here.
Embodiment 4:
Embodiment 4 is with the difference of embodiment 2: N-type material and P section bar matter are exchanged, as shown in figure 14, vertical field-effect pipe, comprise P type substrate 14, it is P type epitaxial loayer 13 above P type substrate 14, multiple groove 9 is arranged at intervals with downwards from the upper end of P type epitaxial loayer 13, n type single crystal silicon 16 is filled with in groove 9, between groove 9, the outside of the groove 9 at two ends is also provided with heavily doped P+ type district 15, P+ type district 15 is positioned at the upper end of P type epitaxial loayer 13 and concordant with groove 9 upper end, can realize good ohmic contact by heavily doped P+ type district 15.Be respectively arranged with bottom metal layer 5 and top layer metallic layer 1 on the top of the bottom of P type substrate 14 and groove 9 and P+ type layer 15, the n type single crystal silicon 16 in groove 9 and P+ type layer 15 connect by top layer metallic layer 1 simultaneously.Identical with embodiment 1, top layer metallic layer 1 is as the anode of this vertical field-effect pipe, and bottom metal layer 5 is as the negative electrode of this vertical field-effect pipe.
The manufacturing process of embodiment 4 is identical with embodiment 2, just N-type material and P section bar matter is exchanged during fabrication, does not repeat them here.
The above is only preferred embodiment of the present invention, and be not restriction the present invention being made to other form, any those skilled in the art may utilize the technology contents of above-mentioned announcement to be changed or be modified as the Equivalent embodiments of equivalent variations.But everyly do not depart from technical solution of the present invention content, any simple modification, equivalent variations and the remodeling done above embodiment according to technical spirit of the present invention, still belong to the protection range of technical solution of the present invention.
Claims (6)
1. a vertical field-effect diode, it is characterized in that: comprise substrate, types of flexure is the epitaxial loayer identical with substrate type, the downward interval, upper surface of epitaxial loayer has multiple groove (9), be filled with the filled media forming P-N junction with the interface of epitaxial loayer in groove (9), be respectively arranged with the bottom metal layer (5) as negative electrode and the top layer metallic layer (1) as anode on the top of the bottom of substrate and groove (9); Between two adjacent described grooves (9) and the outside of the groove (9) being positioned at two ends be also provided with heavy doping type district, heavy doping type district is identical with epitaxial loayer type, is positioned at the upper end of epitaxial loayer and concordant with groove (9) upper end.
2. vertical field-effect diode according to claim 1, is characterized in that: described filled media comprises the polysilicon be filled in groove (9) and the monocrystalline silicon layer be arranged between polysilicon and groove (9) inside edge.
3. vertical field-effect diode according to claim 1, is characterized in that: described filled media is for being filled in the monocrystalline silicon in groove (9).
4., for the manufacture of the manufacture method of the vertical field-effect diode according to any one of claim 1 ~ 4, it is characterized in that: comprise the steps:
Step 1, first forms epitaxial loayer on substrate top, on epitaxial loayer, then form heavily doped region and oxide layer (8) successively;
Step 2, carries out equally spaced etching to heavily doped region and oxide layer (8);
Step 3, using the oxide layer do not etched (8) as hard mask, above epitaxial loayer, interval etches multiple groove (9);
Step 4, fills the filled media forming P-N junction with the interface of epitaxial loayer in groove (9) by fill process;
Step 5, removes the unnecessary filled media in top and oxide layer (8);
Step 6, makes top layer metallic layer (1) and bottom metal layer (5) respectively at chip upper/lower terminal.
5. the manufacture method of vertical field-effect diode according to claim 4, is characterized in that: the fill process described in step 4, comprises the steps:
Step 4-1, generates monocrystalline silicon layer at groove (9) inner surface;
Step 4-2, fills polysilicon in groove (9).
6. the manufacture method of vertical field-effect diode according to claim 4, is characterized in that: the fill process described in step 4, comprises the steps:
Step 4-1, fills monocrystalline silicon in groove (9).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107046065A (en) * | 2017-04-06 | 2017-08-15 | 淄博汉林半导体有限公司 | The vertical field-effect diode and manufacture method of a kind of built-in schottky interface |
| CN107393970A (en) * | 2017-08-28 | 2017-11-24 | 西安理工大学 | A kind of carborundum junction barrier diode |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6404032B1 (en) * | 2000-03-31 | 2002-06-11 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device |
| EP1453094A1 (en) * | 2001-11-07 | 2004-09-01 | Shindengen Electric Manufacturing Company, Limited | Surge protection semiconductor device |
| CN101707214A (en) * | 2009-11-30 | 2010-05-12 | 浙江大学 | Semiconductor device |
| CN101740641A (en) * | 2009-12-24 | 2010-06-16 | 杭州立昂电子有限公司 | Semiconductor device |
| CN101834208A (en) * | 2010-04-30 | 2010-09-15 | 苏州硅能半导体科技股份有限公司 | Power MOS (Metal Oxide Semiconductor) field effect tube with low conduction resistance and manufacturing method |
| CN101901807A (en) * | 2010-06-23 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | Channel schottky barrier diode rectifying device and manufacturing method |
| CN102376777A (en) * | 2010-08-24 | 2012-03-14 | 上海芯石微电子有限公司 | Junction barrier schottky having low forward voltage drop |
| CN204792803U (en) * | 2015-07-10 | 2015-11-18 | 淄博汉林半导体有限公司 | Perpendicular field effect diode |
-
2015
- 2015-07-10 CN CN201510402695.0A patent/CN105023953A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6404032B1 (en) * | 2000-03-31 | 2002-06-11 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device |
| EP1453094A1 (en) * | 2001-11-07 | 2004-09-01 | Shindengen Electric Manufacturing Company, Limited | Surge protection semiconductor device |
| CN101707214A (en) * | 2009-11-30 | 2010-05-12 | 浙江大学 | Semiconductor device |
| CN101740641A (en) * | 2009-12-24 | 2010-06-16 | 杭州立昂电子有限公司 | Semiconductor device |
| CN101834208A (en) * | 2010-04-30 | 2010-09-15 | 苏州硅能半导体科技股份有限公司 | Power MOS (Metal Oxide Semiconductor) field effect tube with low conduction resistance and manufacturing method |
| CN101901807A (en) * | 2010-06-23 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | Channel schottky barrier diode rectifying device and manufacturing method |
| CN102376777A (en) * | 2010-08-24 | 2012-03-14 | 上海芯石微电子有限公司 | Junction barrier schottky having low forward voltage drop |
| CN204792803U (en) * | 2015-07-10 | 2015-11-18 | 淄博汉林半导体有限公司 | Perpendicular field effect diode |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107046065A (en) * | 2017-04-06 | 2017-08-15 | 淄博汉林半导体有限公司 | The vertical field-effect diode and manufacture method of a kind of built-in schottky interface |
| CN107046065B (en) * | 2017-04-06 | 2023-12-01 | 淄博汉林半导体有限公司 | Manufacturing method of vertical field effect diode with built-in Schottky interface |
| CN107393970A (en) * | 2017-08-28 | 2017-11-24 | 西安理工大学 | A kind of carborundum junction barrier diode |
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Application publication date: 20151104 |