US7709864B2 - High-efficiency Schottky rectifier and method of manufacturing same - Google Patents
High-efficiency Schottky rectifier and method of manufacturing same Download PDFInfo
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- US7709864B2 US7709864B2 US11/400,621 US40062106A US7709864B2 US 7709864 B2 US7709864 B2 US 7709864B2 US 40062106 A US40062106 A US 40062106A US 7709864 B2 US7709864 B2 US 7709864B2
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- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 239000002019 doping agent Substances 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 230000005684 electric field Effects 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 20
- 230000007704 transition Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Definitions
- the present invention relates broadly to semiconductor rectifier devices, especially Schottky rectifiers, and methods of manufacturing the same. More specifically, the present invention concerns a two-terminal semiconductor rectifier device comprising an integrated Schottky barrier rectifier and vertically-oriented junction field effect transistor (JFET) separated by a transition zone of inverted bias resulting from a three-layer epitaxial film, and a method of manufacturing the same.
- JFET junction field effect transistor
- Modern power circuits require power rectifiers with improved power switching performance. For some applications, p+/n rectifiers with high switching speeds are used. High switching speeds are necessary to minimize reverse current flow during recovery.
- Majority carrier devices such as Schottky barrier rectifiers, are often used because they offer both improved switching speed and lower forward voltage drop. Unfortunately, Schottky barrier rectifiers suffer from undesirably high reverse leakage current when operating at elevated temperatures.
- JBS junction barrier Schottky
- trench Schottky Another improvement is trench Schottky, which is useful for higher voltage applications in which the forward voltage drop exceeds 0.7 volts and the JBS rectifier ceases to operate as a majority carrier device.
- the trench MOS barrier-controlled Schottky (MBS) rectifier has a lower forward voltage drop than the p-i-n rectifier for breakdown voltages up to 250V, and still operates as a majority carrier device.
- Trench Schottky requires that, in the blocking state, the inner trenches are sufficiently closely spaced and the adjacent areas of the body portion are sufficiently lowly doped that the depletion layer formed in the body portion depletes the intermediate areas of the body portion between the trenches at a smaller voltage than the breakdown voltage. In that way, the reverse voltage blocking characteristic is improved. Unfortunately, it also results in a significant reduction of the area available for the Schottky barrier because the trench may consume as much as 50% of the available area on a chip.
- the present invention provides a high-efficiency two-terminal semiconductor device comprising a Schottky barrier rectifier and a vertically-oriented JFET separated by a transition zone of inverted bias resulting from a three-layer epitaxial film, and a method of manufacturing the same.
- the device has use, for example, in high frequency, low-loss power circuit applications in which high switching speed and low forward voltage drop are desirable.
- the device broadly comprises a multi-layer epitaxial film, a first structure manufactured in the multi-layer epitaxial film, and a second structure manufactured in the multi-layer epitaxial film and oriented vertically relative to the first structure.
- the first structure and the second structure are separated by a transition zone of inverted bias resulting from the multi-layer epitaxial film.
- the first structure is a Schottky barrier rectifier
- the second structure is a JFET.
- the semiconductor device comprises a substrate, with the multi-layer epitaxial film overlaying a top surface of the substrate, a trench manufactured in the multi-layer epitaxial film, a first region associated with an upper portion of the trench, and a second region associated with a lower portion of the trench.
- the substrate includes n-type silicon
- the multi-layer epitaxial film includes n-type material which is doped with phosphorus.
- the multi-layer epitaxial film includes three layers.
- the trench is approximately between 4 micrometers and 5 micrometers deep and approximately 1 micrometer wide, and is substantially filled with conductive polysilicon which is doped with a p-type dopant, such as boron.
- the first trench region is insulated with a dielectric layer from the uppermost (third) layer of the epitaxial film.
- boron-doped polysilicon is in direct contact with the first and second layers of the epitaxial film, forming a p+/n junction.
- the method of making the semiconductor device proceeds broadly as follows. Initially, the layers of the multi-layer epitaxial film are deposited in a single deposition process. During this process, the resistivity of one or more of the layers is established by introducing controlled amounts of n-type dopants in order to achieve desirable electrical characteristics for the layers. Alternatively, the desired resistivity profile can be established using subsequent diffusion processes.
- the first layer is modified with an n-type dopant to provide a particular breakdown voltage
- the second layer is modified with an n-type dopant to provide an area of reverse-direction electric field when the device is reverse-biased
- the third layer is modified with an n-type dopant to support and separate a first space charge region associated with an upper portion of the device and a second space charge region associated with the lower portion of the trench.
- the upper portion of the trench is etched into the multi-layer epitaxial film, and the first trench region is formed by associating an oxide with a surface of the upper portion of the trench.
- the lower portion of the trench is then etched, and the trench is substantially filled with the polysilicon doped with boron.
- the second trench region is formed by diffusing the boron into a surface of the lower portion of the trench.
- the device provides such desirable electrical characteristics as low forward voltage drop, low reverse current leakage, and very fast switching speed matching that of Schottky rectifiers and JFETs, while remaining a majority carrier device.
- the device much like a JBS rectifier, eliminates the Schottky barrier lowering which occurs in standard Schottky rectifiers, but also reverses the direction of the electric field for the portion of the drift region of the diode under current blocking bias, which reduces the reverse leakage current more effectively than the JBS rectifier. Additionally, the device better utilizes chip surface area than MBS when designed for low voltage, low VF application.
- FIG. 1 is a cross-sectional elevation view of an embodiment of the device of the present invention
- FIG. 2 is a cross-sectional elevation view of the device following an initial in a method of making the device of FIG. 1 , showing a multi-layer epitaxial film having been deposited on a substrate;
- FIG. 3 is a cross-sectional elevation view following a fourth step in the method, showing a deposit of nitride
- FIG. 4 is a cross-sectional elevation view following a fifth step in the method, showing a layer of oxide
- FIG. 5 is a cross-sectional elevation view following a sixth step in the method, showing the nitride of FIG. 3 removed;
- FIG. 6 is a cross-sectional elevation view following a seventh step in the method, showing an implantation of boron
- FIG. 7 is a cross-sectional elevation view following an eighth step in the method, showing an upper portion of a trench
- FIG. 8 is a cross-sectional elevation view following a ninth step in the method, showing a layer of oxide
- FIG. 9 is a cross-sectional elevation view following an eleventh step in the method, showing a lower portion of the trench;
- FIG. 10 is a cross-sectional elevation view following a twelfth step in the method, showing a deposit of polysilicon
- FIG. 11 is a cross-sectional elevation view following a thirteenth step in the method, showing an activation/diffusion of boron;
- FIG. 12 is a cross-sectional elevation view following a fourteenth step in the method, showing the device having been planarized;
- FIG. 13 is a cross-sectional elevation view following a sixteenth step in the method, showing the results of an etching process
- FIG. 14 is a cross-sectional elevation view following an eighteenth step in the method, showing a formation of silicide
- FIG. 15 is a cross-sectional elevation view following a nineteenth step in the method, showing a deposit of top metal
- FIG. 16 is a cross-sectional elevation view following a twenty-first step in the method, showing the results of an etching process
- FIG. 17 is a fragmentary plan view showing a first shape and spacing relation of the trenches
- FIG. 18 is a fragmentary plan view showing a second shape and spacing relation of the trenches
- FIG. 19 is a fragmentary plan view showing a third shape and spacing relation of the trenches.
- FIG. 20 is a first graph showing a potential profile of the device
- FIG. 21 is a second graph showing in greater detail area A of the first graph of FIG. 20 ;
- FIG. 22 is a third graph showing an electric field profile of the device along line AA of FIG. 15 ;
- FIG. 23 is a fourth graph showing in greater detail area B of the third graph of FIG. 22 .
- the device broadly comprises a high-efficiency two-terminal rectifier comprising a multi-layer epitaxial film, a first structure manufactured in the multi-layer epitaxial film, and a second structure manufactured in the multi-layer epitaxial film and oriented vertically relative to the first transistor.
- the first structure and the second structure are separated by a transition zone of inverted bias resulting from the multi-layer epitaxial film.
- the first structure is a Schottky barrier rectifier
- the second structure is a JFET.
- the device 10 has use, for example, in high frequency, low-loss power circuit applications in which high switching speed and low forward voltage drop are desirable.
- the device 10 more specifically comprises the multi-layer epitaxial film 12 , a substrate 14 , a trench 16 , a first region 18 associated with an upper portion of the trench 16 , a second region 20 associated with a lower portion of the trench 16 , and an anode 22 .
- the interface between the p+ doped second trench region 20 and the n material of the multi-layer epitaxial film creates a p+/n junction.
- the multi-layer epitaxial film 12 substantially overlays a top surface of the substrate 14 .
- the multi-layer epitaxial film 12 includes a first layer 26 having a thickness of approximately 2 micrometers and a resistivity of approximately 0.35 Ohm-cm; a second layer 28 having a thickness of approximately 3 micrometers and a resistivity of approximately 0.5 Ohm-cm; and a third layer 30 having a thickness of approximately 2.5 micrometers and a resistivity of 0.08 Ohm-cm.
- the resistivity of the third layer 30 is as low as the targeted minimum breakdown voltage allows in order to minimize a series resistance of the p+/n junction diode.
- the thickness and operating characteristics, such as resistivity, of some or all of the layers 26 , 28 , 30 results from dopants added during the epitaxial deposition process.
- the layers are modified by doping during one or more diffusion processes following the initial epitaxial deposition process.
- the n-type dopant may be phosphorous, and a different n-type dopant quantity may be used for each layer.
- the first layer 26 is doped to provide a breakdown voltage of 30 volts or higher; the second layer 28 is doped to provide an area of reverse-direction electric field when the device 10 is reverse-biased; and the third layer, which has the lowest resistivity, is doped to support and separate a space charge region of the reverse-biased Schottky contact and a space charge region of the p+/n junction at the lower portion of the trench 16 .
- the substrate 14 is an n-type silicon substrate having a wafer resistivity of approximately between 0.002 Ohm-cm and 0.005 Ohm-cm.
- the substrate 14 is doped with arsenic; in another embodiment, the substrate 14 is doped with antimony; in another embodiment the substrate is doped with phosphorous.
- the trench 16 is approximately between 4 micrometer and 5 micrometers deep, and approximately 1 micrometer wide. In another embodiment, the trench is approximately 4.5 micrometers deep, and approximately 1 micrometer wide.
- the trench is substantially filled with polysilicon. In one embodiment, the polysilicon is doped with boron. A plurality of such trenches 16 are etched into the substrate 16 .
- FIGS. 17 , 18 , 19 show a variety of different shapes and spacing relations for the trenches 16 a , 16 b , 16 c.
- the first trench region 18 is insulated with a dielectric layer from the uppermost (third) layer 30 of the epitaxial film 12 .
- the first trench region in combination with the third epitaxial layer 30 , operates to separate the space charge region of the reverse-biased Schottky barrier contact and the space charge region of the p+/n junction created at the lower portion of the trench 16 .
- the first insulating region 18 includes CVD oxide or, alternatively, thermal oxide (SiO 2 ).
- boron-doped polysilicon is in direct contact with the first and second layers of the epitaxial film, forming a p+/n junction.
- the second trench region 20 includes boron-doped silicon.
- the anode 22 is a Schottky barrier contact providing one terminal of the two-terminal device.
- a layer of silicide 36 is interposed between the anode 22 and the upper surface of the third layer 30 of the epitaxial film 12 .
- a cathode (not shown) is an Ohmic contact to the n+ substrate 14 providing the other terminal of the two-terminal device.
- a guard ring 38 absorbs forward current surge during operation of the device 10 , and is formed substantially similar to and substantially simultaneous with the trench 16 described above.
- the guard ring 38 is substantially conventional in all other respects.
- the device 10 provides the transition zone of inverted bias between the upper Schottky barrier contact, i.e., anode 22 , and the lower portion 20 of the trench 16 and the adjacent third epitaxial layer 26 , which together support a reverse voltage of 30 volts or higher (see FIGS. 20 and 21 showing a potential profile, and FIGS. 22 and 23 showing an electric field profile on line AA of FIG. 15 ).
- a forward bias mode i.e., the anode 22 being positive and the cathode being negative
- the direction of the electric field across the entire vertical structure is consistent with the external bias, so the forward voltage drop is as low as in conventional Schottky.
- the transition zone with a reversed electric field results from the multi-layer epitaxial film 12 , the oxide (SiO 2 ) spacer provided at the upper portion 18 of the trench 16 , and the p+ spacer provided at the lower portion 20 of the trench 16 working with the third epitaxial layer 26 .
- the third layer 30 of the epitaxial film 12 is heavily doped so that the space charge regions of the reverse-biased Schottky diode and the space charge region of p+/n junction around the lower portion 20 of the trench 16 do not overlap. Without the spacer at the first trench region 18 and the thickness and very low resistivity of the third epitaxial layer 30 , the device 10 would function as a JBS rectifier. When the device 10 is forward-biased, the space charge region from the p-doped trench 16 does not interfere with the field pattern, resulting in low forward voltage drop.
- the device 10 is constructed substantially as follows. It should be understood and appreciated that any one or more of the following steps may be eliminated or substituted with an equivalent alternative step; furthermore, it should be understood and appreciated that the order of any one or more of the following steps may be changed.
- some or all of the layers of the multi-layer epitaxial film 12 are deposited on the substrate 14 in a single deposition cycle using a standard epitaxial deposition process which is controlled, at least with respect to temperature, time, and gas flow rates, including the n-dopant gas flow rate, by a microprocessor.
- a second step When doping is not performed during the initial epitaxial deposition process: in a second step, one or more of the layers 26 , 28 , 30 are modified by one or more diffusion processes which introduce dopants, such as phosphorous, which result in desirable thicknesses and operating characteristics, such as those discussed above.
- silicon nitride 40 is deposited on the upper surface of the third layer 30 of the epitaxial film 12 to a thickness of approximately 1500 Angstroms.
- a first photolithography process is performed to pattern-etch the silicon nitride 40 , leaving circles or stripes approximately 1.4 micrometers in diameter or width.
- thermal oxide (SiO 2 ) 42 is grown approximately 0.5 micrometers thick using a LOCOS (localized oxidation of silicon) process.
- the silicon nitride 40 is removed by etching without removing the oxide 42 .
- boron 44 is implanted at a dose of approximately 3E13 and an energy of approximately 30 keV.
- the upper portion of the trench 16 is etched in the epitaxial film 12 to a depth of approximately 2.5 micrometers.
- an oxide 46 is deposited in the upper portion of the trench 16 to a thickness of approximately 0.15 micrometers, thereby creating the upper insulating region 18 .
- the oxide is CVD (chemical vapor deposition) oxide; in an alternative embodiment, the oxide is thermal oxide.
- the oxide 46 is etched using ion milling to approximately 0.2 micrometers.
- the lower portion of the trench 16 is formed by etching to deepen the trench 16 an additional approximately 2.0 micrometers.
- boron-doped polysilicon 48 is deposited to a thickness of approximately 0.3 micrometers at approximately 600 degrees Celsius.
- the boron 50 within the polysilicon 48 is activated/diffused into the surface of the lower portion of the trench, 16 , thereby creating the lower pn junction region 20 .
- the wafer is planarized using the initial oxide (LOCOS) as an etch stop.
- LOC initial oxide
- a second photolithography process is performed to define the anode contact.
- the oxide 42 is wet etched, and the photoresist used in the previous step is removed.
- titanium is deposited for the silicide Schottky barrier 36 .
- the titanium silicide Schottky barrier 52 is formed, and the excess titanium is removed.
- other metals may be used to create the silicide Schottky barrier
- the anode (top metal) 22 is deposited.
- a third photolithography step is performed to define a metal pattern on the top (anode) side of the wafer.
- a twenty-first step shown in FIG. 16 , the metal is etched, and the photoresist used in the previous step is removed.
- the wafer is thinned.
- the cathode (back metal) is deposited.
- the present invention provides a semiconductor rectifier device having desirable electrical characteristics, including low forward voltage drop, low reverse current leakage, and very fast switching speed matching that of Schottky rectifiers and JFETs, while remaining a majority carrier device.
- the device much like a JBS rectifier, eliminates the Schottky barrier lowering which occurs in standard Schottky rectifiers, but also reverses the direction of the electric field for the portion of the drift region of the diode under current blocking bias, which reduces the reverse leakage current more effectively than the JBS rectifier. Additionally, the device better utilizes chip surface area than MBS when designed for low voltage, low VF application.
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US11/400,621 US7709864B2 (en) | 2006-04-07 | 2006-04-07 | High-efficiency Schottky rectifier and method of manufacturing same |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103367396A (en) * | 2012-04-01 | 2013-10-23 | 朱江 | Super junction Schottky semiconductor device and preparation method thereof |
CN103378178A (en) * | 2012-04-30 | 2013-10-30 | 朱江 | Schottky semiconductor device with groove structures and preparation method thereof |
US20140357059A1 (en) * | 2010-10-21 | 2014-12-04 | Vishay General Semiconductor Llc | Schottky rectifier |
TWI511305B (en) * | 2012-11-01 | 2015-12-01 | Chip Integration Tech Co Ltd | Method of forming schottky rectifier device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US8138033B2 (en) * | 2007-05-09 | 2012-03-20 | Semiconductor Components Industries, Llc | Semiconductor component and method of manufacture |
CN113299539B (en) * | 2021-05-24 | 2022-10-11 | 深圳市联冀电子有限公司 | SBD low forward saturation special material and preparation method thereof |
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US4568958A (en) * | 1984-01-03 | 1986-02-04 | General Electric Company | Inversion-mode insulated-gate gallium arsenide field-effect transistors |
US20060170036A1 (en) * | 2004-02-02 | 2006-08-03 | Hamza Yilmaz | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
-
2006
- 2006-04-07 US US11/400,621 patent/US7709864B2/en active Active
Patent Citations (2)
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US4568958A (en) * | 1984-01-03 | 1986-02-04 | General Electric Company | Inversion-mode insulated-gate gallium arsenide field-effect transistors |
US20060170036A1 (en) * | 2004-02-02 | 2006-08-03 | Hamza Yilmaz | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140357059A1 (en) * | 2010-10-21 | 2014-12-04 | Vishay General Semiconductor Llc | Schottky rectifier |
CN103367396A (en) * | 2012-04-01 | 2013-10-23 | 朱江 | Super junction Schottky semiconductor device and preparation method thereof |
CN103378178A (en) * | 2012-04-30 | 2013-10-30 | 朱江 | Schottky semiconductor device with groove structures and preparation method thereof |
CN103378178B (en) * | 2012-04-30 | 2017-04-26 | 朱江 | Schottky semiconductor device with groove structures and preparation method thereof |
TWI511305B (en) * | 2012-11-01 | 2015-12-01 | Chip Integration Tech Co Ltd | Method of forming schottky rectifier device |
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US20070235830A1 (en) | 2007-10-11 |
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