CN104752363B - The forming method of flash memory - Google Patents
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- CN104752363B CN104752363B CN201310754246.3A CN201310754246A CN104752363B CN 104752363 B CN104752363 B CN 104752363B CN 201310754246 A CN201310754246 A CN 201310754246A CN 104752363 B CN104752363 B CN 104752363B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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Abstract
A kind of forming method of flash memory, including：Substrate is provided；Stop-layer in first groove in substrate between the floating boom of formation core space, floating boom in substrate, the second groove between external zones grid, grid in substrate, and floating boom, grid, the hard mask layer on stop-layer；Form dielectric materials layer；Dielectric materials layer between cmp dielectric materials layer, hard mask layer, adjacent floating boom is that the dielectric materials layer between the first dielectric layer, neighboring gates is the second dielectric layer；Protective layer is formed on the second dielectric layer, afterwards using protective layer as mask, cleaning removes the hard mask layer part of external zones residual；Etching removes stop-layer, and removal protective layer is also etched in the process；Graphical first dielectric layer formation fleet plough groove isolation structure.The performance of flash memory is preferable, and product yield meets volume production requirement.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of flash memory.
Background technology
At present, flash memory（Flash Memory）Also known as flash memory, the main flow for having become non-volatility memorizer is deposited
Reservoir.Different according to structure, flash memory can be divided into or non-flash（NOR Flash）With with non-flash（NAND Flash）.Flash memory
It is mainly characterized by that the information of storage can be kept for a long time in the case of not powered；And with integrated level is high, access speed is fast, be easy to
The advantages of erasing and rewriting, thus be widely used in the multinomial field such as microcomputer, Automated condtrol.
Existing flash memory includes the core memory circuit being located in substrate（Cell Circuit）With positioned at core
Peripheral circuit around storage circuit（Peripheral Circuit）.The core memory circuit, which includes some, has smaller spy
The transistor of size is levied, and peripheral circuit mainly includes having some compared with the high pressure of large-feature-size and the routine of mesolow circuit
MOS transistor, if embedded, also has corresponding low voltage logic circuit.Wherein, adjacent two in core memory circuit are brilliant
The distance between the grid of body pipe is very small, and the distance between grid of two transistor in peripheral circuit is relatively large.
The forming method of existing flash memory includes：
Reference picture 1 is there is provided substrate 10, and 10 points of the substrate is core space I and external zones II, and core is formed with the substrate 10
Heart district I multiple floating booms spaced apart from each other（Floating Gate, FG）11 and external zones II multiple grids spaced apart from each other
12, and the stop-layer 13 on the floating boom 11, grid 12, the hard mask layer 14 on stop-layer 13, stop-layer 13
Material is silicon nitride, and the material of hard mask layer 14 is silica, and the width of floating boom 11 is less than the line width and adjacent two grid of grid 12
Spacing W between pole 122More than the spacing W between adjacent two floating boom 111, the spacing between the grid 12 of arbitrary neighborhood two is also not
Most identical.In addition, when etching forms hard mask layer 14, because floating boom line width is less than grid line width, core space I hard mask
The etching of 14 side of layer be can not ignore, and cause external zones II hard mask layer relatively thin, the hard mask layer than core space I is thin；
It is mask with hard mask layer 14, etches segment thickness substrate formation first groove between adjacent two floating boom 11（In figure
Non- label）, and etch segment thickness substrate formation second groove between adjacent two grid 12（Non- label in figure）, due to W2>W1,
The etch rate of substrate is more than the etch rate of substrate between adjacent two floating boom 11 between adjacent two grid 12 so that described second
The depth D of groove2More than the depth D of first groove1；
Reference picture 2, deposited oxide silicon material layer 15 on the substrate 10, silica material layer 15 covers hard mask layer 14, filled out
Full of first groove and second groove, the silica material layer in first groove, second groove, which has, is higher by hard mask layer 14
Part.
Reference picture 3, cmp silica material layer 15（Reference picture 2）, stop to the upper surface of stop-layer 13, grinding
During mill, core space I hard mask layer is milled away, but external zones II hard mask layer 14 has residual.Adjacent two floating boom
Remaining silica material layer is used as the first silicon oxide layer 16, the upper surface of the first silicon oxide layer 16 and the upper table of stop-layer 13 between 11
Face maintains an equal level；Remaining silica material layer is used as the second silicon oxide layer 17 between adjacent two grid 12.Additionally, due to W2>W1, correspondence
The grinding rate of the silica material layer segment of second groove position is more than the silica material layer segment of first groove position
The upper surface of the second silicon oxide layer 17 after grinding rate, therefore grinding is slightly below the upper surface of stop-layer 13, and recessed.In figure
In 3, dotted line frame represents the upper surface of the second silicon oxide layer 17 after grinding.
Reference picture 4, the hard mask layer 14 of cleaning external zones II residuals（Reference picture 3）To ensure stop-layer 13（Reference picture 3）
Upper no hard mask layer remains and causes follow-up stop-layer removal unclean.But, in cleaning process, the second silicon oxide layer 17
Also cleaned so that the height of the second silicon oxide layer 17 further reduces, with reference to reference picture 2 so that the second silicon oxide layer 17
Less than grid 12, and the upper surface of the second silicon oxide layer 17 is persistently recessed and forms the first groove 18；
Without using mask, etching removes stop-layer 13.
Reference picture 5, the first silicon oxide layer 16 of patterned part height（Reference picture 4）, remaining first silicon oxide layer part
Higher than the upper surface of substrate 10, fleet plough groove isolation structure is used as；
Formed on the upper surface of floating boom 11 and side wall, fleet plough groove isolation structure upper surface, grid 12 with the first groove surfaces
Insulating barrier 19；
Control gate material layer 20 is formed on insulating barrier 19；
Amorphous carbon layer 21, the silicon oxynitride layer 22 on amorphous carbon layer 21 are formed in control gate material layer 20,
Silicon oxynitride layer 22 is used as dielectric anti-reflective layer（Dielectric Anti-Reflection Coating, DARC）, without fixed
Shape carbon-coating 21 can improve subsequent etching quality and the fineness of figure；
Bottom anti-reflection layer is formed on silicon oxynitride layer 22（Bottom Anti-Reflection Coating, BARC）
23 and the patterned photoresist layer 24 in bottom anti-reflection layer 23, patterned photoresist layer 24 defines control gate position
Put.
Reference picture 6, using patterned photoresist layer as mask, etching bottom anti-reflecting layer 23, silicon oxynitride layer 22, nothing are fixed
Shape carbon-coating 21 and control gate material layer 20（Reference picture 5）, stop to insulating barrier 19, form control gate 25.Remove afterwards graphical
Photoresist layer and remaining bottom anti-reflection layer, silicon oxynitride layer, amorphous carbon layer.
But, the performance of the flash memory formed using prior art is not good.
The content of the invention
The problem of present invention is solved is that the performance of the flash memory formed using prior art is not good.
To solve the above problems, the present invention provides a kind of forming method of flash memory, the formation of the flash memory
Method includes：
The first groove between the multiple floating booms of core space, adjacent two floating boom in substrate is formed on the substrate, and it is described
Second groove between multiple grids of external zones, adjacent two grid in substrate, and on the floating boom, the stopping on grid
Layer, the hard mask layer on the stop-layer, the floating gate width is less than grid width and first groove width is less than second
Groove width；
Dielectric materials layer is formed, the dielectric materials layer covers the hard mask layer, the full first groove of filling and the second ditch
Dielectric materials layer in groove, the first groove, second groove has the part for being higher by hard mask layer；
Dielectric materials layer, hard mask layer described in cmp to the stop-layer stop, and are remained between adjacent two floating boom
Remaining dielectric material layer segment is as the first dielectric layer, and remaining dielectric material layer segment is used as second to be situated between adjacent two grid
Electric layer；
Protective layer is formed on second dielectric layer, afterwards using the protective layer as mask, cleaning removes the periphery
The hard mask layer part of area's residual；
Etching removes the stop-layer, in this process, and also etching removes the protective layer；
After etching removes stop-layer, the graphical first dielectric layer formation fleet plough groove isolation structure.
Alternatively, the dielectric material is silica, and the material of the hard mask layer is silica, the stopping layer material
For silicon nitride.
Alternatively, the protective layer material is silicon oxynitride.
Alternatively, Rapid Thermal Nitrided, the processing of decoupled plasma nitrogen or microwave nitrogen are carried out to the second dielectric layer upper surface
Corona treatment, silicon oxynitride is formed on second dielectric layer.
Alternatively, the gas that the Rapid Thermal Nitrided process is used is ammonia, and temperature range is 700 DEG C~1000 DEG C, is held
The continuous time is 30s~90s, and the range of flow of ammonia is 1000sccm~10000sccm.
Alternatively, decoupled plasma nitrogen processing is carried out in nitrogen environment.
Alternatively, the thickness range of the protective layer is。
Alternatively, the method that etching removes stop-layer is wet etching.
Alternatively, the etching agent that the wet etching is used is phosphoric acid solution.
Alternatively, using wet etching or dry etching, cleaning removes the hard mask layer part of the external zones residual.
Alternatively, the etching agent that the wet etching process is used is dilute hydrofluoric acid solution.
Alternatively, the fleet plough groove isolation structure is higher than upper surface of substrate.
Alternatively, the forming method bag of the floating boom, first groove, grid, second groove, hard mask layer and stop-layer
Include：
Gate material layer, the stopping material layer in gate material layer, the shape on the stop-layer are formed on the substrate
Into layer of hard mask material；
Patterned photoresist layer is formed in the layer of hard mask material, the patterned photoresist layer definition is floating
The position of grid, grid；
Using the patterned photoresist layer as mask, etch hard mask materials layer forms hard mask layer and etching stopping
The gate material layer of material layer formation stop-layer and the gate material layer formation floating boom and etching external zones that etch core space forms grid
Pole；
Remove patterned photoresist layer；
First groove, second groove are formed by mask etching segment thickness substrate of the hard mask layer.
Alternatively, the method for the dielectric layer of etched portions thickness first is dry etching, or wet etching, or first dry method are carved
Erosion, rear wet etching.
Alternatively, after the first dielectric layer of etched portions thickness, the 3rd groove is formed between adjacent two floating boom；
The forming method of the flash memory also includes：Form insulating barrier and positioned at many of the core space laid out in parallel
Individual control gate, the insulating barrier covers the 3rd trenched side-wall and bottom, the second dielectric layer and grid, each control gate filling
Insulation layer segment on full multiple 3rd grooves, the covering floating boom.
Alternatively, the method for control gate is formed on the insulating barrier to be included：
Chemical vapor deposition insulating barrier, the control gate material layer on insulating barrier；
The control gate material layer is patterned to form control gate.
Alternatively, it is self-alignment duplex pattern method to the method for controlling gate material layer to be patterned.
Alternatively, the self-alignment duplex pattern method includes：
Hard mask layer is formed in the control gate material layer；
The first amorphous carbon layer, the first electricity on first amorphous carbon layer is formed on the hard mask layer to be situated between
Matter anti-reflecting layer；
The second amorphous carbon layer is formed on first dielectric anti-reflective layer, on second amorphous carbon layer
The second dielectric anti-reflective layer；
Bottom anti-reflection layer, the photoresist in bottom anti-reflection layer are formed on second dielectric anti-reflective layer
Layer；
The photoresist layer is patterned, and using the photoresist layer after graphical as mask etching bottom anti-reflective
Layer, the second dielectric anti-reflective layer and the second amorphous carbon layer form multiple first strip pieces；
Side wall, the position of the side wall correspondence control gate are formed in the first strip piece two side；
By the strip piece of mask etching first of the side wall, it is the first dielectric anti-reflective layer and the first amorphous carbon layer, hard
Mask layer, forms the second strip piece；
Remaining first dielectric anti-reflective layer, the first amorphous carbon layer are removed, afterwards, is carved by mask of remaining hard mask layer
Erosion control gate material layer formation control gate.
Compared with prior art, technical scheme has advantages below：
After chemical mechanical polishing, external zones remains hard mask layer part.Protective layer is formed on the second dielectric layer,
When cleaning removes the hard mask layer part of external zones residual, protective layer protects the second dielectric layer to exempt from cleaning loss.So, with showing
There is technology to compare, the difference in height between the second dielectric layer upper surface and gate upper surface is smaller, and the second dielectric layer upper surface will not
Deeper groove is formed, also influence would not be produced on being subsequently formed control gate process.So, in the second dielectric layer of external zones
On will not produce pseudo- control gate defect, the signal transmission between external zones each transistor can be stablized, lifting flash memory
Read/write speed and read/write quality, the performance of flash memory are preferable.Moreover, external zones would not be done without pseudo- control gate defect
Parameter measure on line is disturbed, final products yield meets volume production requirement.
Brief description of the drawings
Fig. 1~Fig. 6 is cross-sectional view of the flash memory of prior art in forming process；
Fig. 7~Figure 16 is cross-sectional view of the flash memory of the specific embodiment of the invention in forming process.
Embodiment
Analyzed, found for prior art：Reference picture 4, the upper surface of the second silicon oxide layer 17 is less than the upper table of grid 12
Difference in height between face, and the second larger silicon oxide layer 17 of width and grid 12 is bigger, is more than, in the second silica
17 upper surface of layer are in deeper for the first deeper groove 18.
Control gate layer material sections upper surface and grid on reference picture 4, Fig. 5, the first groove 18 with smaller width
Control gate layer material sections on 12 remain basically stable, and the control gate layer material sections on the first groove 18 with larger width
The second groove is formed less than the control gate layer material sections of surrounding, that is, in control gate material layer 20（Non- label in figure）.
Second groove pattern passes to amorphous carbon layer 21, silicon oxynitride layer 22 successively, and the 3rd groove is formed in amorphous carbon layer 21
With the 4th groove of formation in silicon oxynitride layer 22（Non- label in figure）, but from the first groove, the second groove, the 3rd groove to
Four grooves, width is gradually reduced.The upper surface of bottom anti-reflection layer 23 is flat, but the bottom anti-reflective of the 4th groove location of correspondence
Penetrate the thickness H of layer segment2It is greater than the thickness H1 of the bottom anti-reflective layer segment of surrounding, because the 4th groove is compared to flat
Face can assemble more bottom anti-reflective materials.
So, reference picture 5, Fig. 6, with patterned photoresist layer 24 be mask etching bottom anti-reflection layer 23, to nitrogen
Silicon oxide layer 22 exposes, and the silicon oxynitride layer segment of the 4th bottom portion of groove is not removed also completely, with residual.Then, continue
Silicon oxynitride layer 22 is etched to amorphous carbon layer 21, in this process, the bottom anti-reflective layer segment of the 4th bottom portion of groove is gone
Remove, the silicon oxynitride layer segment under the 4th bottom portion of groove is not removed completely, with residual.And then etching amorphous carbon layer
21, under conditions of etching amorphous carbon layer 21, amorphous carbon has higher etching selection ratio compared to silicon oxynitride, and the 4th is recessed
Remaining silicon oxynitride layer part is not etched substantially under trench bottom, and the amorphous carbon layer segment under the 4th bottom portion of groove does not have
Etched.Afterwards, the control gate material layer under the etching control process of gate material layer 20, the 4th bottom portion of groove is not carved
Erosion.After patterned photoresist layer and remaining bottom anti-reflection layer, silicon oxynitride layer, amorphous carbon layer is removed, in correspondence the
Four bottom portion of groove positions form pseudo- control gate 26.Pseudo- control gate 26 is likely to result in the train of signal between each transistor of external zones
Disturb, cause flash memory read/write speed, or even cause read/write errors, cause flash memory performance not good.Moreover, online
In upper defective workmanship detection, pseudo- control gate is considered as the source of defect, and pseudo- control gate causes to do to defective workmanship detection process
Disturb, cause to be difficult that even can not detect other defect, cause product yield to decline.
To solve the problem of prior art is present, technical solution of the present invention proposes a kind of formation of new flash memory
Method.Using the forming method of the flash memory, in cmp dielectric materials layer formation the first dielectric layer and second
After dielectric layer, protective layer is formed on the second dielectric layer.So, the hard mask layer partial routine remained on stop-layer is cleaned
In, protective layer protects the second dielectric layer to exempt from cleaning loss.Protective layer prevents the second dielectric layer surface by more losses, it is ensured that
Second dielectric layer is by less etching.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Reference picture 7 includes core space I and external zones II there is provided substrate 100, substrate 100.In the present embodiment, in core
Area I will form the piled grids formula transistor of core memory circuit, and the MOS transistor of peripheral circuit will be formed in external zones II.
In a particular embodiment, substrate 100 is silicon base, germanium substrate or silicon-on-insulator substrate etc.；Or substrate 100
Material can also include other materials, the III-V such as GaAs.Those skilled in the art can basis
The transistor types formed in substrate 100 select substrate, therefore the type of substrate should not be limited the scope of the invention.
Reference picture 8, formation core space I multiple floating booms 101 and external zones II spaced apart from each other is multiple in substrate 100
Grid 102 spaced apart from each other, the width of floating boom 101 is less than the width of grid 102, the spacing W between adjacent two floating boom 1011It is small
Spacing W between adjacent two grid 1022So that the distribution density of floating boom 101 is more than the distribution density of grid 102.In floating boom
101st, stop-layer 105, the hard mask layer 115 on stop-layer 105 are formed with grid 102.Wherein, in floating boom 101 and base
Gate dielectric layer 106 is formed between bottom, between grid 102 and substrate.
It should be noted that the spacing between external zones II each grid line width, adjacent two grid is also to be not quite similar
's.
In a particular embodiment, the shape of gate dielectric layer 106, floating boom 101, grid 102, hard mask layer 115 and stop-layer 105
Include into method：
Gate dielectric material layer is formed in substrate 100, the material of gate dielectric material layer is silica, specific usableization
Learn vapour deposition or thermal oxide growth technique；
Gate material layer, the stopping material layer in gate material layer are formed on gate dielectric material layer, positioned at stopping material
Layer of hard mask material on layer, grid material is polysilicon, and hard mask material is silica, and stopping layer material is silicon nitride, specifically
Chemical vapor deposition method can be used；
Patterned photoresist layer is formed in the layer of hard mask material, patterned photoresist layer defines floating boom, grid
The position of pole；
Using the patterned photoresist layer as mask, etch hard mask materials layer forms hard mask layer 115 and etch-stop
Only material layer formation stop-layer 105 and etching core space I gate material layer form floating boom 101 and etching external zones II grid material
Bed of material formation grid 102 and etching gate dielectric material layer form gate dielectric layer 106；
Remove patterned photoresist layer.In etch hard mask materials layer, the hard mask under patterned photoresist layer
Layer side can also be etched.Because the width of floating boom 101 is less than the width of grid 102, in external zones II, patterned photoetching
The etch amount of hard mask layer side under glue-line is insignificant, the thickness of external zones II hard mask layer 115 compared with its width
Degree and the thickness of layer of hard mask material are of substantially equal.And the quarter of the hard mask layer side under core space I, patterned photoresist layer
Erosion amount can not be ignored compared with its width, cause the thickness of final core space I hard mask layer 115 to be less than hard mask material
The thickness of the bed of material.So, the thickness of external zones II hard mask layer 115 is more than the thickness of core space I hard mask layer 115.
Reference picture 9, is mask with hard mask layer 115, and etching substrate 100 is formed between adjacent two floating boom 101 in substrate
Second groove 104 between first groove 103 and adjacent two grid 102 in substrate.The depth D of second groove 1042More than
The depth D of one groove 1031。
Reference picture 10, forms dielectric materials layer 107, the covering of dielectric materials layer 107 hard mask layer 115, full first ditch of filling
Groove 103 and second groove 104（Reference picture 9）, and dielectric materials layer in first groove, second groove has and is higher by hard mask layer
115 part.
In a particular embodiment, the material of dielectric materials layer 107 is silica, and usable chemical vapor deposition is formed.
Reference picture 11, cmp dielectric materials layer 107, hard mask layer 115（Reference picture 9）, stop to stop-layer 105
Only.Wherein, core space I hard mask layer 115 is relatively thin and be milled away, and external zones II hard mask layer 115 is thicker and has
Residual.After grinding, remaining dielectric material layer segment is used as the first dielectric layer 108, adjacent two grid between adjacent two floating boom 101
Remaining dielectric material layer segment is used as the second dielectric layer 109 between 102.
Due to W2>W1, the upper surface area of the second dielectric layer 109 is more than the upper surface area of the first dielectric layer 108, therefore, in change
Learn in mechanical grinding process, the grinding rate of the dielectric material layer segment of correspondence second groove position is more than first groove position
The grinding rate of dielectric material layer segment, makes to indicate slightly below stop-layer 105 on the second dielectric layer 109, and the second dielectric layer 109
Upper surface is in groove-like.
Reference picture 12, forms protective layer 110 on the second dielectric layer 109.
In a particular embodiment, the material of protective layer 110 is silicon oxynitride.Specifically, to the upper surface of the second dielectric layer 109
Carry out Rapid Thermal Nitrided（Rapid Thermal Nitridation, RTN）, decoupled plasma nitrogen processing（Decoupled
Plasma Nitridation, DPN）Or microwave nitrogen plasma（Microwave Generated Nitrogen Plasma）
Processing, forms silicon oxynitride, the silicon oxynitride is used as protective layer 110 on the second dielectric layer 109.Wherein, in nitrogen environment
Carry out decoupled plasma nitrogen processing.
In the present embodiment, it is situated between first in core space I formation photoresist layers, the first of photoresist layer covering core space I
Electric layer 108, stop-layer 105；Afterwards, using rapid thermal nitridation process, protective layer 110 is formed on the second dielectric layer 110.It is described
Rapid Thermal Nitrided refers to carrying out quick thermal annealing process, and is passed through ammonia simultaneously, and in Rapid Thermal Nitrided process, nitrogen and second is situated between
The oxidation pasc reaction generation silicon oxynitride on the surface of electric layer 110.In Rapid Thermal Nitrided process, keeping temperature is 700 DEG C~1000 DEG C,
Duration is 30s~90s, and the range of flow of ammonia is 1000sccm~10000sccm.If the duration is less than 30s,
The protective layer of minimum predetermined thickness can not be formed；If the duration is more than 90s, the protective layer formed is blocked up, in follow-up work
It is unfavorable for removing in skill.
In the present embodiment, the thickness range of protective layer 110 is.If the thickness of protective layer 110 is less than, during follow-up cleaning removes residual hard mask layer part, protective layer may comparatively fast be washed and can not risen
To the effect of the second dielectric layer 109 of protection, and further produce the problem of prior art is present.If the thickness of protective layer 110
It is more than, protective layer 110 is difficult to be removed during etching removes stop-layer.
Reference picture 13, is mask with protective layer 110, and cleaning removes the hard mask layer 115 of external zones II residuals（Reference picture
12）Part, in cleaning process, protective layer 110 protects the second dielectric layer 109 to exempt from cleaning loss.
In a particular embodiment, using dry etching or wet etching, cleaning removes the hard mask layer of external zones II residuals
Part.In the present embodiment, using wet etching, the etching agent used in wet etching process is dilute hydrofluoric acid solution.
Compared to prior art, the second dielectric layer 109 will not be lost by cleaning, and the thickness of the second dielectric layer 109 will not
Become lower so that the difference in height between the second dielectric layer upper surface and gate upper surface is less than, and prior art is clear
The difference in height washed between the second dielectric layer upper surface behind residual hard mask layer part and gate upper surface is more than.So,
The groove of second dielectric layer upper surface is shallower, will not produce influence to being subsequently formed control gate process, on the second dielectric layer not
Pseudo- control gate defect can be produced.
Reference picture 14, etching removes stop-layer 105（Reference picture 13）.During etching stop layer 105, do not formed and covered
Film layer, stop-layer 105, the dielectric layer 108 of protective layer 107 and first are directly contacted with etching atmosphere.Due in etching stop layer
Under the conditions of 105, protective layer and etching stop layer have close etching selection ratio, therefore, in etching stop layer, protective layer
Be etched removal.
In a particular embodiment, the method that etching removes stop-layer is wet etching.Used during wet etching
Etching agent is phosphoric acid solution, this technique being well known to those skilled in the art, and be will not be described in detail herein.
Reference picture 15, after etching removes stop-layer, graphical first dielectric layer 108（Reference picture 14）Formed shallow trench every
From structure 111, and the 3rd groove 112 of formation between adjacent two floating boom 101.In the present embodiment, fleet plough groove isolation structure 111
With the part for being higher by upper surface of substrate, this can increase the distance between control gate and active area, realize control gate to floating boom more
Effectively control.
In a particular embodiment, the method for graphical first dielectric layer includes：It is initially formed patterned photoresist layer, institute
State the position that patterned photoresist layer defines core space I；Using patterned photoresist layer as mask, the of etched portions thickness
One dielectric layer formation fleet plough groove isolation structure；Afterwards, patterned photoresist layer is removed.
In a particular embodiment, the method for the first dielectric layer of etched portions thickness is dry etching or wet etching.
In the present embodiment, first dry etching, rear wet-etching technology are used.Dry etching has preferable anisotropic etching, and wet
Method etch it is smaller to the etch rates of the first dielectric layer portions of the side wall of floating boom 101, make the upper surface of fleet plough groove isolation structure 111 with
Angle between 3rd groove 112 becomes round and smooth, and which further increases the distance between control gate and active area.
Reference picture 16, formed fleet plough groove isolation structure 111 after, formed insulating barrier 113 and positioned at core space I it is multiple simultaneously
The control gate 114 of row, insulate 113 layers of the 3rd groove 112 of covering（Reference picture 15）Side wall and bottom, the second dielectric layer 109 and grid
Insulating barrier portion on pole 102, each full multiple the 3rd grooves being located along the same line of the filling of control gate 114, covering floating boom 101
Point.
In a particular embodiment, forming the method for control gate on the insulating layer includes：
Chemical vapor deposition insulating barrier, the control gate material layer on insulating barrier, insulating barrier are silica, positioned at oxidation
The laminated construction of silicon nitride on silicon and the silica on silicon nitride, it is polysilicon to control grid material, in depositional control grid
During material layer, because the groove of the second dielectric layer upper surface is shallower, the control gate layer material sections of the second dielectric layer position of correspondence
Upper surface and the upper surface of control gate layer material sections of surrounding remain basically stable；
Control gate material layer is patterned to form control gate.
In the present embodiment, to controlling the method that gate material layer is patterned to be self-alignment duplex pattern method.It is described
The graphical method of autoregistration includes：
Hard mask layer is formed in control gate material layer；
The first amorphous carbon layer, the first dielectric anti-reflective on the first amorphous carbon layer are formed on hard mask layer
Layer, the material of the first dielectric anti-reflective layer is SiON；
The second amorphous carbon layer, the second electricity on the second amorphous carbon layer are formed on the first dielectric anti-reflective layer
Dielectric anti reflective layer, the material of the second dielectric anti-reflective layer is SiON；
Bottom anti-reflection layer, the photoresist layer in bottom anti-reflection layer are formed on the second dielectric anti-reflective layer；
Photoresist layer is patterned, in patterned exposure process, bottom anti-reflection layer is used for reducing following each layer
Reflection to exposure light, it is anti-for mask etching bottom anti-reflection layer, the second dielectric using the photoresist layer after graphical afterwards
Reflecting layer, the second amorphous carbon layer form multiple first strip pieces.In this process, photoresist layer after graphical also can be by
Partly or entirely etch, if by partial etching, after the first strip piece is formed, removing remaining photoresist layer part.
Side wall, side wall correspondence control gate position are formed in the first strip piece two side；
By the strip piece of mask etching first of side wall, the first dielectric anti-reflective layer and the first amorphous carbon layer, hard mask
Layer, forms the second strip piece；
Remaining first dielectric anti-reflective layer, the first amorphous carbon layer are removed, afterwards, is carved by mask of remaining hard mask layer
Erosion control gate material layer formation control gate.Control gate figure using the formation of self-alignment duplex pattern method is finer, size symbol
Close and be expected.
So, floating boom 101, control gate 114 and control gate 114 and floating boom on floating boom 101 are included in core space I formation
The stack grid structure of insulating barrier between 101.Afterwards, in the both sides substrate of floating boom 101, the both sides substrate of grid 102 it is medium-sized
Source electrode, drain electrode（Not shown in figure）.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (18)
1. a kind of forming method of flash memory, it is characterised in that including：
Substrate is provided, the substrate includes core space and external zones；
The first groove between the multiple floating booms of core space, adjacent two floating boom in substrate, and the periphery are formed on the substrate
Second groove between multiple grids in area, adjacent two grid in substrate, and on the floating boom, the stop-layer on grid,
Hard mask layer on the stop-layer, the floating gate width is less than grid width and first groove width is less than second groove
Width；
Dielectric materials layer is formed, the dielectric materials layer covers the hard mask layer, the full first groove of filling and second groove, institute
Stating the dielectric materials layer in first groove, second groove has the part for being higher by hard mask layer；
Dielectric materials layer, hard mask layer described in cmp to the stop-layer stop, remaining between adjacent two floating boom
Dielectric material layer segment is as the first dielectric layer, and remaining dielectric material layer segment is used as the second dielectric between adjacent two grid
Layer；
Protective layer is formed on second dielectric layer, afterwards using the protective layer as mask, it is residual that cleaning removes the external zones
The hard mask layer part stayed；
Etching removes the stop-layer, in this process, and also etching removes the protective layer；
After etching removes stop-layer, the graphical first dielectric layer formation fleet plough groove isolation structure.
2. the forming method of flash memory as claimed in claim 1, it is characterised in that the dielectric material is silica,
The material of the hard mask layer is silica, and the stopping layer material is silicon nitride.
3. the forming method of flash memory as claimed in claim 2, it is characterised in that the protective layer material is nitrogen oxidation
Silicon.
4. the forming method of flash memory as claimed in claim 3, it is characterised in that to the second dielectric layer upper surface
Rapid Thermal Nitrided, the processing of decoupled plasma nitrogen or microwave nitrogen plasma treatment are carried out, nitrogen is formed on second dielectric layer
Silica.
5. the forming method of flash memory as claimed in claim 4, it is characterised in that the Rapid Thermal Nitrided process is used
Gas be ammonia, temperature range is 700 DEG C~1000 DEG C, and the duration is 30s~90s, and the range of flow of ammonia is
1000sccm~10000sccm.
6. the forming method of flash memory as claimed in claim 4, it is characterised in that decoupled etc. in nitrogen environment
The processing of gas ions nitrogen.
7. the forming method of flash memory as claimed in claim 1, it is characterised in that the thickness range of the protective layer is
8. the forming method of flash memory as claimed in claim 3, it is characterised in that the method that etching removes stop-layer is
Wet etching.
9. the forming method of flash memory as claimed in claim 8, it is characterised in that the etching that the wet etching is used
Agent is phosphoric acid solution.
10. the forming method of flash memory as claimed in claim 2, it is characterised in that carved using wet etching or dry method
Erosion, cleaning removes the hard mask layer part of the external zones residual.
11. the forming method of flash memory as claimed in claim 10, it is characterised in that the wet etching process is used
Etching agent be dilute hydrofluoric acid solution.
12. the forming method of flash memory as claimed in claim 1, it is characterised in that the fleet plough groove isolation structure is high
In upper surface of substrate.
13. the forming method of flash memory as claimed in claim 1, it is characterised in that the floating boom, first groove, grid
Pole, second groove, the forming method of hard mask layer and stop-layer include：
Gate material layer, the stopping material layer in gate material layer are formed on the substrate, the shape in the stopping material layer
Into layer of hard mask material；
Patterned photoresist layer is formed in the layer of hard mask material, the patterned photoresist layer defines floating boom, grid
The position of pole；
Using the patterned photoresist layer as mask, etch hard mask materials layer forms hard mask layer and etching stopping material
Layer forms stop-layer and the gate material layer formation floating boom for etching core space and etches the gate material layer formation grid of external zones；
Remove patterned photoresist layer；
First groove, second groove are formed by mask etching segment thickness substrate of the hard mask layer.
14. the forming method of flash memory as claimed in claim 1, it is characterised in that the dielectric of etched portions thickness first
The method of layer is dry etching, or wet etching, or first dry etching, rear wet etching.
15. the forming method of flash memory as claimed in claim 1, it is characterised in that the first of etched portions thickness
After dielectric layer, the 3rd groove is formed between adjacent two floating boom；
The forming method of the flash memory also includes：Form insulating barrier and multiple controls positioned at the core space laid out in parallel
Grid processed, the insulating barrier covers the 3rd trenched side-wall and bottom, the second dielectric layer and grid, and each control gate filling is full more
Insulation layer segment on individual 3rd groove, the covering floating boom.
16. the forming method of flash memory as claimed in claim 15, it is characterised in that control is formed on the insulating barrier
The method of grid processed includes：
Chemical vapor deposition insulating barrier, the control gate material layer on insulating barrier；
The control gate material layer is patterned to form control gate.
17. the forming method of flash memory as claimed in claim 16, it is characterised in that enter to the control gate material layer
The patterned method of row is self-alignment duplex pattern method.
18. the forming method of flash memory as claimed in claim 17, it is characterised in that the self-alignment duplex pattern
Method includes：
Hard mask layer is formed in the control gate material layer；
The first amorphous carbon layer, the first dielectric on first amorphous carbon layer is formed on the hard mask layer to resist
Reflecting layer；
The second amorphous carbon layer, the on second amorphous carbon layer are formed on first dielectric anti-reflective layer
Two dielectric anti-reflectives layer；
Bottom anti-reflection layer, the photoresist layer in bottom anti-reflection layer are formed on second dielectric anti-reflective layer；
The photoresist layer is patterned, and by mask etching bottom anti-reflection layer of the photoresist layer after graphical, the
Two dielectric anti-reflectives layer and the second amorphous carbon layer form multiple first strip pieces；
Side wall, the position of the side wall correspondence control gate are formed in the first strip piece two side；
By the strip piece of mask etching first of the side wall, the first dielectric anti-reflective layer and the first amorphous carbon layer, hard mask
Layer, forms the second strip piece；
Remaining first dielectric anti-reflective layer, the first amorphous carbon layer are removed, afterwards, using remaining hard mask layer as mask etching control
Gate material layer formation control gate processed.
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| CN106910707A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN106910706B (en) * | 2015-12-23 | 2020-01-03 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN105655297B (en) * | 2016-01-26 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor devices |
| CN107437547B (en) * | 2016-05-26 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN108682675A (en) * | 2017-03-31 | 2018-10-19 | 上海格易电子有限公司 | A kind of flash memory and its manufacturing method |
| CN108091562B (en) * | 2017-12-21 | 2020-06-16 | 上海华力微电子有限公司 | ONO etching method of SONOS memory |
| CN110223982B (en) * | 2018-03-01 | 2021-07-27 | 联华电子股份有限公司 | Dynamic random access memory and manufacturing method thereof |
| CN111354675B (en) * | 2018-12-21 | 2023-04-25 | 上海新微技术研发中心有限公司 | Shallow trench isolation structure and forming method thereof |
| CN111755449B (en) * | 2019-03-27 | 2023-08-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112466751B (en) * | 2019-09-06 | 2023-07-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| DE102020102842A1 (en) * | 2019-09-30 | 2021-04-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | SOURCE / DRAIN CONTACT WITH A PROJECTING SEGMENT |
| CN110854120A (en) * | 2019-11-27 | 2020-02-28 | 上海华力微电子有限公司 | Method for forming semiconductor |
| CN112951714A (en) * | 2019-12-10 | 2021-06-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111146082B (en) * | 2019-12-30 | 2023-04-14 | 上海集成电路研发中心有限公司 | Method for preparing head-to-head graph |
| CN114068687A (en) * | 2021-11-26 | 2022-02-18 | 上海华虹宏力半导体制造有限公司 | Method for forming inter-gate oxide layer and method for forming shielded gate trench type device |
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