CN115295570B - Method for manufacturing CMOS image sensor - Google Patents
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- CN115295570B CN115295570B CN202211170495.3A CN202211170495A CN115295570B CN 115295570 B CN115295570 B CN 115295570B CN 202211170495 A CN202211170495 A CN 202211170495A CN 115295570 B CN115295570 B CN 115295570B
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L27/144—Devices controlled by radiation
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- H01L27/1463—Pixel isolation structures
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14643—Photodiode arrays; MOS imagers
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Abstract
The invention provides a manufacturing method of a CMOS image sensor. The manufacturing method comprises the following steps: providing a substrate comprising a first area and a second area, wherein a hard mask layer is formed on the upper surface of the substrate; forming a core mold structure on the hard mask layer; forming side walls on the side walls of the core mold structure, removing the core mold structure, wherein a first interval is formed between adjacent side walls on the first area, and a second interval is formed between adjacent side walls on the second area; taking the first area and/or the second area as a trimming area, and trimming the outline of the side wall on the trimming area through an etching process; and etching the hard mask layer and the substrate by taking the side wall as a mask, and respectively forming a first groove and a second groove with different depths in the substrates of the first area and the second area, wherein the groove with the set section shape is formed by trimming the outline of the side wall on the trimming area. Therefore, the grooves with small size and different depths can be formed simultaneously, and the cross section shapes of the grooves are controllable.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a CMOS image sensor.
Background
CMOS Image Sensors (CIS) are used in applications including digital cameras. In semiconductor technology, CIS is used to sense light incident on a semiconductor substrate. Generally, these devices utilize an array of pixels (pixels) containing photodiodes and other transistors to convert an image into digital data or electronic signals.
CIS products typically include a pixel region and a logic region. Shallow Trench Isolation (STI) is a feature of an integrated circuit to prevent leakage current (leakage current) between adjacent semiconductor components. However, as the pixel size of the CIS is smaller, shallow trench isolation used in the pixel region needs to be made shallower compared to the logic region in order to increase the photosensitive area of the pixel region and reduce the dark current of the pixel.
Fig. 1 to 4 are schematic views of a step structure of a method for fabricating a CMOS image sensor. The manufacturing method of the CMOS image sensor comprises the following steps: as shown in fig. 1, a substrate 10 includes a pixel region 10a and a logic region 10b, and a hard mask layer 11 and a patterned first photoresist layer 12 are sequentially formed on the substrate 10; as shown in fig. 2, the patterned first photoresist layer 12 is used as a mask, the hard mask layer 11 and the substrate 10 are etched to form first shallow trenches 13 in the substrate of the pixel region 10a and the substrate of the logic region 10b, and then the patterned first photoresist layer 12 is removed; as shown in fig. 3, a patterned second photoresist layer 14 is formed on the substrate 10, and the patterned second photoresist layer 14 exposes the logic region 10b; as shown in fig. 4, using the patterned second photoresist layer 14 and the hard mask layer 11 as a mask, a second shallow trench 15 is etched down at the position of the first shallow trench 13 in the logic region 10 b.
In the process of forming the trenches with different depths in the substrate of the pixel area and the logic area of the CMOS image sensor, two masks are required to be used and two etching processes are performed, and the size of the trench is smaller with the reduction of the size of the CIS. Therefore, how to form trenches with smaller size and different depths at the same time is worth studying.
Disclosure of Invention
The invention aims to provide a manufacturing method of a CMOS image sensor, which can simultaneously form grooves with smaller size and different depths, and is beneficial to reducing the size of the CMOS image sensor and reducing the number of used masks.
In order to achieve the above object, the present invention provides a method for manufacturing a CMOS image sensor, comprising: providing a substrate, wherein the substrate comprises a first area and a second area, and a hard mask layer is formed on the upper surface of the substrate; forming a core mold structure on the hard mask layer; forming side walls on the side walls of the core mold structure, removing the core mold structure, wherein a first interval is formed between adjacent side walls on the first area, and a second interval is formed between adjacent side walls on the second area; taking the first area and/or the second area as a trimming area, and trimming the outline of the side wall on the trimming area through an etching process; etching the hard mask layer and the substrate by taking the side wall as a mask, stopping in the substrate, forming a first groove in the substrate of the first area and forming a second groove in the substrate of the second area; wherein the first trench and the second trench having different depths are formed by setting the first pitch and the second pitch to be different; and forming a groove with a set section shape in the substrate of the trimming area by trimming the profile of the side wall on the trimming area.
Optionally, the first area is a pixel area, and the second area is a logic area; the depth of the first trench is less than the depth of the second trench.
Optionally, the method for forming a mandrel structure on the hard mask layer includes: forming a core mold material layer and a patterned first mask layer on the core mold material layer on the upper surface of the hard mask layer; with the patterned first mask layer as a mask, etching the core mold material layer downwards and stopping on the upper surface of the hard mask layer to form the core mold structure; and removing the patterned first mask layer.
Optionally, an amorphous carbon layer, a silicon oxycarbide layer, and a bottom anti-reflection layer stacked from bottom to top are disposed between the mandrel material layer and the patterned first mask layer.
Optionally, the method for forming the sidewall on the sidewall of the core mold structure includes: forming a side wall material layer, wherein the side wall material layer covers the side wall and the top surface of the core mold structure and covers the exposed upper surface of the hard mask layer; and etching to remove the side wall material layer on the top surface of the core mold structure and part of the side wall material layer on the upper surface of the hard mask layer, and reserving the side wall material layer on the side wall of the core mold structure as the side wall.
Optionally, the hard mask layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked from bottom to top on the upper surface of the substrate.
Optionally, the first distance is 45 nm to 55 nm, and the depth of the first groove is 150 nm to 250 nm; the second distance is 55-65 nanometers, and the depth of the second grooves is 270-330 nanometers.
Optionally, the method for trimming the profile of the sidewall on the trimming region by using an etching process includes: and etching the side walls of the side walls to enable the cross section of the opening between the adjacent side walls in the trimming area to be in a shape with a wide top and a narrow bottom, so that a groove with a cross section in a shape with a wide top and a narrow bottom is formed in the substrate of the trimming area in the subsequent step.
Optionally, the method for etching the hard mask layer and the substrate by using the side wall as a mask includes: and etching the substrate in at least two sub-steps, wherein the etching conditions of the at least two sub-steps are different, so that the side wall of the first groove and the side wall of the second groove have at least two gradients.
According to the manufacturing method of the CMOS image sensor, the core mold structure is formed on the hard mask layer of the substrate, the side wall of the core mold structure is formed, then the core mold structure is removed, the hard mask layer and the substrate are etched by taking the side wall as the mask, so that the first groove is formed in the substrate of the first area, the second groove is formed in the substrate of the second area, and therefore the first groove and the second groove which are small in size (namely critical size) can be formed at the same time, the size of the CMOS image sensor is reduced, and the integration level of a chip is improved. In addition, a first interval is formed between the adjacent side walls on the first area, a second interval is formed between the adjacent side walls on the second area, and through setting different first and second intervals, a first groove and a second groove with different depths can be formed in the first area and the second area at the same time, so that different isolation requirements of the first area and the second area are met at the same time, the performance of the CMOS image sensor is improved, and the number of used masks is reduced.
Further, after the mandrel structure is removed, before the hard mask layer and the substrate are etched by using the side wall as a mask, the first region and/or the second region is/are used as a trimming region, and the profile of the side wall on the trimming region is trimmed by an etching process to form a trench with a set cross-sectional shape in the substrate of the trimming region, so that an isolation structure with a set cross-sectional shape can be formed according to the actual needs of the CMOS image sensor, and the performance of the CMOS image sensor is improved.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a patterned first photoresist layer formed on a substrate in a method for fabricating a CMOS image sensor.
FIG. 2 is a cross-sectional view of a substrate with a first shallow trench formed therein during a method for fabricating a CMOS image sensor.
Fig. 3 is a schematic cross-sectional view illustrating a patterned second photoresist layer formed on a substrate in a method for fabricating a CMOS image sensor.
Fig. 4 is a schematic cross-sectional view illustrating a second shallow trench formed in a substrate in a method for fabricating a CMOS image sensor.
Fig. 5 is a flowchart illustrating a method for fabricating a CMOS image sensor according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view illustrating a hard mask layer, a mandrel material layer and a patterned first mask layer formed on a substrate in a method for fabricating a CMOS image sensor according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view illustrating a core mold structure formed on a substrate in a method for fabricating a CMOS image sensor according to an embodiment of the invention.
Fig. 8 is a schematic cross-sectional view illustrating a sidewall material layer formed on a substrate according to a method for fabricating a CMOS image sensor in an embodiment of the invention.
Fig. 9 is a schematic cross-sectional view illustrating a sidewall formed on a sidewall of a mandrel structure in a method for fabricating a CMOS image sensor according to an embodiment of the invention.
Fig. 10 is a schematic cross-sectional view illustrating a method for fabricating a CMOS image sensor according to an embodiment of the invention, after removing a mandrel structure.
Fig. 11 is a schematic cross-sectional view illustrating a first trench and a second trench formed in a substrate in a method for manufacturing a CMOS image sensor according to an embodiment of the invention.
Fig. 12 is a schematic cross-sectional view illustrating a trimmed sidewall in a method for fabricating a CMOS image sensor according to an embodiment of the invention.
Fig. 13 is a schematic cross-sectional view illustrating a first trench and a second trench formed in a substrate in a method for manufacturing a CMOS image sensor according to an embodiment of the invention.
FIG. 14 is a cross-sectional view of a second trench in an embodiment of the present invention.
Description of the reference numerals:
(fig. 1 to 4) 10-a substrate; 10 a-pixel region; 10 b-logical area; 11-a hard mask layer; 12-a patterned first photoresist layer; 13-a first shallow trench; 14-a patterned second photoresist layer; 15-a second shallow trench;
(fig. 6-14) 20-a substrate; 20 a-a first zone; 20 b-a second zone; 21-a hard mask layer; 211-a first silicon oxide layer; 212-a silicon nitride layer; 213-a second silicon dioxide layer; 22-a mandrel material layer; 22 a-core mold structure; 231-an amorphous carbon layer; a 232-silicon oxycarbide layer; 233-bottom antireflective layer; 24-a first mask layer; 25-side wall material layer; 25 a-side wall; 25 b-an opening; 26-a first trench; 27-second trenches.
Detailed Description
The following describes a method for fabricating a CMOS image sensor according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to simultaneously form trenches with smaller size and different depths so as to reduce the size of the CMOS image sensor and reduce the number of used masks, the application provides a manufacturing method of the CMOS image sensor. Fig. 5 is a flowchart illustrating a method for fabricating a CMOS image sensor according to an embodiment of the invention. As shown in fig. 5, the method for fabricating the CMOS image sensor includes:
s1, providing a substrate, wherein the substrate comprises a first area and a second area, and a hard mask layer is formed on the upper surface of the substrate;
s2, forming a core mold structure on the hard mask layer;
s3, forming a side wall on the side wall of the core mold structure, and removing the core mold structure; a first space is formed between the adjacent side walls on the first area, and a second space is formed between the adjacent side walls on the second area;
s4, taking the first area and/or the second area as a trimming area, and trimming the outline of the side wall on the trimming area through an etching process; and
s5, with the side walls as masks, etching the hard mask layer and the substrate and stopping in the substrate, forming a first groove in the substrate of the first area and forming a second groove in the substrate of the second area; wherein the first trench and the second trench having different depths are formed by setting the first pitch and the second pitch to be different; and forming a groove with a set cross-sectional shape in the substrate of the trimming area by trimming the profile of the side wall on the trimming area.
It should be understood that, although the steps in the flowchart of fig. 5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a part of the steps in fig. 5 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
Fig. 6 to 13 are schematic views of a sub-step structure of a method for manufacturing a CMOS image sensor according to an embodiment of the invention. A method for manufacturing a CMOS image sensor according to the present invention will be described below with reference to fig. 5 to 13.
As shown in fig. 6, a substrate 20 is provided to include a first region 20a and a second region 20b, and a hard mask layer 21 is formed on an upper surface of the substrate 20.
The substrate 20 may be made of silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like, or may be made of silicon on insulator or germanium on insulator; or may be other materials such as group III-V compounds such as gallium arsenide. In this embodiment, the first area 20a may be a pixel area, and the second area 20b may be a logic area, but is not limited thereto.
In the present application, by adjusting the thickness of the hard mask layer 21, the depth and profile of the first trench and the second trench to be formed later can be adjusted, and the profile of the trench may specifically include the cross-sectional shape of the trench. The "cross section of the trench" in this application refers to a cross section of the trench perpendicular to the upper surface of the substrate 20.
In this embodiment, the hard mask layer 21 may include, but is not limited to, a first silicon oxide layer 211, a silicon nitride layer 212, and a second silicon oxide layer 213 stacked from bottom to top on the upper surface of the substrate 20. In some embodiments, the hard mask layer 21 may also be a single-layer structure, and may further include only the first silicon oxide layer 211 and the silicon nitride layer 212.
The thickness of the first silicon oxide layer 211 may be 30 to 50 angstroms, for example, 40 angstroms, but is not limited thereto. The first silicon oxide layer 211 may be formed by a thermal oxidation process. The thickness of the silicon nitride layer 212 may be 150 to 250 angstroms, such as 200 angstroms, but is not limited thereto. The thickness of the second silicon oxide layer 213 may be 550 to 650 angstroms, such as 600 angstroms, but is not limited thereto. The silicon nitride layer 212 and the second silicon oxide layer 213 may be formed by a chemical vapor deposition process, but are not limited thereto. The thicknesses of the first silicon oxide layer 211, the silicon nitride layer 212, and the second silicon oxide layer 213 may also be adjusted according to the depth and the sectional shape of the first trench and the second trench to be formed later.
A method of forming a mandrel structure on the hard mask layer 21 may include: as shown in fig. 6, a core mold material layer 22 and a patterned first mask layer 24 on the core mold material layer 22 are formed on the upper surface of the hard mask layer 21; as shown in fig. 7, with the patterned first mask layer 24 as a mask, etching the mandrel material layer 22 downward and stopping on the upper surface of the hard mask layer 21 to form the mandrel structure 22a; the first masking layer 24 is removed.
The material of patterned first mask layer 24 may be a photoresist. The method of forming patterned first masking layer 24 may include: coating a photoresist on the substrate 20 to form a photoresist layer; the photoresist layer is exposed and developed to form a patterned first mask layer 24.
In order to improve the pattern accuracy of the patterned first mask layer 24 and improve the pattern transfer accuracy of the patterned first mask layer 24 into the mandrel material layer 22, as shown in fig. 6, an amorphous carbon layer 231, a silicon oxycarbide layer 232 (SiOC), and a bottom anti-reflection layer 233 (BARC) are disposed between the mandrel material layer 22 and the patterned first mask layer 24, which are stacked from bottom to top.
Specifically, amorphous carbon layer 231 is used to improve the accuracy with which the pattern of patterned first mask layer 24 is transferred into mandrel material layer 22. Amorphous carbon layer 231 may be formed by a chemical vapor deposition process.
The silicon oxycarbide layer 232 on the amorphous carbon layer 231 can be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), which can be used to absorb light irradiated thereon, which is advantageous for improving the pattern in the amorphous carbon layer 231 and the mandrel material layer 22. The better the light absorption effect of the silicon oxycarbide layer 232, the more accurate the pattern of the mandrel structure 22a formed by etching the mandrel material layer 22. In other embodiments, the silicon oxycarbide layer 232 may also be replaced by a carbon doped silicon oxide layer or a silicon nitride layer (SiN).
The bottom anti-reflection layer 233 formed on the silicon oxycarbide layer 232 is made of an organic material, is in a liquid state, and has good fluidity, so that the formed bottom anti-reflection layer 233 has a relatively uniform surface, and in the subsequent process of forming a photoresist layer and performing exposure, the bottom anti-reflection layer 233 plays a role in anti-reflection, and further ensures that the subsequently formed patterned first mask layer 24 has relatively high resolution. The method of forming the bottom anti-reflection layer 233 may be: an organic material layer is coated on the silicon oxycarbide layer 232 by spin coating or spray coating, and then the organic material layer is soft-baked to form the bottom anti-reflection layer 233.
Referring to fig. 6 and 7, after the mandrel structure 22a is formed, the patterned first mask layer 24, the bottom anti-reflection layer 233, the silicon oxycarbide layer 232, and the amorphous carbon layer 231 are sequentially removed. Next, as shown in fig. 9, a sidewall 25a is formed on the sidewall of the core mold structure 22a.
The method for forming the sidewall 25a on the sidewall of the core mold structure 22a may include: as shown in fig. 8, forming a sidewall material layer 25, where the sidewall material layer 25 covers the sidewalls and the top surface of the core mold structure 22a and covers the exposed upper surface of the hard mask layer 21; as shown in fig. 9, the sidewall material layer on the top surface of the core mold structure 22a and a part of the sidewall material layer on the upper surface of the hard mask layer 21 are removed by etching, and the sidewall material layer on the sidewall of the core mold structure 22a is reserved as the sidewall 25a.
The material of the sidewall material layer 25 may include, but is not limited to, silicon oxide. In order to improve the thickness uniformity and compactness of the side wall material layer 25, the side wall material layer 25 may be formed by using an Atomic Layer Deposition (ALD) process, but is not limited thereto. The sidewall material layer 25 may also be formed by other chemical vapor deposition processes known in the art. In the process of etching the sidewall material layer 25 to form the sidewall 25a, the etching is stopped on the surface of the hard mask layer 21. The thickness of the sidewall material layer 25 may be set according to actual requirements.
As shown in fig. 10, the core mold structure 22a is removed. The mandrel structure 22a may be etched away by, for example, a dry etching process.
In this application, as shown in fig. 10, a first distance d1 is provided between adjacent side walls 25a on the first region 20a, a second distance d2 is provided between adjacent side walls 25a on the second region 20b, and d1 is not equal to d2, so that a first trench and a second trench with different depths are formed in the first region 20a and the second region 20b in the following process.
As shown in fig. 11, using the sidewall 25a as a mask, etching the hard mask layer 21 and the substrate 20 and stopping in the substrate 20, forming a first trench 26 in the substrate of the first region 20a and forming a second trench 27 in the substrate of the second region 20 b. In the present application, the first trenches 26 and the second trenches 27 having different depths are formed by setting the first pitch d1 and the second pitch d2 to be different; that is, by adjusting the interval between the sidewalls in the first and second regions 20a and 20b, the first and second trenches 26 and 27 having different depths may be simultaneously formed in the same etching process.
In order to increase the photosensitive area of the pixel region and reduce the dark current of the pixel, the depth of the first trench 26 is smaller than the depth of the second trench 27, so that the first distance d1 needs to be smaller than the second distance d2.
When d1 and d2 are large, the difference in depth between the formation of the first trench 26 and the formation of the second trench 27 is small, and thus, in the present application, d1 and d2 are each less than 70 nm. Taking the first region 20a as a pixel region and the second region 20b as a logic region as an example, in order to form a shallow first trench 26 in the pixel region and a deep second trench 27 in the logic region, and to enable the depths of the first trench 26 and the second trench 27 to respectively satisfy the isolation requirements of the pixel region and the logic region, referring to fig. 10 and 11, the first distance d1 may be 5 nm to 55 nm, and the depth H1 of the first trench 26 may be 150 nm to 250 nm; the second distance d2 may be 55 nm to 65 nm, and the depth H2 of the second trench 27 may be 270 nm to 330 nm.
Referring to fig. 10 and 11, after removing the core mold structure 22a, two opposite sidewalls of the sidewall 25a are substantially vertical, and the cross-sectional shape of the trench (including the first trench 26 and the second trench 27) formed by etching the hard mask layer 21 and the substrate 20 using the sidewall 25a thus contoured as a mask is substantially rectangular.
In order to meet the requirement of the CMOS image sensor, in some embodiments, after the mandrel structure 22a is removed, before the sidewall 25a is used as a mask and the hard mask layer 21 and the substrate 20 are etched, the first region 20a and/or the second region 20b may be used as a trimming region, and the profile of the sidewall 25a on the trimming region is trimmed by an etching process, so as to form a trench with a set cross-sectional shape in the substrate of the trimming region. For example, the profile of the sidewall spacers 25a may be trimmed by a dry etching process.
As an example, as shown in fig. 12 and fig. 13, the first region 20a and the second region 20b are both trimming regions, and the side walls of the side walls 25a are etched, so that the cross section of the opening 25b between adjacent side walls 25a on the trimming regions is in a shape with a wide top and a narrow bottom (for example, an inverted trapezoid), so as to form the first trench 26 and the second trench 27 in the shape with a wide top and a narrow bottom (for example, an inverted trapezoid) in the base of the trimming regions, which is helpful for improving the isolation effect of each unit in the CMOS image sensor, but is not limited thereto. It is also possible to make the cross section of the opening 25b in a shape that is narrow at the top and wide at the bottom to form a groove in a shape that is narrow at the top and wide at the bottom.
In some embodiments, only the sidewall 25a on the first region 20a or the second region 20b may be trimmed, so that a trimming mask layer is required to be formed on the hard mask layer 21 before trimming, and the trimming mask layer is required to cover the region not required to be trimmed and expose the region required to be trimmed.
In order to meet the diversity requirement of the CMOS image sensor, in the process of etching the hard mask layer 21 and the substrate 20 to form the first trench and the second trench by using the sidewall 25a as a mask, the substrate 20 may be etched in at least two sub-steps, where the etching conditions of the at least two sub-steps are different, for example, the etching gases and/or the etching gas flows of the at least two sub-steps are different, so that the sidewall of the first trench and the sidewall of the second trench have at least two inclinations.
FIG. 14 is a cross-sectional view of a second trench in an embodiment of the present invention. Referring to fig. 14, when the substrate 20 is etched through at least two sub-steps of different etching conditions, the upper sidewall of the second trench 27 is formed to have a greater inclination than the lower sidewall, and the sidewall profile of the first trench (not shown in fig. 14) is similar to that of the second trench 27. As an example, the substrate 20 is etched by two sub-etching steps to form a first trench and a second trench 27; wherein the etching gas of the first sub-etching step comprises Cl 2 ，Cl 2 The flow rate of HBr is between 30sccm and 60sccm, and the second sub-etching step includes HBr with a flow rate of between 5sccm and 15 sccm, but is not limited thereto. The inclination of the upper sidewall of the trench may be formed to be smaller than that of the lower sidewall.
In the method for manufacturing the CMOS image sensor of the present application, first, a core mold structure 22a is formed on a hard mask layer 21 of a substrate 20, then, a sidewall 25a is formed on a sidewall of the core mold structure 22a, then, the core mold structure 22a is removed, and then, the hard mask layer 21 and the substrate 20 are etched by using the sidewall 25a as a mask, so as to form a first trench 26 in the substrate of a first region 20a and a second trench 27 in the substrate of a second region 20b, which may form the first trench 26 and the second trench 27 having smaller sizes (i.e., critical sizes) at the same time, thereby facilitating reducing the size of the CMOS image sensor and improving the integration level of a chip. In addition, a first distance d1 is formed between adjacent side walls 25a on the first region 20a, a second distance d2 is formed between adjacent side walls 25a on the second region 20b, and by setting different first and second distances d1 and d2, a first trench 26 and a second trench 27 with different depths can be simultaneously formed in the first region 20a and the second region 20b, so that different isolation requirements of the first region 20a and the second region 20b can be simultaneously met, the performance of the CMOS image sensor can be improved, and the number of used masks can be reduced.
Further, after the mandrel structure 22a is removed, the sidewall 25a is used as a mask, before the hard mask layer 21 and the substrate 20 are etched, the first region 20a and/or the second region 20b is used as a trimming region, and the profile of the sidewall 25a on the trimming region is trimmed through an etching process, so that a trench with a set cross-sectional shape is formed in the substrate of the trimming region, and thus, an isolation structure with a set cross-sectional shape can be formed according to actual needs of the CMOS image sensor, which is beneficial to improving the performance of the CMOS image sensor.
It should be noted that the terms "first", "second", "third", and the like in the description are used for distinguishing various components, elements, steps, and the like in the description, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any variations and modifications of the present invention may be made by those skilled in the art without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above, and therefore, any modifications, equivalent variations and modifications made to the above embodiments according to the technical essence of the present invention are within the protection scope of the present invention.
Claims (8)
1. A method for fabricating a CMOS image sensor, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area, and a hard mask layer is formed on the upper surface of the substrate;
forming a core mold structure on the hard mask layer;
forming side walls on the side walls of the core mold structure, and removing the core mold structure; a first space is formed between the adjacent side walls on the first area, and a second space is formed between the adjacent side walls on the second area;
taking the first area and/or the second area as a trimming area, and trimming the profile of the side wall on the trimming area through an etching process; and
etching the hard mask layer and the substrate by taking the side wall as a mask, stopping in the substrate, forming a first groove in the substrate of the first area and forming a second groove in the substrate of the second area;
wherein the first trench and the second trench having different depths are formed by setting the first pitch and the second pitch to be different; forming a groove with a set cross-sectional shape in the substrate of the trimming area by trimming the profile of the side wall on the trimming area; the method for etching the hard mask layer and the substrate comprises the following steps: and etching the substrate in at least two sub-steps, wherein the etching conditions of the at least two sub-steps are different, so that the side wall of the first groove and the side wall of the second groove have at least two gradients.
2. The method of claim 1, wherein the first region is a pixel region and the second region is a logic region; the depth of the first trench is less than the depth of the second trench.
3. The method of claim 1, wherein the forming a mandrel structure on the hard mask layer comprises:
forming a core mold material layer and a patterned first mask layer on the core mold material layer on the upper surface of the hard mask layer;
with the first patterned mask layer as a mask, etching the core mold material layer downwards and stopping on the upper surface of the hard mask layer to form the core mold structure; and
and removing the patterned first mask layer.
4. The method of claim 3, wherein a bottom-up stack of an amorphous carbon layer, a silicon oxycarbide layer, and a bottom anti-reflective layer is disposed between the mandrel material layer and the patterned first mask layer.
5. The method of claim 1, wherein the forming the sidewall on the sidewall of the mandrel structure comprises:
forming a side wall material layer, wherein the side wall material layer covers the side wall and the top surface of the core mold structure and covers the exposed upper surface of the hard mask layer;
and etching to remove the side wall material layer on the top surface of the core mold structure and part of the side wall material layer on the upper surface of the hard mask layer, and reserving the side wall material layer on the side wall of the core mold structure as the side wall.
6. The method of claim 1, wherein the hard mask layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked from bottom to top on the substrate.
7. The method of any one of claims 1 to 6, wherein the first pitch is 45 nm to 55 nm, and the depth of the first trench is 150 nm to 250 nm; the second distance is 55-65 nanometers, and the depth of the second grooves is 270-330 nanometers.
8. The method of claim 1, wherein the method of trimming the profile of the sidewall on the trim region by an etching process comprises: and etching the side walls of the side walls to enable the cross section of the opening between the adjacent side walls in the trimming area to be in a shape with a wide top and a narrow bottom, so that a groove with a cross section in a shape with a wide top and a narrow bottom is formed in the substrate of the trimming area in the subsequent step.
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