TWI803645B - Method for planarizing semiconductor structure - Google Patents

Abstract

A method for planarizing a semiconductor structure is disclosed. An etching back process is performed on a bottom anti-reflective coating, which covers the first trenches with a small width and the second trenches, so that the first trenches and the second trenches are not filled with the bottom anti-reflective coating. A photoresist layer is formed on thebottomanti-reflective coating, and a photolithography processfor the photoresist layer above the first trenches is performedto leave scum on the bottom anti-reflective coating within the first trenches, wherein the surface of the scum within the first trenches areat the same height. Then, the scum and a portion of the bottom anti-reflective coating within the first trench are removed, so that the heights of the remaining bottom anti-reflective coatings within the first trenches are substantially the same.

Description

Method for planarizing semiconductor structures

The invention relates to a semiconductor manufacturing process, in particular to a method for planarizing a semiconductor structure.

In semiconductor integrated circuits, shrinking geometries help increase production efficiency and reduce associated costs. However, as device geometries become smaller, semiconductor devices may cause loading problems, such as undesirably high resistance.

In the semiconductor manufacturing process of forming a field effect transistor (FET) device, a trench is formed on the semiconductor substrate to set a metal gate. Generally, when forming a metal gate, a work function metal layer is first formed in the trench, and then A low-resistance metal layer is formed. When forming the work function metal layer, since the width of the trench on the semiconductor substrate is getting finer, it is difficult to control the height of the work function metal layer in the trench to be at the same height, resulting in the inability of the work function metal layer to have the same height in the trench. The relatively flat height further affects the filling of the low-resistance metal layer deposited later as the metal gate electrode, resulting in the performance of the field effect transistor (FET) device being affected.

The invention provides a method for planarizing a semiconductor structure, which helps to manufacture semiconductor elements with better element characteristics.

The method for planarizing a semiconductor structure provided by the present invention includes: providing a substrate structure, the substrate structure has a first surface, a plurality of first grooves and at least one second groove are formed on the first surface, and the width of the first groove is less than the width of the second trench; forming a work function metal layer to be at least located in the first trench and the second trench; forming an anti-reflection material layer on the first surface of the substrate structure and filling the first trench and the second trench groove; etch back the anti-reflection material layer to remove part of the anti-reflection material layer so that the anti-reflection material layer does not fill the first groove and the second groove; form a photoresist layer on the substrate structure to cover the first surface and an anti-reflection material layer, wherein the photoresist layer has a first part and a second part, the first part corresponds to the distribution area of the first groove, and the second part corresponds to the distribution area of the second groove; a lithography process is performed on the first part to Remaining photoresist residue on the anti-reflection material layer in the first groove; and removing the photoresist residue and part of the anti-reflection material layer in the first groove, so that the remaining anti-reflection material layer in the first groove heights are substantially the same.

In an embodiment of the present invention, the above-mentioned work function metal layer is formed at least on the bottom surface and the inner sidewall of the first trench and the second trench.

In an embodiment of the present invention, before forming the work function metal layer, a gate dielectric layer is formed in the first trench and the second trench.

In an embodiment of the present invention, after the step of etching back the anti-reflection material layer, the height of the anti-reflection material layer in the first trench is higher than the height of the anti-reflection material layer in the second trench.

In one embodiment of the present invention, after the step of etching back the anti-reflective material layer, the anti-reflective material layer in the first groove has a first height, and after the step of photolithography, the photoresist residue has a first height. Two heights, the ratio of the first height to the second height is between 9 and 2.

In an embodiment of the present invention, the above photoresist residue has a second surface, the second surface is lower than the first surface, and the height of the second surface in the first trench is substantially the same.

In an embodiment of the present invention, the removal rates of the photoresist residue and part of the anti-reflection material layer in the first trench are substantially the same.

In an embodiment of the present invention, the width of the above-mentioned first trench is less than 25 nm.

In an embodiment of the present invention, after the heights of the remaining anti-reflection material layers in the first trenches are substantially the same, a metal shrinkage process is further performed to remove part of the work function metal layer in the first trenches.

In an embodiment of the present invention, when the metal shrinkage process is performed, part of the work function metal layer in contact with the remaining anti-reflection material layer will not be removed.

In an embodiment of the present invention, after the metal shrinkage process is performed, the remaining anti-reflection material layer in the first trench, the second part of the photoresist layer, and the anti-reflection material in the second trench are further removed layer.

In the present invention, an etch-back process is first performed on the anti-reflection material layer covering the first groove and the second groove, so that the anti-reflection material layer does not fill the first groove and the second groove, and then covers the photoresist layer on the anti-reflection material layer, and carry out a lithography process on the photoresist layer above the first trench with a smaller width, so as to leave photoresist residues on the anti-reflection material layer in the first trench; and then at the same time removing the photoresist residue and part of the anti-reflection material layer in the first groove, so that the heights of the remaining anti-reflection material layer in the first groove are substantially the same. Therefore, the method for planarizing the semiconductor structure in this embodiment will help to manufacture semiconductor devices with better device characteristics.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10: Substrate structure

101: First Surface

12:Interlayer dielectric

14, 14', 14": the first groove

141: inner wall

142: Bottom

16: Second groove

161: inner wall

162: Bottom

W1, W2`: Width

D: Depth

18: Gate dielectric layer

20, 20': work function metal layer

22, 22': anti-reflection material layer

Z1, Z2: area

H1: first height

24: photoresist layer

24a: Part I

24b: Second part

26: Photoresist residue

261: second surface

H2: second height

R: height difference

T1: first thickness

1A to 1I are cross-sectional schematic diagrams of the process of planarizing a semiconductor structure according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of different thicknesses of an anti-reflection material layer according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a work function metal layer with a uniform height in a first trench according to an embodiment of the present invention.

1A to 1I are cross-sectional schematic diagrams of the process of planarizing a semiconductor structure according to an embodiment of the present invention. As shown in FIG. 1A, a substrate structure 10 is provided. The substrate structure 10 has a first surface 101, and a plurality of grooves are formed on the first surface 101. For example, there is an isolation structure known in the art between the grooves and the grooves, such as nitrogen silicon and/or interlayer dielectric (ILD) 12, in one embodiment, the trench includes a first trench 14 and a second trench 16, the first trench 14 has two opposite inner sidewalls 141 and a bottom surface 142, The second trench 16 has two opposite inner sidewalls 161 and a bottom surface 162. The width W1 of the first trench 14 is smaller than the width W2 of the second trench, wherein the width W1 of the first trench 14 is less than 25 nanometers (nm). In one embodiment, the width W1 of the first groove 14 is between 7 nm and 25 nm, and the first groove 14 and the second groove 16 have a depth D, for example, the depth D is 55 nm. to 100 nm. 1A to 1I show three first trenches 14 and one second trench 16 for illustration, but not limited thereto.

Next, as shown in FIG. 1B , the gate dielectric layer 18 and the work function metal layer 20 are sequentially formed in the first surface 101 , the first trench 14 and the second trench 16 of the substrate structure 10 . The gate dielectric layer 18 includes a high-K dielectric material; the work function metal layer 20 includes a conductive material, such as a metal or a metal compound. In one embodiment, the gate dielectric layer 18 is conformally formed on the inner sidewall 141 and the bottom surface 142 of the first trench 14 , the inner sidewall 161 and the bottom surface 162 of the second trench 16 , and a portion of the first surface 101 , Part of the first surface 101 may be the surface of the interlayer dielectric layer 12 . The work function metal layer 20 conformally covers the gate dielectric layer 18 .

After that, as shown in FIG. 1C , an anti-reflective material layer (Bottom Anti-Reflective Coating; BARC) 22 is formed on the substrate structure and fills up the first trench 14 (marked in FIG. 1A ) and the second trench 16 (marked in FIG. 1A ). Figure 1A). In one embodiment. The anti-reflection material layer 22 can be formed on the work function metal layer 20 by a coating process, the anti-reflection material layer 22 completely fills and protrudes from the first groove 14 and the second groove 16, and the anti-reflection material layer 22 is in the There are different thicknesses above the substrate structure 10 . For example, if the first groove 14 is located in the region Z1 with a higher groove pattern density, the anti-reflection material layer 22 above the first groove 14 is thicker, and the second groove 16 is located in a region with a lower pattern density. area Z2, the anti-reflective material layer 22 above the second trench 16 is relatively thin.

Afterwards, the first etch-back process is carried out to etch back the anti-reflective material layer 22 to remove part of the anti-reflective material layer 22, as shown in FIG. 1D, so that the anti-reflective material layer 22 does not fill the first trench 14 and For the second trench 16 , in one embodiment, the height of the anti-reflection material layer 22 in the first trench 14 is higher than the height of the anti-reflection material layer 22 in the second trench 16 . In one embodiment, after the first etch-back process is performed, the anti-reflection material layers 22 in the plurality of first trenches 14 have a first height H1, and the first heights H1 are not uniform. Wherein, the first etch-back process only etches the anti-reflective material layer 22 and does not etch materials other than the anti-reflective material layer 22. As shown in FIG. 1D, the work function metal layer 20 will not be affected by the etch-back process and remains Located on the first surface 101 of the substrate structure 10 and in the first groove 14 /the second groove 16 .

Next, as shown in FIG. 1E, a photoresist layer 24 is formed on the substrate structure 10 to cover the work function metal layer 20 and the anti-reflection material layer 22, wherein the photoresist layer 24 can be divided into a first part 24a and a second part 24b , the first portion 24a corresponds to the distribution area Z1 of the first groove 14 (marked in FIG. 1A ), and the second portion 24b corresponds to the distribution area Z2 of the second groove 16; afterward, the first portion 24a of the photoresist layer 24 is lithographically process, in one embodiment, the photolithography process includes exposure and development, for example, wherein the photoresist layer 24 in the first trench 14 will interact with nitrogen during the exposure process, thereby generating photoresist poisoning (poison) so that Amine (NHx) photoresist residue (scum) 26 remains in the first groove during the developing step On the anti-reflection material layer 22 in the groove 14, as shown in FIG. H2 is not consistent. For the same first trench 14 , the ratio of the first height H1 (shown in FIG. 1D ) to the second height H2 is between 9 and 2. The photoresist residue 26 has a second surface 261, and the heights of the second surface 261 of the photoresist residue 26 remaining in the plurality of first grooves 14 are substantially the same, and the second surface 261 can be lower than or equal to the height For the first surface 101 of the substrate structure 10 , in one embodiment, the height difference R between the second surface 261 and the first surface 101 is between 0 and 10 nm.

Afterwards, under the premise that the second portion 24b of the photoresist layer 24 still covers the second groove distribution area Z2, a second etch-back process is performed to remove the photoresist residue 26 and the first groove 14 (marked in FIG. 1A ) part of the anti-reflection material layer 22. In one embodiment, when performing the second etch-back process, the removal rates of the photoresist residue 26 and part of the anti-reflective material layer 22 in the first trench 14 are substantially the same, as shown in FIG. 1G , so that the second etch-back After the process, the heights of the remaining anti-reflection material layers 22 ′ in the plurality of first trenches 14 are substantially the same.

Next, under the premise that the second portion 24b of the photoresist layer 24 still covers the second groove distribution area Z2, a metal shrinkage process is performed to remove the work function metal layer 20 not protected by the second portion 24b of the photoresist layer 24. . In one embodiment, the metal shrinking process includes an etching process, wherein the etchant will remove the material of the work function metal layer 20 but will not affect other materials, so after performing the metal shrinking process, the portion deposited on the first surface 101 The work function metal layer 20 and part of the work function metal layer 20 on the inner wall 141 of the first trench 14 will be removed, as shown in FIG. The contacted portion of the work function metal layer 20' will not be removed. Wherein, since the remaining anti-reflection material layer 22' in the first groove 14 has substantially the same height, the part of the work in the first groove 14 that will not be removed due to contact with the remaining anti-reflection material layer 22' The heights of the functional metal layers 20' are also substantially the same.

Next, remove the second portion 24b of the photoresist layer 24, the anti-reflection material layer 22 in the second trench 16, and the remaining anti-reflection material layer 22' in the first trench 14 to expose the second trench 16. And the work function metal layer 20 on the first surface 101 around the second trench 16, and the work function metal layer 20' in the first trench 14, as shown in FIG. 1I, wherein the plurality of first trenches 14 The heights of the work function metal layers 20 ′ are consistent, and the heights of the work function metal layers 20 ′ in the first trench 14 are smaller than the heights of the work function metal layers 20 in the second trench 16 .

After that, in an embodiment not shown in the follow-up, a low-resistance metal layer can be formed in the first trench 14 and the second trench 16, so that the low-resistance metal layer is located in the work function metal layer 20, 20' and fill the first trench 14 and the second trench 16 . In one embodiment, a planarization process, such as a chemical mechanical polishing process, is further performed to remove the redundant low-resistance metal layer outside the first trench 14 and the second trench 16 and the gate on the first surface 101 The dielectric layer 18 and the work function metal layer 20 are used to complete the fabrication of the metal gate electrode.

In the above-mentioned embodiment, the deposition thickness of the anti-reflection material layer 22 is related to the density of the groove patterns. In one embodiment, the anti-reflection material layer 22 above the area with a higher density of groove patterns is thicker. The anti-reflection material layer 22 is thinner in the region where the concentration of groove patterns is lower. Fig. 2 is a schematic diagram of different thicknesses of the anti-reflection material layer according to an embodiment of the present invention. The thickness of the anti-reflection material layer 22 above the grooves 14, 14' is relatively thick, for example, it has a first thickness T1, and one of the first grooves 14' is adjacent to the second groove 16 with a larger width, so that the first groove 14 'The thickness of the upper anti-reflection material layer 22 is slightly smaller than the first thickness T1, and there is another first groove 14" surrounded by two second grooves 16 with larger widths, then the upper part of the first groove 14" The thickness of the anti-reflection material layer 22 is also slightly smaller than the first thickness T1. Also as shown in FIG. 2 , a work function metal layer 20 is formed in the first trenches 14 , 14 ′, 14 ″ and the second trench 16 . 14 ′, 14 ″/a gate dielectric layer (not shown) exists between the inner sidewall and the bottom surface of the second trench 16 .

Fig. 3 is a schematic diagram of a work function metal layer with a uniform height in the first trench according to an embodiment of the present invention, wherein the pattern of the first trench and the second trench on the substrate structure is the same as that of the embodiment shown in Fig. 2 , in the embodiment shown in FIG. 2, the deposition thickness of the anti-reflection material layer 22 is different, and in the method for planarizing the semiconductor structure according to the embodiment shown in the above-mentioned FIG. 1D to FIG. The reflective material layer 22 is first etched back for the first time, so that the anti-reflective material layer 22 does not fill the first trenches 14, 14', 14" and the second trenches 16, and then covers the photoresist layer 24 (marked In FIG. 1E ) on the anti-reflection material layer 22, and for the photoresist layer 24 above the first grooves 14, 14', 14" with a smaller width, the lithography process is carried out, so that the first grooves 14, 14' , 14 "on the anti-reflection material layer 22, photoresist residue 26 (marked in Fig. 1F) remains, and then the photoresist residue 26 and part of the anti-reflection material in the first trenches 14, 14', 14" are removed simultaneously layer 22, so that the heights of the remaining anti-reflective material layer 22' in the first grooves 14, 14', 14" are substantially the same, and then the remaining photoresist layer 24 and anti-reflective material layer are removed in the subsequent metal shrinkage process After 22, the heights of the work function metal layers 20' in the plurality of first trenches 14, 14', 14" are all consistent.

According to the above, in the present invention, photoresist residues remain on the anti-reflection material layer in the first trench with a smaller width, and the surface heights of the photoresist residues in the first trenches are substantially the same; then the photoresist residues are removed and part of the anti-reflective material layer in the first trench, so that the heights of the remaining anti-reflective material layer in the first trench are substantially the same; furthermore, after the subsequent metal shrinkage process, the work function metal layer in the first trench has Relatively flat height, therefore, can improve the flatness of the low-resistance metal that is subsequently deposited as the metal gate, so that the metal gate electrode has better performance and helps to manufacture semiconductor devices with better device characteristics.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

101: First Surface

20: Work function metal layer

22: Anti-reflection material layer

Z2: area

24: photoresist layer

24b: Second part

26: Photoresist residue

261: second surface

H2: second height

R: height difference

Claims (11)

A method of planarizing a semiconductor structure, comprising: A substrate structure is provided, the substrate structure has a first surface, a plurality of first grooves and at least one second groove are formed on the first surface, the width of the first grooves is smaller than that of the second grooves width; forming a work function metal layer to be located at least in the first trenches and the second trenches; forming an anti-reflection material layer on the first surface of the substrate structure and filling the first grooves and the second grooves; Etching back the anti-reflection material layer to remove part of the anti-reflection material layer so that the anti-reflection material layer does not fill the first grooves and the second grooves; forming a photoresist layer on the substrate structure to cover the first surface and the anti-reflective material layer, wherein the photoresist layer has a first portion and a second portion, the first portion corresponds to the first grooves distribution area, the second part corresponds to the distribution area of the second trench; performing a lithography process on the first portion to leave a photoresist residue on the anti-reflective material layer in the first grooves; and The photoresist residue and part of the anti-reflection material layer in the first grooves are removed, so that the remaining heights of the anti-reflection material layer in the first grooves are substantially the same. The method for planarizing a semiconductor structure as claimed in claim 1, wherein the work function metal layer is formed at least on the bottom surfaces and inner sidewalls of the first trenches and the second trenches. The method for planarizing a semiconductor structure as claimed in claim 1, wherein, before forming the work function metal layer, a gate dielectric layer is formed in the first trenches and the second trenches. The method for planarizing a semiconductor structure as claimed in claim 1, wherein, after the step of etching back the antireflection material layer, the height of the antireflection material layer in the first trenches is higher than that of the second trenches The height of the layer of anti-reflection material inside the groove. The method for planarizing a semiconductor structure as claimed in claim 1, wherein, after the step of etching back the antireflective material layer, the antireflective material layer in the first trenches has a first height, and After the photolithography process step, the photoresist residue has a second height, and the ratio of the first height to the second height is between 9 and 2. The method for planarizing a semiconductor structure as claimed in claim 1, wherein the photoresist residue has a second surface, the second surface is lower than the first surface, and the second surface is above the first grooves The heights inside are substantially the same. The method for planarizing a semiconductor structure as claimed in claim 1, wherein the removal rates of the photoresist residue and part of the anti-reflection material layer in the first trenches are substantially the same. The method for planarizing a semiconductor structure as claimed in claim 1, wherein the width of the first trenches is less than 25 nm. The method for planarizing a semiconductor structure as claimed in claim 1, wherein after the heights of the remaining anti-reflective material layers in the first trenches are substantially the same, a metal shrinkage process is further performed to remove the layers A portion of the work function metal layer within the first trench. The method for planarizing a semiconductor structure as claimed in claim 9, wherein when the metal shrinkage process is performed, the part of the work function metal layer in contact with the remaining anti-reflection material layer will not be removed. The method for planarizing a semiconductor structure according to claim 10, wherein after the metal shrinkage process is performed, the remaining anti-reflective material layer and the first photoresist layer in the first trenches are further removed Two parts, and the anti-reflection material layer in the second groove.

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