CN102909639B - The surface treatment method of Semiconductor substrate - Google Patents
The surface treatment method of Semiconductor substrate Download PDFInfo
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- CN102909639B CN102909639B CN201210422897.8A CN201210422897A CN102909639B CN 102909639 B CN102909639 B CN 102909639B CN 201210422897 A CN201210422897 A CN 201210422897A CN 102909639 B CN102909639 B CN 102909639B
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Abstract
The invention provides a kind of surface treatment method of Semiconductor substrate and the preparation method of Semiconductor substrate.The surface treatment method of described Semiconductor substrate comprises the steps: to provide semi-conductive substrate; Grind a surface of thinning described Semiconductor substrate; Adopt the polished thinning surface of Semiconductor substrate described in oxide slurry polishing; Adopt the polished thinning surface of Semiconductor substrate described in the polishing of Semiconductor substrate polishing slurries.The invention has the advantages that, grinding technics can form one deck natural oxidizing layer on the surface of Semiconductor substrate, present invention employs and the oxide slurry of natural oxidizing layer of corrosion resistant semiconductor substrate can implement polishing to Semiconductor substrate, ensure before to the machine glazed finish of Semiconductor substrate surface chemistry, the surface of Semiconductor substrate is definitely without any unnecessary material, avoids the mechanical strength of different material difference to impact grinding.
Description
Technical field
The present invention relates to field of semiconductor materials, particularly relate to a kind of surface treatment method of Semiconductor substrate and the preparation method of Semiconductor substrate.
Background technology
Body silicon and SOI material are collectively referred to as silica-base material, are microelectronic basic materials, are widely applied to the every field of integrated circuit.For SOI material, by the thickness of its top layer silicon thin layer, thin film SOI (top layer silicon is less than 1 μm usually) and the large class of thick film SOI (top layer silicon is greater than 1 μm usually) two can be divided into.The application in thin film SOI market 95% concentrates on 8 inches and 12 inches, and wherein most user is the guide of most advanced and sophisticated microelectric technique, as IBM, AMD, Motorola, Intel, UMC, TSMC, OKI etc.Current supplier is Japanese SHIN-ETSU HANTOTAI (SEH), French Soitec, Japanese SUMCO, has wherein supplied the about product of more than 90% for first two.The main driving force in thin film SOI market comes from a high speed, low-power consumption product, particularly microprocessor (CPU) application.These products with high content of technology, added value is large, is the tap of whole integrated circuit.
Much the report of SOI is all concentrated in these breathtaking tip application above, and the application that in fact SOI is early stage concentrates on Aero-Space and military field, is extended to now power and smart material and MEMS and applies.Particularly in automotive electronics, display, wireless telecommunications etc., development is rapid.Because the control of power supply and conversion, automotive electronics and consumer power device aspect are to the requirement of adverse circumstances, high temperature, big current, high power consumption aspect, the strict demand in reliability is made to have to adopt SOI device.At these field many employings thick film SOI materials, concentrate on 6 inches and 8 inches, current user comprises the U.S. Maxim, ADI, TI (USA), Japan NEC, Toshiba, Panasonic, Denso, TI (Japan), FUJI, Omron etc., European Philips, X-Fab etc.The feature in this field is that SOI device technology is relatively ripe, and technology content is relatively low, and the profit of device also reduces relatively, responsive to the price comparison of SOI material.Inside these SOI material users, very large application is mainly derived from the drive circuit in various application: be applied to as Maxim the amplifier circuit being mainly the mobile phone section of acceptance; Panasonic, TI, FUJI, Toshiba, NEC etc. are mainly used in the scan drive circuit in display driver circuit; The application of DENSO is mainly at automotive electronics, wireless radio frequency circuit etc.; The application of Toshiba is even in the power control circuit of air-conditioning; Omron is mainly in sensor; ADI is also main at high temperature circuit, sensor; The application of the Phillips LDMOS then mainly in power device, in consumer electronics as automobile audio, audio frequency, audio-frequency amplifier etc.; The Magnchip (Hynix) of Korea S is then for Kopin produces for the display driver circuit of digital camera and the PDP display driver circuit etc. for LG production.
At present, the main technology of preparing of thick film SOI material is bonding and back side corrosion technology (BESOI), and it has, and technique is simple, low cost and other advantages, is therefore subject to people's attention.First BESOI technology adopts the thinning top layer silicon of the way of grinding, forms the grinding damage layer of an a few micron thickness in the process on its surface.Therefore, need subsequently to adopt chemically mechanical polishing (CMP) polishing remove damage layer and reduce its surface roughness to reach the requirement of CMOS technology.And experiment shows, polishing can cause the top layer silicon thickness evenness of SOI to reduce, and the larger whole top layer silicon uniformity of CMP removal amount is poorer.How to reduce the CMP after grinding to the impact of top layer silicon gross thickness confonnality deviations, this is that those skilled in that art face but insurmountable problem always for a long time.
Summary of the invention
Technical problem to be solved by this invention is, provides a kind of surface treatment method of Semiconductor substrate and the preparation method of Semiconductor substrate, improves the flatness after substrate surface polishing.
In order to solve the problem, the invention provides a kind of surface treatment method of Semiconductor substrate, comprise the steps: to provide semi-conductive substrate; Grind a surface of thinning described Semiconductor substrate; Adopt the polished thinning surface of Semiconductor substrate described in oxide slurry polishing; Adopt the polished thinning surface of Semiconductor substrate described in the polishing of Semiconductor substrate polishing slurries.
Optionally, the step on the polished thinning surface of Semiconductor substrate described in the polishing of described employing oxide slurry is adopt twin polishing technique further; The step on the polished thinning surface of Semiconductor substrate described in the polishing of described employing Semiconductor substrate polishing slurries is adopt single-sided polishing technique further.
Optionally, the step on the polished thinning surface of Semiconductor substrate described in the polishing of described employing oxide slurry is adopt single-sided polishing technique further; The step on the polished thinning surface of Semiconductor substrate described in the polishing of described employing Semiconductor substrate polishing slurries, is adopt single-sided polishing technique further, and comprises rough polishing step and meticulous polishing step.
Invention further provides a kind of preparation method of Semiconductor substrate, comprise the steps: to provide support substrate; Grind a surface of thinning support substrates; Adopt the polished thinning surface of Semiconductor substrate described in oxide slurry polishing; Adopt the polished thinning surface of Semiconductor substrate described in the polishing of Semiconductor substrate polishing slurries; Device substrate is provided; Insulating barrier is formed at the polished surface of device substrate and/or a surface of support substrates; Take insulating barrier as intermediate layer, support substrates and device substrate are bonded together.
Optionally, the exposed surface grinding thinning described device substrate is comprised the steps: further; Adopt the polished thinning surface of device substrate described in oxide slurry polishing; Adopt the polished thinning surface of device substrate described in the polishing of Semiconductor substrate polishing slurries.
The invention has the advantages that, grinding technics can form one deck natural oxidizing layer on the surface of Semiconductor substrate, present invention employs and the oxide slurry of natural oxidizing layer of corrosion resistant semiconductor substrate can implement polishing to Semiconductor substrate, ensure before to the machine glazed finish of Semiconductor substrate surface chemistry, the surface of Semiconductor substrate is definitely without any unnecessary material, avoids the mechanical strength of different material difference to impact grinding.
Accompanying drawing explanation
It is the implementation step schematic diagram of the surface treatment method detailed description of the invention of Semiconductor substrate of the present invention shown in accompanying drawing 1.
It is the process chart of method shown in accompanying drawing 1 shown in accompanying drawing 2A to accompanying drawing 2D.
It is the implementation step schematic diagram of the preparation method detailed description of the invention of Semiconductor substrate of the present invention shown in accompanying drawing 3.
Detailed description of the invention
Elaborate below in conjunction with the detailed description of the invention of accompanying drawing to the surface treatment method of Semiconductor substrate provided by the invention and the preparation method of Semiconductor substrate.
First the detailed description of the invention of the surface treatment method of Semiconductor substrate of the present invention is provided by reference to the accompanying drawings.
Be the implementation step schematic diagram of this detailed description of the invention shown in accompanying drawing 1, comprise: step S100, semi-conductive substrate is provided; Step S110, grinds a surface of thinning described Semiconductor substrate; Step S120, adopts the polished thinning surface of Semiconductor substrate described in oxide slurry polishing; Step S130, adopts the polished thinning surface of Semiconductor substrate described in the polishing of Semiconductor substrate polishing slurries.
It is the process chart of this detailed description of the invention shown in accompanying drawing 2A to accompanying drawing 2D.
Shown in accompanying drawing 2A, refer step S100, provides semi-conductive substrate 200.Described Semiconductor substrate 200 can be comprise the common Semiconductor substrate of any one of monocrystalline substrate, and this detailed description of the invention is for monocrystalline silicon.
Shown in accompanying drawing 2B, refer step S110, grinds a surface of thinning described Semiconductor substrate 200.This step can form one deck natural oxidizing layer 220 on the surface of damage.
The object of this step is the total thickness deviation reducing Semiconductor substrate 200.Milling apparatus can be wire cutting machine or twin grinder, and be preferably single-sided lapping machine, first roughly grind thinning fast, grinding wheel speed is greater than 2000rpm, and fine grinding reduces to grind the damage caused subsequently, and grinding wheel speed is greater than 2000rpm.This technique can rapid thinning Semiconductor substrate 200, but also can form grinding damage on the surface of Semiconductor substrate 200 simultaneously, and through carefully studying discovery to grinding technics, grind in thinning process, speed lapping can produce high temperature, although there is water-cooled, still one deck natural oxidizing layer 220 can be formed on the surface of damage.
Shown in accompanying drawing 2C, refer step S120, adopts the polished thinning surface of Semiconductor substrate 200 described in oxide slurry polishing.The natural oxidizing layer 220 that Semiconductor substrate 200 is polished thinning surface by this step removes.
Natural oxidizing layer 220 owing to being that the material of Semiconductor substrate 200 is formed under high-temperature oxydation, therefore its mechanical strength and Semiconductor substrate 200 itself normally inconsistent.In follow-up CMP process, polishing fluid is by SiO
2throwing slurry composition, is therefore pass through SiO to the polishing of the surperficial natural oxidizing layer 220 of Semiconductor substrate 200
2mechanical lapping realize, in this process due to impact that the mechanical strength of natural oxidizing layer 220 mechanical strength and Semiconductor substrate 200 is inconsistent, polishing is uneven to the removal amount of Semiconductor substrate 200, therefore can cause after polishing or Semiconductor substrate 200 thickness evenness reduce, and the chemically mechanical polishing time is longer, and thickness evenness is poorer.
On the basis finding this problem, present invention employs and the oxide slurry of natural oxidizing layer 220 of corrosion resistant semiconductor substrate 200 can implement polishing to Semiconductor substrate 200, ensure before to the machine glazed finish of Semiconductor substrate 200 surface chemistry, the surface of Semiconductor substrate 200 is definitely without any unnecessary material, avoid the mechanical strength of different material difference to impact grinding, improve the flatness of substrate surface.Those skilled in the art can select polishing fluid and the polishing mode of heterogeneity according to actual conditions.Polishing mode can be single-sided polishing or twin polishing, or both combinations, and polishing fluid can be chosen flexibly according to backing material.
If integrated artistic adopts the combination of one side and twin polishing, then this step is twin polishing, injects oxide slurry, and oxide cmp slurry is less than 1:100 with the ratio of water, and polishing time is less than 10 minutes.If integrated artistic adopts single-sided polishing, then this step is single-sided polishing, injects special oxide slurry, and oxide cmp slurry is less than 1:100 with the ratio of water, and polishing time is less than 10 minutes.
Shown in accompanying drawing 2D, refer step S130, adopts the polished thinning surface of Semiconductor substrate 200 described in the polishing of Semiconductor substrate polishing slurries.The object of this step is the polished thinning surface planarisation of Semiconductor substrate 200.
If what step S120 adopted is twin polishing technique, then this step is single-sided polishing, first implements rough polishing, uses rough polishing slurry, throws slurry and is less than for 1:100 with the ratio of water; In the meticulous polishing of enforcement, in meticulous polishing, essence throws slurry should be less than 1:100 with the ratio of water, and the total polishing removal amount of this step is not more than 8 microns.Rough polishing process can not also be adopted, and the Semiconductor substrate 200 after the HF acid treatment twin polishing of 5%HF or 10% should be selected, soak and be no more than 5 minutes, directly implement meticulous polishing subsequently, essence throws slurry should be less than 1:100 with the ratio of water, and total polishing removal amount is not more than 8 microns.
If what step S120 adopted is single-sided polishing, then this step is single-sided polishing, first implements rough polishing, uses rough polishing slurry, throws slurry and is less than for 1:100 with the ratio of water; In the meticulous polishing of enforcement, in meticulous polishing, essence throws slurry should be less than 1:100 with the ratio of water, and the total polishing removal amount of this step is not more than 8 microns.
Next the detailed description of the invention of the preparation method of Semiconductor substrate of the present invention is provided by reference to the accompanying drawings.
Be the implementation step schematic diagram of this detailed description of the invention shown in accompanying drawing 3, comprise: step S300, provide support substrate; Step S311, grinds a surface of thinning support substrates; Step S312, adopts the polished thinning surface of Semiconductor substrate described in oxide slurry polishing; Step S313, adopts the polished thinning surface of Semiconductor substrate described in the polishing of Semiconductor substrate polishing slurries; Step S321, provides device substrate; Step S322, forms insulating barrier at the polished surface of device substrate and/or a surface of support substrates; Step S323, take insulating barrier as intermediate layer, support substrates and device substrate is bonded together; Step S331, grinds the exposed surface of thinning described device substrate; Step S332, adopts the polished thinning surface of device substrate described in oxide slurry polishing; Step S333, adopts the polished thinning surface of device substrate described in the polishing of Semiconductor substrate polishing slurries.
The wherein enforcement of step S300 to step S313, please refer to last detailed description of the invention, repeats no more herein.
Step S322, form insulating barrier at the polished surface of device substrate and/or a surface of support substrates, can adopt oxidation technology, also can adopt PECVD or LPCVD deposition insulating layer, dielectric can be silica also can be silicon nitride.Optimization Technology is the thermal oxidation technology of standard, and oxidizing condition can wet oxygen also can be dry oxygen, and oxidation technology depends on the oxidated layer thickness of needs, and temperature is 900-1400 DEG C, wet-oxygen oxidation, and oxidated layer thickness need determine according to the thickness of final SOI.
This bonding can be hydrophilic bonding can be also hydrophobic bonding, is optimized for hydrophilic bonding.Now, the hydrophilic bonding of plasma asistance can be selected also can be common hydrophilic bonding.
Step S323, take insulating barrier as intermediate layer, support substrates and device substrate are bonded together, if using plasma assists hydrophilic bonding, first adopt Ar or N2 or O2 ion pair surface to process, carry out annealing subsequently to reinforce, annealing temperature is 50-700 DEG C, is optimized for 300 DEG C, and annealing time is that 10min was by 10 hours, be optimized for 2.5 hours, annealing atmosphere is oxygen, argon gas, nitrogen or its mist.If adopt traditional hydrophilic or hydrophobic bonding, reinforcing temperature is 800-1400 DEG C, and annealing time is 0.5-10 hour, and annealing atmosphere is oxygen, argon gas, nitrogen or its mist.
After bonding, can also select as required to carry out chamfering.Chamfering width is determined by customer specifications, is generally 1.5mm.Substrate after chamfering is corroded in TMAH solution, removes the remaining silicon layer in 100 microns of edges.The way optimized is the way adopting spin etching, sprays TMAH corrosive liquid, and in corrosion process, substrate is to rotating, and rotating speed is 100-10000rpm, is optimized for 1000rpm, and TMAH temperature optimization is 95 DEG C.
Substrate after bonding, if the thickness of device substrate exceedes actual demand, can also carry out reduction processing to device substrate, thinningly can adopt method described in step S331 to step S333, to improve the flatness of device substrate surface.Implementation process please refer to last detailed description of the invention, repeats no more herein.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (1)
1. a preparation method for Semiconductor substrate, is characterized in that, comprises the steps:
Provide support substrate;
One surface of the thinning support substrates of mechanical lapping;
Adopt the polished thinning surface of support substrates described in oxide slurry polishing, described oxide slurry refers to can the slurry of natural oxidizing layer of corrosion resistant support substrate;
Adopt the polished thinning surface of support substrates described in the polishing of Semiconductor substrate polishing slurries;
Device substrate is provided;
Insulating barrier is formed at the polished surface of device substrate and/or a surface of support substrates;
Take insulating barrier as intermediate layer, support substrates and device substrate are bonded together, form Semiconductor substrate;
Grind the exposed surface of thinning described device substrate;
Adopt the polished thinning surface of device substrate described in oxide slurry polishing, described oxide slurry refers to can the slurry of natural oxidizing layer of corrosion device substrate;
Adopt the polished thinning surface of device substrate described in the polishing of Semiconductor substrate polishing slurries.
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| CN104681404A (en) * | 2013-11-27 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Production method of contact holes and wet cleaning method of semiconductor device |
| CN109290853B (en) * | 2017-07-24 | 2021-06-04 | 蓝思科技（长沙）有限公司 | Preparation method of ultrathin sapphire sheet |
| CN111515792A (en) * | 2020-04-28 | 2020-08-11 | 福建晶安光电有限公司 | Substrate material suitable for graphene growth and manufacturing method thereof |
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| US5225034A (en) * | 1992-06-04 | 1993-07-06 | Micron Technology, Inc. | Method of chemical mechanical polishing predominantly copper containing metal layers in semiconductor processing |
| US5340370A (en) * | 1993-11-03 | 1994-08-23 | Intel Corporation | Slurries for chemical mechanical polishing |
| JP3371775B2 (en) * | 1997-10-31 | 2003-01-27 | 株式会社日立製作所 | Polishing method |
| KR20010046395A (en) * | 1999-11-12 | 2001-06-15 | 안복현 | Composition for cmp polishing |
| CN102074472A (en) * | 2009-11-24 | 2011-05-25 | 上海华虹Nec电子有限公司 | Method for improving chemical mechanical polishing efficiency of silicon |
| CN101901753B (en) * | 2010-06-25 | 2012-05-23 | 上海新傲科技股份有限公司 | Method for preparing thick-film material with insulating embedded layer |
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