CN103241708A - Preparation method of substrate with cavity - Google Patents
Preparation method of substrate with cavity Download PDFInfo
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- CN103241708A CN103241708A CN2013101753225A CN201310175322A CN103241708A CN 103241708 A CN103241708 A CN 103241708A CN 2013101753225 A CN2013101753225 A CN 2013101753225A CN 201310175322 A CN201310175322 A CN 201310175322A CN 103241708 A CN103241708 A CN 103241708A
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Abstract
The invention provides a preparation method of a substrate with a cavity. The preparation method comprises the following steps of: providing a support substrate and a device substrate, wherein a groove is formed in the surface, which is used for bonding, of the support substrate, the support substrate and the device substrate are bonded together under a vacuum environment, and the device substrate is thinned to reach a preset thickness. The preparation method has the advantages that the bonding is carried out in the vacuum environment, and thus the pressure is applied to the cavity from outside to inside even if the device substrate is thinned, and the pressure only plays a role in reinforcing the bonding joint surface between the support substrate and the device substrate without smashing a device.
Description
Technical field
The present invention relates to Semiconductor substrate and make the field, relate in particular to a kind of preparation method who has the substrate of cavity.
Background technology
Bonding and thinning back side (BESOI) technology is the most ripe and business-like SOI technology at present.This technology is that the silicon chip after two oxidations is bonded together as support substrates and device substrate respectively, reinforce more than 2 hours being higher than under 1000 ℃ the temperature subsequently, adopt modes such as grinding, polishing that device substrate is thinned to the needed thickness of SOI device then, namely obtain final bonding SOI wafer.The BESOI technology has simple, the low cost and other advantages of technology, therefore is subjected to the attention of industry.
Have the SOI material (Cavity-SOI) of cavity as a kind of novel SOI material, compare with common SOI material, its supporter has been left specific hole by photoetching and etching technics before bonding, and these holes form specific graphical distribution on the surface.The development of MEMS technology, at pressure sensor, the increasing Cavtiy SOI material of using in the MEMS application such as gyroscope.In the process of preparation Cavity-SOI material, because the existence of these holes, make that the contact area of bonding part greatly reduces on the supporter, and distinctive cavity structure, follow-up process will directly be influenced, the device layer of hole top is not owing to support, and top layer silicon thickness is more thin, more easy the damage by mechanical stress in the mechanical lapping process and produce damaged situation.
Summary of the invention
Technical problem to be solved by this invention is, a kind of preparation method who has the substrate of cavity is provided, and can reduce the fragment rate of substrate in preparation process.
In order to address the above problem, the invention provides a kind of preparation method who has the substrate of cavity, comprise the steps: to provide support substrate and device substrate, described support substrates is used for having groove in the surface of bonding; Under vacuum environment, support substrates and device substrate are bonded together; The attenuate device substrate is to predetermined thickness.
Optionally, the pressure limit of described vacuum environment is 10Pa ~ 0.3Pa.
Optionally, the surface coverage oxide layer of described support substrates.
Optionally, described oxide layer also covers the inwall of described groove.
Optionally, the material of described support substrates and device substrate is monocrystalline silicon.
Optionally, further comprise etch stop layer in the described device substrate.
Optionally, described device substrate has different resistivity with support substrates.
The invention has the advantages that, bonding carries out in a vacuum, even the device substrate attenuation, the pressure of outer bound pair cavity also is ecto-entad, this pressure only can play the effect of reinforcing to the bonding faying face between support substrates and the device substrate, and can not cause fragment.
Description of drawings
It is the implementation step schematic diagram of the described method of the specific embodiment of the present invention shown in the accompanying drawing 1.
Accompanying drawing 2A is to shown in the accompanying drawing 2F being the process chart of said method.
The specific embodiment
Elaborate below in conjunction with the specific embodiment of accompanying drawing to the preparation method of a kind of substrate that has a cavity provided by the invention.
It is the implementation step schematic diagram of the described method of this specific embodiment shown in the accompanying drawing 1, comprise: step S101, provide support substrate and device substrate, comprise etch stop layer: step S102 in the described device substrate, in the surface of described support substrates for bonding, form groove; Step S103 forms oxide layer on the surface of described support substrates, and described oxide layer further covers the inwall of described groove; Step S110 is bonded together support substrates and device substrate under vacuum environment; Step S121, the corrosion device substrate is to etch stop layer; Step S122 continues the surface that the polishing device substrate is corroded, to predetermined thickness.
Accompanying drawing 2A is to shown in the accompanying drawing 2F being the process chart of said method.
Shown in the accompanying drawing 2A, refer step S101 provides support substrate 200 and device substrate 210, comprises etch stop layer 211 in the described device substrate.Described etch stop layer 211 is used for controlling the erosion removal amount more accurately at follow-up reduction process, accurately obtains predetermined thickness.In this specific embodiment, the material of support substrates 200 and device substrate 210 is monocrystalline silicon, and in other the specific embodiment, the material of above-mentioned two substrates can be selected from any common semiconductor substrate materials.Support substrates 200 can have different resistivity with device substrate 210.
Shown in the accompanying drawing 2B, refer step S102 forms groove 201 in the surface of described support substrates 200 for bonding.This specific embodiment in other the specific embodiment, can further comprise more or groove still less 201 with 4 grooves 201 for example.Form groove and can adopt photoetching and corroding method, described corrosion can be dry etching or wet etching.
Shown in the accompanying drawing 2C, refer step S103 forms oxide layer 220 on the surface of described support substrates 200, and described oxide layer 220 further covers the inwall of described groove 201.The method that forms oxide layer 220 can be chemical vapor deposition method etc., is under the situation of monocrystalline silicon for support substrates 200 materials, and oxide layer 220 also can be the silica that adopts thermal oxidation technology to form.Above-mentioned two kinds of technologies can form oxide layer 220 on the surface of support substrates 200 and the inwall place of groove 201 simultaneously.If do not wish in groove to form oxide layer 220, also can be again to remove this processing steps of oxide layer 220(of groove 201 inwalls by the method for selective corrosion not shown).
After above-mentioned steps is implemented to finish, has the support substrates 200 that is formed cavity by groove 201 in the surface of formation bonding.Oxide layer 220 is optional layers, can determine to add or omit according to the needs of subsequent device technology to substrat structure.
Shown in the accompanying drawing 2D, refer step S110 is bonded together support substrates 200 and device substrate 210 under vacuum environment.Be bonded under the vacuum environment and carry out, further selective annealing reinforcing after bonding is finished.Bonding is finished the cavity that rearward recess 201 changes confined space into, owing to bonding carries out under vacuum environment, so groove 201 inside behind the bonding also should be vacuum.The pressure limit of described vacuum environment is 10Pa ~ 0.3Pa.
Shown in the accompanying drawing 2E, refer step S121, corrosion device substrate 210 is to etch stop layer 211.Etch stop layer 211 for example can be oxide layer or heavily doped layer etc., and this step is further selected the suitable selectivity etching process according to the character of etch stop layer 211.It is an optional technical scheme that etch stop layer 211 is set in device substrate 210, and purpose is better to control reduction process.If etch stop layer 211 is not set, then need the corrosion rate of accurate Calculation etching process, the control corrosion stops at the position that needs.
Shown in the accompanying drawing 2F, refer step S122 continues the surface that polishing device substrate 210 is corroded, to predetermined thickness.The surface that is corroded is coarse, handles so need further to adopt glossing that it is carried out Surface Machining.
Above-mentioned corrosion and glossing all carry out under normal pressure.If the bonding of step S110 also carries out under normal pressure, because can at first forming all around of the process further groove 201 of bonding is airtight, slightly compression forms stable bonding surface again, so the air pressure in the cavity can be slightly larger than normal pressure.Like this in attenuate and glossing implementation process, the device substrate 210 of cavity correspondence position can be subjected to pressure from inside to outside, continuous attenuation along with device substrate 210, this pressure can cause the bonding faying face between support substrates 200 and the device substrate 210 to break away from, make device substrate 210 lose support, cause the generation of fragment.And in the described technology of this specific embodiment, because bonding carries out in a vacuum, even device substrate 210 attenuation, the pressure of outer bound pair cavity also is ecto-entad, this pressure only can play the effect of reinforcing to the bonding faying face between support substrates 200 and the device substrate 210, and can not cause fragment.Experiment shows, adopts above-mentioned vacuum bonding technology, and the minimum thickness behind the attenuate can be in 0.2 micron ~ 10 microns scope.
The above only is preferred embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. a preparation method who has the substrate of cavity is characterized in that, comprises the steps:
Provide support substrate and device substrate, described support substrates is used for having groove in the surface of bonding;
Under vacuum environment, support substrates and device substrate are bonded together;
The attenuate device substrate is to predetermined thickness.
2. the preparation method who has the substrate of cavity according to claim 1 is characterized in that, the pressure limit of described vacuum environment is 10Pa ~ 0.3Pa.
3. the preparation method who has the substrate of cavity according to claim 1 is characterized in that, the surface coverage oxide layer of described support substrates.
4. the preparation method who has the substrate of cavity according to claim 3 is characterized in that, described oxide layer also covers the inwall of described groove.
5. the preparation method who has the substrate of cavity according to claim 1 is characterized in that, the material of described support substrates and device substrate is monocrystalline silicon.
6. the preparation method who has the substrate of cavity according to claim 1 is characterized in that, further comprises etch stop layer in the described device substrate.
7. the preparation method who has the substrate of cavity according to claim 1 is characterized in that, described device substrate has different resistivity with support substrates.
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| CN2013101753225A CN103241708A (en) | 2013-05-14 | 2013-05-14 | Preparation method of substrate with cavity |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103839776A (en) * | 2014-03-07 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN104925745A (en) * | 2015-04-28 | 2015-09-23 | 歌尔声学股份有限公司 | Cavity forming method and manufacturing method of sensor chip, chip and electronic equipment |
| CN106847739A (en) * | 2015-12-04 | 2017-06-13 | 上海新微技术研发中心有限公司 | Method for manufacturing silicon-on-insulator material |
| CN107304039A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic installation |
| CN107857232A (en) * | 2016-09-22 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof and electronic installation |
| CN108622851A (en) * | 2018-04-28 | 2018-10-09 | 中科芯集成电路股份有限公司 | A kind of preparation method of the substrate with cavity |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103839776A (en) * | 2014-03-07 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN103839776B (en) * | 2014-03-07 | 2016-11-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
| CN104925745A (en) * | 2015-04-28 | 2015-09-23 | 歌尔声学股份有限公司 | Cavity forming method and manufacturing method of sensor chip, chip and electronic equipment |
| CN106847739A (en) * | 2015-12-04 | 2017-06-13 | 上海新微技术研发中心有限公司 | Method for manufacturing silicon-on-insulator material |
| CN106847739B (en) * | 2015-12-04 | 2018-08-31 | 上海新微技术研发中心有限公司 | Method for manufacturing silicon-on-insulator material |
| CN107304039A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic installation |
| CN107857232A (en) * | 2016-09-22 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof and electronic installation |
| CN108622851A (en) * | 2018-04-28 | 2018-10-09 | 中科芯集成电路股份有限公司 | A kind of preparation method of the substrate with cavity |
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Application publication date: 20130814 |