CN103258778B - With the preparation method of the substrate of cavity - Google Patents
With the preparation method of the substrate of cavity Download PDFInfo
- Publication number
- CN103258778B CN103258778B CN201310175296.6A CN201310175296A CN103258778B CN 103258778 B CN103258778 B CN 103258778B CN 201310175296 A CN201310175296 A CN 201310175296A CN 103258778 B CN103258778 B CN 103258778B
- Authority
- CN
- China
- Prior art keywords
- substrate
- device substrate
- bonding
- support substrates
- preparation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a kind of preparation method of the substrate with cavity, comprise the steps: to provide support substrate and device substrate, described support substrates is for having groove in the surface of bonding; Support substrates and device substrate are bonded together; Device substrate edge after the center position grinding bonding of device substrate, to the overhanging portion of removal devices edges of substrate; Grind thinning device substrate to predetermined thickness.The invention has the advantages that; first edge overhanging portion was removed before grinding is thinning; prevent after being thinned to a certain thickness; the unsettled place, edge of device substrate is not owing to having the reinforcement protection effect of bonded interface; can be chipping because of the effect of cannot meeting with stresses, thus reduce the probability that broken limit occurs in the process of grinding.
Description
Technical field
The present invention relates to Semiconductor substrate and manufacture field, particularly relate to a kind of preparation method of the substrate with cavity.
Background technology
Bonding and thinning back side (BESOI) technology are the most ripe at present and business-like SOI technology.This technology is bonded together as support substrates and device substrate by the silicon chip after two panels oxidation, reinforce more than 2 hours at higher than the temperature of 1000 DEG C subsequently, then adopt the modes such as grinding, polishing device substrate to be thinned to thickness required for SOI device, namely obtain final bonding SOI wafer.BESOI technology has that technique is simple, low cost and other advantages, is therefore subject to the attention of industry.
With the SOI material (Cavity-SOI) of cavity as a kind of novel SOI material, compared with common SOI material, its supporter has outputed specific hole by photoetching and etching technics before bonding, and these holes form specific graphical distribution on surface.The development of MEMS technology, at pressure sensor, increasing application CavtiySOI material in the MEMS application such as gyroscope.In the process of preparation Cavity-SOI material, due to the existence of these holes, the contact area of bonding part on supporter is greatly reduced, and distinctive cavity structure, to directly affect the follow-up course of processing, device layer above hole is not owing to supporting, and top layer silicon thickness is thinner, more easily damaged by mechanical stress and produce damaged situation in mechanical grinding process.
Summary of the invention
Technical problem to be solved by this invention is, provides a kind of preparation method of the substrate with cavity, can reduce the fragment rate in preparation process.
In order to solve the problem, the invention provides a kind of preparation method of the substrate with cavity, comprise the steps: to provide support substrate and device substrate, described support substrates is for having groove in the surface of bonding; Support substrates and device substrate are bonded together; Device substrate edge after the center position grinding bonding of device substrate, to the overhanging portion of removal devices edges of substrate; Grind thinning device substrate to predetermined thickness.
Optionally, in described grinding steps, the removal amount scope at device substrate edge is 0.5mm ~ 2mm.
Optionally, described bonding steps carries out under vacuum conditions.
Optionally, the material of described support substrates and device substrate is monocrystalline silicon.
Optionally, etch stop layer is comprised further in described device substrate.
Optionally, described support substrates and device substrate have different resistivity.
The invention has the advantages that; first edge overhanging portion was removed before grinding is thinning; prevent after being thinned to a certain thickness; the unsettled place, edge of device substrate is not owing to having the reinforcement protection effect of bonded interface; can be chipping because of the effect of cannot meeting with stresses, thus reduce the probability that broken limit occurs in the process of grinding.
Accompanying drawing explanation
It is the implementation step schematic diagram of method described in the specific embodiment of the invention shown in accompanying drawing 1.
It is the process chart of said method shown in accompanying drawing 2A to accompanying drawing 2F.
Embodiment
Elaborate below in conjunction with the embodiment of accompanying drawing to the preparation method of a kind of substrate with cavity provided by the invention.
Be the implementation step schematic diagram of method described in this embodiment shown in accompanying drawing 1, comprise: step S101, provide support substrate and device substrate: step S102, in the surface that described support substrates is used for bonding, form groove; Step S103, form oxide layer on the surface of described support substrates, described oxide layer covers the inwall of described groove further; Step S110, is bonded together support substrates and device substrate; Step S120, the device substrate edge after the center position grinding bonding of substrate, to the overhanging portion of removal devices edges of substrate; Step S130, grinds thinning device substrate to predetermined thickness.
It is the process chart of said method shown in accompanying drawing 2A to accompanying drawing 2F.
Shown in accompanying drawing 2A, refer step S101, provides support substrate 200 and device substrate 210.In this embodiment, the material of support substrates 200 and device substrate 210 is monocrystalline silicon, and in other embodiment, the material of above-mentioned two substrates can be selected from the common semiconductor substrate materials of any one.Support substrates 200 and device substrate 210 can have different resistivity.
Shown in accompanying drawing 2B, refer step S102, in described support substrates 200 for forming groove 201 in the surface of bonding.This embodiment is illustrated with 4 grooves 201, in other embodiment, can comprise more or less groove 201 further.Form the method that groove can adopt photoetching and corrosion, described corrosion can be dry etching or wet etching.
Shown in accompanying drawing 2C, refer step S103, forms oxide layer 220 on the surface of described support substrates 200, and described oxide layer 220 covers the inwall of described groove 201 further.The method forming oxide layer 220 can be chemical vapor deposition method etc., and when being monocrystalline silicon for support substrates 200 material, oxide layer 220 also can be the silica adopting thermal oxidation technology to be formed.Above-mentioned two kinds of techniques can form oxide layer 220 at the inwall place of the surface of support substrates 200 and groove 201 simultaneously.Oxide layer 220 is formed in a groove if do not wish, also can be not shown by this processing step of oxide layer 220(of method removing groove 201 inwall of selective corrosion again).
After above-mentioned steps is implemented, in the surface of formation bonding, there is the support substrates 200 being formed cavity by groove 201.Oxide layer 220 is optional layers, can determine to add or omit according to subsequent device technique to the needs of substrat structure.
Shown in accompanying drawing 2D, refer step S110, is bonded together support substrates 200 and device substrate 210.Bonding preferably carries out under vacuum conditions, can selective annealing reinforce further after bonding completes.Bonding completes the cavity that rearward recess 201 changes confined space into.If bonding carries out under vacuum conditions, groove 201 inside after bonding also should be vacuum.
Shown in step 2E, refer step S120, device substrate 210 edge after the center position grinding bonding of device substrate 210, to the overhanging portion at removal devices substrate 210 edge.Because support substrates 200 and device substrate 210 all can adopt common commercial substrate usually, former capital has chamfering to exist.Therefore after bonding, the edge chamfer part of device substrate 210 can be unsettled outside oxide layer 220.Even if non-oxidation layer 220, because the edge that there is device substrate 210 of chamfering also cannot contact with support substrates 200 completely.When inside has cavity, device substrate 210 and support substrates 200 contact and insecure, inner exist the stress caused by cavity.If directly implement grinding to device substrate 210 in the case, after being thinned to a certain thickness, the unsettled place, edge of device substrate 210, can be chipping because of the effect of cannot meeting with stresses owing to not having the reinforcement protection effect of bonded interface.Therefore first this step by removing edge overhanging portion, the problem that broken limit occurs in the process of grinding can be prevented.The range scale removing edge overhanging portion can be such as 0.5mm ~ 2mm, and carries out consistency adjustment according to diameter wafer.
Shown in accompanying drawing 2F, refer step S130, grinds thinning device substrate 210 to predetermined thickness.On the basis implementing step S120, in this step, the probability on the broken limit of device substrate 210 is greatly diminished.Surface after grinding is coarse, can also implement glossing further and carry out Surface Machining process to it.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. with a preparation method for the substrate of cavity, it is characterized in that, comprise the steps:
Provide support substrate and device substrate, described support substrates is for having groove in the surface of bonding;
Support substrates and device substrate are bonded together;
Device substrate edge after the center position grinding bonding of device substrate, to the overhanging portion of removal devices edges of substrate;
Grind thinning device substrate to predetermined thickness; In described grinding steps, the removal amount scope at device substrate edge is 0.5mm ~ 2mm.
2. the preparation method of the substrate with cavity according to claim 1, is characterized in that, described bonding steps carries out under vacuum conditions.
3. the preparation method of the substrate with cavity according to claim 1, is characterized in that, the material of described support substrates and device substrate is monocrystalline silicon.
4. the preparation method of the substrate with cavity according to claim 1, is characterized in that, described support substrates and device substrate have different resistivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310175296.6A CN103258778B (en) | 2013-05-14 | 2013-05-14 | With the preparation method of the substrate of cavity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310175296.6A CN103258778B (en) | 2013-05-14 | 2013-05-14 | With the preparation method of the substrate of cavity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103258778A CN103258778A (en) | 2013-08-21 |
| CN103258778B true CN103258778B (en) | 2016-02-24 |
Family
ID=48962608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310175296.6A Active CN103258778B (en) | 2013-05-14 | 2013-05-14 | With the preparation method of the substrate of cavity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103258778B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103442324B (en) * | 2013-08-22 | 2017-08-18 | 上海华虹宏力半导体制造有限公司 | Backboard and its manufacture method |
| CN106847739B (en) * | 2015-12-04 | 2018-08-31 | 上海新微技术研发中心有限公司 | Method for manufacturing silicon-on-insulator material |
| CN107304039A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof and electronic installation |
| CN107857232A (en) * | 2016-09-22 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS and preparation method thereof and electronic installation |
| CN108622843A (en) * | 2017-03-22 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | MEMS microphone and forming method thereof |
| CN108622851A (en) * | 2018-04-28 | 2018-10-09 | 中科芯集成电路股份有限公司 | A kind of preparation method of the substrate with cavity |
| CN117241654A (en) * | 2023-11-14 | 2023-12-15 | 北京青禾晶元半导体科技有限责任公司 | Method for preparing composite piezoelectric substrate based on mechanical thinning technology |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1787168A (en) * | 2005-10-11 | 2006-06-14 | 中国电子科技集团公司第二十四研究所 | Method for mfg. silicon film on silicon base substrate with deep slot pattern |
| CN101599451A (en) * | 2009-07-10 | 2009-12-09 | 上海新傲科技股份有限公司 | The Semiconductor substrate that has insulating buried layer is carried out the method for edge chamfer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08107091A (en) * | 1994-09-30 | 1996-04-23 | Kyushu Komatsu Denshi Kk | Manufacture of soi substrate |
| WO2011003366A1 (en) * | 2009-07-10 | 2011-01-13 | 上海新傲科技股份有限公司 | Method for forming substrate with insulating buried layer |
-
2013
- 2013-05-14 CN CN201310175296.6A patent/CN103258778B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1787168A (en) * | 2005-10-11 | 2006-06-14 | 中国电子科技集团公司第二十四研究所 | Method for mfg. silicon film on silicon base substrate with deep slot pattern |
| CN101599451A (en) * | 2009-07-10 | 2009-12-09 | 上海新傲科技股份有限公司 | The Semiconductor substrate that has insulating buried layer is carried out the method for edge chamfer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103258778A (en) | 2013-08-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103258778B (en) | With the preparation method of the substrate of cavity | |
| CN103400797B (en) | With the preparation method of the Semiconductor substrate of cavity | |
| US8372728B2 (en) | Process for fabricating a multilayer structure with trimming using thermo-mechanical effects | |
| US8298916B2 (en) | Process for fabricating a multilayer structure with post-grinding trimming | |
| US8383489B2 (en) | SOI wafer and method for forming the same | |
| EP2402983B1 (en) | Method for manufacturing soi wafer | |
| CN103241708A (en) | Preparation method of substrate with cavity | |
| CN106158580B (en) | Wafer thinning method | |
| EP3109893B1 (en) | Composite substrate | |
| GB201222329D0 (en) | Substrates for semiconductor devices | |
| US8754532B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN103560106B (en) | Method for manufacturing semiconductor substrate with low warping degree | |
| CN101777513A (en) | Method for improving growth of gate oxide layer and manufacture method of shallow groove isolating process | |
| WO2015074479A1 (en) | Low-warpage semiconductor substrate and method of preparing same | |
| SG172762A1 (en) | A test method on the support substrate of a substrate of the "semiconductor on insulator" type | |
| WO2015074480A1 (en) | Method for preparing semiconductor substrate with smooth edges | |
| WO2016173268A1 (en) | Method for forming cavity of sensor chip, method for manufacturing sensor chip, chip and electronic device | |
| CN103531520A (en) | Forming method of shallow trench isolation and semiconductor structure | |
| CN102437047A (en) | Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method | |
| RU2645895C2 (en) | Method for manufacturing a composite structure | |
| CN103247568B (en) | With the manufacture method of the substrate of graphical insulating buried layer | |
| JP6256576B1 (en) | Epitaxial wafer and method for manufacturing the same | |
| US9233836B2 (en) | Semiconductor device including accelerometer devices | |
| WO2020145891A1 (en) | An ultra-thin integrated chip and manufacture of the same | |
| CN104716017A (en) | Processing method for wafer edge improvement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |