CN102768981A - Method for preparing substrate with insulating buried layer - Google Patents
Method for preparing substrate with insulating buried layer Download PDFInfo
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- CN102768981A CN102768981A CN2012102333240A CN201210233324A CN102768981A CN 102768981 A CN102768981 A CN 102768981A CN 2012102333240 A CN2012102333240 A CN 2012102333240A CN 201210233324 A CN201210233324 A CN 201210233324A CN 102768981 A CN102768981 A CN 102768981A
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Abstract
The invention provides a method for preparing a substrate with an insulating buried layer, comprising the following steps of providing a supporting substrate and a device substrate which are made of the same material; polishing the surface of the supporting substrate by using a single-side polishing process; forming an insulating layer on the polished surface of the supporting substrate and/or one surface of the device substrate; bonding the supporting substrate and the device substrate by regarding the insulating layer as an intermediate layer; grinding and thinning the device substrate; and polishing the grinded surface of the device substrate by using the single-side polishing process which uses the process parameters the same as those of the polishing process to polish the surface of the supporting substrate. The method provided by the invention has the advantages that the twice polishing processes use the same polishing conditions, so that the surface appearances of the polished surfaces of the device substrate and the supporting substrate are the same, and the surface appearance matching of the device substrate and the supporting substrate can ensure a device layer in uniform thickness.
Description
Technical field
The present invention relates to field of semiconductor materials, relate in particular to a kind of preparation method who has the insulating buried layer substrate.
Background technology
Compare with the body silicon device, silicon-on-insulator (SOI) device has advantages such as high speed, low driving voltage, high temperature resistant, low-power consumption and anti-irradiation, enjoys people's attention, is all obtaining development fast aspect material and the preparation of devices.The SOI material can be divided into two big types of thin film SOI (top layer silicon is usually less than 1 μ m) and thick film SOIs (top layer silicon is usually greater than 1 μ m) by the thickness of its top layer silicon thin layer.The application in thin film SOI market 95% concentrates on 8 inches and 12 inches, and wherein most users are the guide of most advanced and sophisticated microelectric technique, like IBM, AMD, Motorola, Intel, UMC, TSMC, OKI etc.Supplier is Japanese SHIN-ETSU HANTOTAI (SEH), French Soitec, Japanese SUMCO at present, and wherein preceding two families have supplied about product more than 90%.The main actuating force in thin film SOI market comes from a high speed, low-power consumption product, particularly microprocessor (CPU) are used.These products with high content of technology, added value is big, is the tap of whole integrated circuit.
Much the report to SOI all concentrates on above these breathtaking most advanced and sophisticated application, and in fact the early stage application of SOI concentrates on Aero-Space and military field, is extended to power and smart and MEMS now and uses.Particularly development is rapid at aspects such as automotive electronics, demonstration, wireless telecommunications.Because the control of power supply and conversion, automotive electronics and consumer power device aspect make that to the requirement of adverse circumstances, high temperature, big electric current, high power consumption aspect the strict demand aspect reliability has to adopt the SOI device.Adopt thick film SOI material in these fields more; Concentrate on 6 inches and 8 inches; Present user comprises U.S. Maxim, ADI, TI (USA), Japanese NEC, Toshiba, Panasonic, Denso, TI (Japan), FUJI, Omron etc., European Philips, X-Fab etc.The characteristics in this field are that the SOI device technology is relatively ripe, and technology content is relatively low, and the profit of device also reduces relatively, and is responsive to the price comparison of SOI material.In these SOI materials user the inside, very big application is mainly derived from the drive circuit in the various application: like the amplifier circuit that is applied to be mainly mobile phone acceptance section of Maxim; Panasonic, TI, FUJI, Toshiba, NEC etc. are mainly used in the scan drive circuit in the display driver circuit; The application of DENSO is mainly at automotive electronics, wireless radio frequency circuit etc.; The application of Toshiba even in the power control circuit of air-conditioning; Omron is mainly aspect transducer; ADI is also mainly at high temperature circuit, transducer etc.; The application of Phillips then mainly is the LDMOS in the power device, is used for consumer electronics such as automobile audio, audio frequency, audio frequency amplifier etc.; The Magnchip of Korea S (Hynix) then is used for display driver circuit that digital camera uses and as the PDP display driver circuit of LG production etc. for Kopin produces.
At present, the technology of preparing of SOI material mainly contains injection oxygen isolation technology (SIMOX), bonding and back side corrosion technology (BESOI) and the smart peeling technology (Smart-cut), epitaxial loayer transfer techniques (ELTRAN) etc. of deriving out.Wherein, Technology is simple because bonding and back side corrosion technology have, low cost and other advantages, therefore receives people's attention, though oxygen buried layer thickness is adjustable continuously; But through the way attenuate top layer silicon of grinding or corroding, the thickness evenness of top layer silicon is difficult to precisely controlled.Is on the basis of 1 ± 0.3 mu m bonded attenuate SOI material like P.B.Mumola etc. at top layer silicon thickness; Adopt the special way of computer controlled controlling partially plasma attenuate; Top layer silicon is thinned to 0.1 μ m; Evenness only can be controlled at ± 0.01 μ m, and this has also just limited bonding and wafer thinning SOI material in the application that the top layer silicon thickness evenness is required aspect high.And the SOI material that adopts the SIMOX technology to prepare; Though have excellent top layer silicon thickness evenness; But owing to receive the restriction of implantation dosage and energy, the oxygen buried layer maximum ga(u)ge is difficult to surpass 400nm, and SIMOX technology is to utilize high annealing; Promote oxygen to form continuous oxygen buried layer in silicon chip inner gathering nucleation, but the SiO that the pin hole that exists in the oxygen buried layer makes its insulation property form not as thermal oxidation
2, puncture voltage is only about 6MV/cm, these drawbacks limit the application of SIMOX material aspect thick buried regions (greater than 400nm).The Smart-cut technology develops on the basis of bonding techniques; And the thickness of its top layer silicon is determined by hydrionic injection energy; Its thickness is adjustable continuously; Therefore this technology can satisfy oxygen buried layer thickness and the inhomogeneity requirement of top layer silicon simultaneously, but should technology peel off device layer owing to adopt hydrogen ion to inject, so production cost is higher.The epitaxial loayer transfer techniques need be on porous silicon the epitaxy single-crystal silicon layer, defective control difficulty, the prematurity still of this technology, the report of not using.
Summary of the invention
Technical problem to be solved by this invention is, a kind of preparation method who has the insulating buried layer substrate is provided, the thickness of control device layer better, thus improve the thickness evenness and the yield of entire substrate.
In order to address the above problem, the invention provides a kind of preparation method who has the insulating buried layer substrate, comprise the steps: to provide support substrates and device substrate with same material; Adopt the surface of single-sided polishing technology polishing support substrates; Form insulating barrier at the surface of polished of support substrates and/or a surface of device substrate; With the insulating barrier is that the intermediate layer is bonded together support substrates and device substrate; Grind the attenuate device substrate; Adopt single-sided polishing technology polishing device substrate by lapped face, the technological parameter that is adopted is with to polish the support substrates surface identical.
Optional, before the single-sided polishing support substrates, also comprise the step of support substrates being implemented twin polishing; Between the step of step of grinding the attenuate device substrate and single-sided polishing device substrate, also further comprise the step of support substrates being implemented twin polishing; Said twice twin polishing step also adopts identical technological parameter.
Optional, in the bonding step and grind between the attenuate step, comprise that further the device substrate behind the para-linkage carries out the step of chamfered.
Optional, the material of said support substrates and device substrate is monocrystalline silicon.
Optional, the material of said insulating barrier is selected from any one in silica, silicon nitride and the silicon oxynitride.
The invention has the advantages that; Twice glossing adopts identical process conditions; So the device substrate surface after the polishing should have and the identical surface topography in support substrates surface; The device substrate surface cooperates with the pattern on support substrates surface like this, and the thickness that can guarantee device layer is uniform.Because the thickness of device layer has only several microns even thinner usually, therefore identical glossing is adopted with the support substrates surface in the device substrate surface, can significantly improve the thickness evenness of device layer.
Description of drawings
It shown in the accompanying drawing 1 the implementation step sketch map of the specific embodiment of the invention.
Accompanying drawing 2A is to the process chart that shown in the accompanying drawing 2F is this embodiment of invention.
Embodiment
Below in conjunction with accompanying drawing the embodiment that has the preparation method of insulating buried layer substrate provided by the invention is elaborated.
Be the implementation step sketch map of this embodiment shown in the accompanying drawing 1, comprise: step S10 provides support substrates and device substrate with same material; Step S11, the surface of adopting single-sided polishing technology polishing support substrates; Step S12 forms insulating barrier at the surface of polished of support substrates and/or a surface of device substrate; Step S13 is that the intermediate layer is bonded together support substrates and device substrate with the insulating barrier; Step S14 grinds the attenuate device substrate; Step S15, adopt single-sided polishing technology polishing device substrate by lapped face, the technological parameter that is adopted is with to polish the support substrates surface identical.
Accompanying drawing 2A is to shown in the accompanying drawing 2F being the process chart of this embodiment.
Shown in the accompanying drawing 2A, refer step S10 provides support substrates 200 and device substrate 210 with same material.Both materials can be any one the common semi-conducting materials that comprises monocrystalline substrate.
Shown in the accompanying drawing 2B, refer step S11, the surface of adopting single-sided polishing technology polishing support substrates 200.The purpose of this step is to reduce the total thickness deviation of support substrates 200.After the whole throwing of single-sided polishing, support substrates 200 has three kinds of possible thickness distribution: first kind is that the intermediate thin edge is thick, is similar to a kind of distribution in the bottom of a pan; Second kind is the thick middle thin edge, is similar to a kind of distribution of back-off pot; The third is flat distribution, and just support substrates 200 surfaces in polishing back are for flat, and this is a kind of very desirable distribution.Shown in this embodiment accompanying drawing 2B is first kind of state.As a rule, the thickness of mid portion should be no more than 0.5 μ m than thin edge, is generally about 0.2 μ m, and accompanying drawing 2B has for the sake of clarity done exaggeration and illustrated, and does not mean that actual substrate has so big thickness deviation after polishing.
Before step S11 implements, can also select support substrates 200 is implemented the step of twin polishing, with the total thickness deviation of further correction support substrates 200.
Shown in the accompanying drawing 2C, refer step S12 forms insulating barrier 220 at the surface of polished of support substrates 200 and/or a surface of device substrate 210.This embodiment is the surface of polished formation insulating barrier 220 in support substrates 200, and the technology of formation can be chemical vapour deposition (CVD) or thermal oxidation etc., and material can be silica, silicon nitride or silicon oxynitride.Because the speed of growth technique is uniformly throughout, so the surface topography of insulating barrier 220 has still been followed the surface topography of support substrates 200.
Shown in the accompanying drawing 2D, refer step S13 is that the intermediate layer is bonded together support substrates 200 and device substrate 210 with insulating barrier 220.This bonding can be that hydrophilic bonding can be a hydrophobic bonding also, is optimized for hydrophilic bonding.At this moment, can select the auxiliary hydrophilic bonding of plasma also can be common hydrophilic bonding.Because the evenness deviation on support substrates 200 polished surfaces is merely the scope less than 1 micron; And bonded interface itself has certain elasticity; So for the device substrate behind the bonding 210, we can think that its exposed surface is smooth, can not receive the influence of support substrates 200.
Behind bonding, can also select device substrate 210 is implemented chamfer angle technique, the parameter of chamfering is by user's decision of this substrate.
Shown in the accompanying drawing 2E, refer step S14 grinds attenuate device substrate 210.Milling apparatus is preferably the single face grinder; At first roughly grind quick attenuate; Grinding wheel speed is greater than 2000rpm, and correct grinding reduces to grind the damage that causes subsequently, and grinding wheel speed is greater than 2000rpm; Grind the target thickness that back substrate thickness should be slightly larger than the top layer device layer, think that junior scholar's glossing is reserved surplus.
Shown in the accompanying drawing 2F; Refer step S15; Adopt single-sided polishing technology polishing device substrate 210 by lapped face; Polishing support substrates 200 surfaces are identical among the technological parameter that is adopted and the step S11, comprise type, concentration and the consumption etc. that adopt identical ramming head pressure, rotary speed, polishing fluid.This step forms final devices layer 211 on the surface of insulating barrier 220.Because both adopt identical process conditions, so device substrate 210 surfaces after the polishing should have and the identical surface topography in support substrates 200 surfaces, promptly should be that the intermediate thin edge is thick, be similar to a kind of distribution in the bottom of a pan.Device substrate 210 surfaces cooperate with the pattern on support substrates 200 surfaces like this, and the thickness that can guarantee device layer 211 is uniform.Because the thickness of device layer 211 has only several microns even thinner usually, therefore identical glossing is adopted with support substrates 200 surfaces in device substrate 210 surfaces, can significantly improve the thickness evenness of device layer 211.
If before step S11 implements, selected to implement the step of twin polishing, then preferably before step S15 implements, also select substrate behind the para-linkage to implement the step of twin polishing, with the total thickness deviation of the substrate behind the further correction bonding.And twice twin polishing step also adopts identical technological parameter, to form the coupling of surface topography, improves the thickness evenness of device layer 211.
Next provide one embodiment of the present of invention.
Step 1: a slice support substrates is provided, the Si support substrates is handled monocrystalline substrate; With 8 cun substrates is example, 750 microns of substrate thickness, and the substrate total thickness deviation is less than 4 microns; Substrate target thickness is 650 microns, at first grinds this monocrystalline substrate of attenuate, and milling apparatus is preferably the single face grinder; At first roughly grind quick attenuate, grinding wheel speed is greater than 2000rpm, and correct grinding reduces to grind the damage that causes subsequently; Grinding wheel speed grinds back substrate thickness and more than 3 microns, is thinned to 665 microns greater than target thickness here greater than 2000rpm.
Step 2: the support substrates to after grinding is polished, and can be that twin polishing also can be a single-sided polishing, also can be two-sided+single-sided polishing, is two-sided+single-sided polishing here.At first twin polishing, whole polishing process was divided into for two steps, at first rough polishing, finishing polish subsequently, total polishing removal amount is no less than 2 microns in two throwing processes; Adopt single-sided polishing with accurate control silicon wafer thickness subsequently, whole polishing process is divided into rough polishing and two steps of finishing polish equally, and polishing removal amount is not more than 4 microns, and after revising, the substrate total thickness deviation is less than 1 micron.After the whole throwing of single-sided polishing, support substrates presents intermediate thin, and the distribution that the edge is thick is similar to a kind of distribution in the bottom of a pan, and intermediate epitaxial layers thickness should be generally 0.2 μ m than thin edge 0-0.5 μ m.
Step 3: to support substrates or device substrate, perhaps the two all being carried out insulating and handle, can be oxidation technology, can be PECVD or LPCVD deposition insulating layer, and dielectric can be that silicon dioxide also can be silicon nitride.Optimizing technology is the thermal oxidation technology of standard, and oxidizing condition can wet oxygen also can be dried oxygen, and oxidation technology depends on the oxidated layer thickness of needs, and temperature is 900-1400 ℃, and wet-oxygen oxidation, oxidated layer thickness need the thickness decision according to final SOI.
Step 4: support substrates after the oxidation and the device substrate bonding of delaying outward, this bonding can be that hydrophilic bonding can be a hydrophobic bonding also, is optimized for hydrophilic bonding.At this moment, can select the auxiliary hydrophilic bonding of plasma also can be common hydrophilic bonding.If using plasma is assisted hydrophilic bonding; At first adopt Ar or N2 or O2 ion pair surface to handle, the reinforcing of annealing subsequently, annealing temperature is 50-700 ℃; Be optimized for 300 ℃; Annealing time is 10 min to 10 hours, is optimized for 2.5 hours, and annealing atmosphere is oxygen, argon gas, nitrogen or its mist.If adopt traditional hydrophilic or hydrophobic bonding, reinforcing temperature is 800-1400 ℃, and annealing time is 0.5-10 hour, and annealing atmosphere is oxygen, argon gas, nitrogen or its mist.
Step 5: to carrying out chamfered, the chamfering width is determined by customer specifications to the substrate after reinforcing.Grinding the remaining silicon layer thickness of back edge is the 0-150 micron.Substrate after the chamfering in TMAH solution, corroding, is removed the remaining silicon layer in 100 microns edges.The way of optimizing is to adopt the way of spin etching, sprays the TMAH corrosive liquid, and in the corrosion process, substrate is to rotating, and rotating speed is 100-10000rpm, is optimized for 1000rpm, and the TMAH temperature optimization is 95 ℃.
Step 6: grind the attenuate device substrate; Milling apparatus is preferably the single face grinder, at first roughly grinds quick attenuate, and grinding wheel speed is greater than 2000rpm; Correct grinding reduces to grind the damage that causes subsequently; Grinding wheel speed is greater than 2000rpm, and more than 3 microns, be thinned to the excess silicon layer thickness here is 18 microns to grinding back substrate thickness greater than prepared SOI top material layer silicon target thickness.Also should to be similar to support substrates the same in the distribution of remaining silicon layer thickness behind the attenuate, presents the thick distribution in a kind of intermediate thin edge.
Step 7: the device substrate to after grinding is polished, and can be that twin polishing also can be a single-sided polishing, also can be two-sided+single-sided polishing, is optimized for two-sided+single-sided polishing here.At first twin polishing, whole polishing process was divided into for two steps, at first rough polishing, finishing polish subsequently, total polishing removal amount is no less than 2 microns in two throwing processes; Adopt single-sided polishing with accurate control silicon wafer thickness subsequently, whole polishing process is divided into rough polishing and two steps of finishing polish equally, and polishing removal amount is not more than 6 microns.In the single side polishing machine polishing process, adopt and identical before parameter setting, it is recessed to require its final thickness to be distributed as.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (6)
1. a preparation method who has the insulating buried layer substrate is characterized in that, comprises the steps:
Support substrates and device substrate with same material are provided;
Adopt the surface of single-sided polishing technology polishing support substrates;
Form insulating barrier at the surface of polished of support substrates and/or a surface of device substrate;
With the insulating barrier is that the intermediate layer is bonded together support substrates and device substrate;
Grind the attenuate device substrate;
Adopt single-sided polishing technology polishing device substrate by lapped face, the technological parameter that is adopted is with to polish the support substrates surface identical.
2. method according to claim 1 is characterized in that, before the single-sided polishing support substrates, also comprises the step of support substrates being implemented twin polishing; Between the step of step of grinding the attenuate device substrate and single-sided polishing device substrate, also further comprise the step of support substrates being implemented twin polishing.
3. method according to claim 2 is characterized in that, said twice twin polishing step also adopts identical technological parameter.
4. method according to claim 1 is characterized in that, in the bonding step and grind between the attenuate step, comprises that further the device substrate behind the para-linkage carries out the step of chamfered.
5. method according to claim 1 is characterized in that the material of said support substrates and device substrate is monocrystalline silicon.
6. method according to claim 1 is characterized in that the material of said insulating barrier is selected from any one in silica, silicon nitride and the silicon oxynitride.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983074A (en) * | 2012-11-30 | 2013-03-20 | 上海新傲科技股份有限公司 | Method for thinning device layer and substrate preparation method |
| WO2015074480A1 (en) * | 2013-11-22 | 2015-05-28 | 上海新傲科技股份有限公司 | Method for preparing semiconductor substrate with smooth edges |
| CN106847846A (en) * | 2016-12-23 | 2017-06-13 | 江苏正桥影像科技股份有限公司 | A kind of grinding method of ultra-thin image sensor wafer |
| CN110010458A (en) * | 2019-04-01 | 2019-07-12 | 徐州鑫晶半导体科技有限公司 | Control the method and semiconductor wafer of semiconductor crystal wafer surface topography |
| CN113601376A (en) * | 2021-08-10 | 2021-11-05 | 山西烁科晶体有限公司 | Method for measuring single-side polishing rate in silicon carbide double-side polishing |
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| US6090688A (en) * | 1996-11-15 | 2000-07-18 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating an SOI substrate |
| CN101609800A (en) * | 2009-06-19 | 2009-12-23 | 上海新傲科技股份有限公司 | A kind of method for preparing the crystallographic orientation semiconductor substrate |
| CN101901753A (en) * | 2010-06-25 | 2010-12-01 | 上海新傲科技股份有限公司 | Method for preparing thick-film material with insulating embedded layer |
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2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6090688A (en) * | 1996-11-15 | 2000-07-18 | Komatsu Electronic Metals Co., Ltd. | Method for fabricating an SOI substrate |
| CN101609800A (en) * | 2009-06-19 | 2009-12-23 | 上海新傲科技股份有限公司 | A kind of method for preparing the crystallographic orientation semiconductor substrate |
| CN101901753A (en) * | 2010-06-25 | 2010-12-01 | 上海新傲科技股份有限公司 | Method for preparing thick-film material with insulating embedded layer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983074A (en) * | 2012-11-30 | 2013-03-20 | 上海新傲科技股份有限公司 | Method for thinning device layer and substrate preparation method |
| CN102983074B (en) * | 2012-11-30 | 2015-10-14 | 上海新傲科技股份有限公司 | The method of thinning device layer and the preparation method of substrate |
| WO2015074480A1 (en) * | 2013-11-22 | 2015-05-28 | 上海新傲科技股份有限公司 | Method for preparing semiconductor substrate with smooth edges |
| CN106847846A (en) * | 2016-12-23 | 2017-06-13 | 江苏正桥影像科技股份有限公司 | A kind of grinding method of ultra-thin image sensor wafer |
| CN110010458A (en) * | 2019-04-01 | 2019-07-12 | 徐州鑫晶半导体科技有限公司 | Control the method and semiconductor wafer of semiconductor crystal wafer surface topography |
| CN113601376A (en) * | 2021-08-10 | 2021-11-05 | 山西烁科晶体有限公司 | Method for measuring single-side polishing rate in silicon carbide double-side polishing |
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