KR100529633B1 - A semiconductor device using epitaxial silicon, and a manufacturing method thereof - Google Patents

Abstract

The present invention relates to a silicon-on-insulator (SOI) semiconductor device formed without defects using epitaxial silicon growth and planarization techniques, and a method of manufacturing the same. A method of manufacturing a semiconductor device using epitaxial silicon according to the present invention includes the steps of: i) forming an insulating layer on a silicon wafer surface and selectively removing the insulating layer to expose a silicon wafer surface in a field region; Ii) growing a silicon epitaxial layer on the silicon wafer surface of the field region; Iii) overgrowth the silicon epitaxial layer to completely cover the insulating layer; Iii) planarizing the overgrown silicon epitaxial layer; Iii) selectively removing said silicon epitaxial layer to expose a silicon wafer surface in the field region; Iii) filling and planarizing the field region with an insulating material; And iii) forming an element in an active region between the field regions. According to the present invention, a semiconductor device can be manufactured in a consistent process on SOI without defects caused by ion implantation and void defects occurring at the time of bonding in the existing SIMOX technology or wafer bonding technology.

Description

A semiconductor device using epitaxial silicon, and a manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using epitaxial silicon and a method of manufacturing the same. More specifically, a silicon-on-insulator (SOI) semiconductor device and a method of manufacturing the same, which are formed without defects using epitaxial silicon growth and planarization techniques. It is about.

As semiconductor devices become more integrated, there is an increasing demand for technologies that can reduce parasitic capacitance, which affects device performance and interconnect latency, and improve radiation immunity. have. As a result, next-generation silicon devices smaller than 0.1 μm are typically formed on silicon-on-insulators (SOIs) due to 1) faster speeds, 2) lower power consumption, and 3) ease of additional scaling than simple silicon wafers. have.

Unlike conventional wafers, the SOI refers to a wafer in which two wafers are bonded to each other by an oxide film. An SOI is an insulating film inserted into a silicon wafer. An SOI is an insulating film on a silicon wafer substrate, and a single crystal silicon film on which an integrated circuit is manufactured. Say that there is. The SOI is used in TFT-LCD CMOS, Bipolar CCD (Charge Coupled Device Detectors), HDTV, Photo-detector, etc., which are applications using high temperature, low power consumption, and high speed characteristics.

There are several methods for realizing SOI structures on silicon wafers, among others, wafer bonded and SIMOX (Separation by IMplanted OXygen) technologies that are currently commercially available in the semiconductor industry.

Hereinafter, the SOI technology according to the related art will be described in detail with reference to FIGS. 1 and 2A to 2D.

1 is a diagram illustrating an SOI manufactured by a wafer bonding method according to the related art.

The wafer bonding technique refers to a technique of bonding two prime wafers 11a and 11b and only etching back the back side or separating by a predetermined cleaving technique.

The wafer bonding method is an oxide film (12a, 12b) and then van der Waals forces (vander Walls force) in the wafer two sheets (11a, 11b) formed a see the SiO ₂ film (12a, 12b) facing each other on the silicon wafer surface to After the two wafers 11a and 11b are bonded together, the surface of the part where the device is manufactured is planarized, leaving only the required thickness of silicon. This wafer bonding method has a problem that voids are very likely between two wafers to be bonded. Here, reference numeral A denotes a void occurring between two wafers.

Meanwhile, FIGS. 2A to 2D are diagrams illustrating a process of manufacturing an SOI using the SIMOX method according to the prior art, respectively.

The SIMOX technology is a technique of injecting oxygen into a silicon wafer and performing high temperature heat treatment. Specifically, such a SIMOX technology, when ion implanted into the silicon wafer 21a with a depth of about 0.5 μm using O ²⁺ of about 2E ¹⁸ / cm ₂ (see FIG. 2A), the silicon wafer 21a An ion implantation layer 22a is formed in the inside (see FIG. 2B), and then 1100 ?? When annealed with nitrogen (N ² ) at the high temperature (see FIG. 2C), a SiO ₂ layer (SiO ₂ buried layer) 22b is formed below the surface of the silicon 21b (see FIG. 2D), and then again, silicon epi It is a method of growing a tactile layer about 0.5 micrometer. The SIMOX technology has a problem in that defects are more likely to occur at the interface between the lower SiO ₂ and the upper silicon layer (see B and B ′) due to the high impurity and high energy ion implantation.

That is, conventional SOI wafers by wafer bonding or SIMOX have a problem in that defects due to ion implantation occurring in the manufacturing process of semiconductor devices and void defects occurring during bonding are generated.

An object of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device on an SOI without defects using epitaxial silicon growth and planarization techniques.

As a means for achieving the above object, a method of manufacturing a semiconductor device using epitaxial silicon according to the present invention,

Iii) forming an insulating layer on the silicon wafer surface and selectively removing the insulating layer to expose the silicon wafer surface in the field region;

Ii) growing a silicon epitaxial layer on the silicon wafer surface of the field region;

Iii) overgrowth the silicon epitaxial layer to completely cover the insulating layer;

Iii) planarizing the overgrown silicon epitaxial layer;

Iii) selectively removing said silicon epitaxial layer to expose a silicon wafer surface in the field region;

Iii) filling and planarizing the field region with an insulating material; And

Iii) forming an element in an active region between the field regions

It includes.

Here, the insulating layer is preferably an oxide film (SiO ₂ ) or a nitride film (Si ₃ N ₄ ).

In the step ii), the selective silicon epitaxial layer is grown using the exposed silicon wafer surface as a seed.

The method may further include sequentially laminating a pad oxide film and a nitride film on the silicon epitaxial layer between the steps iii) and iii), and in this case, the pad oxide film between the steps iii) and iii). And removing the nitride film.

In addition, a chemical mechanical polishing (CMP) method may be used to planarize the silicon epitaxial layer and the insulating material.

On the other hand, as another means for achieving the above object, a semiconductor device using epitaxial silicon according to the present invention,

Silicon wafers;

An insulating layer formed on a surface of the silicon wafer in a region other than a field region;

A silicon epitaxial layer formed over the insulating layer;

A separation insulating layer filled in the field region and performing element isolation; And

Transistors provided in an active region between the field regions;

It includes.

According to the present invention, a semiconductor device can be processed in a consistent process on an SOI without defects caused by ion implantation and void defects occurring at the time of bonding in the conventional SIMOX technology or wafer bonding technology.

Hereinafter, a semiconductor device using epitaxial silicon and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3J are diagrams illustrating an SOI manufacturing process using epitaxial silicon, respectively, according to an exemplary embodiment of the present invention.

First, an SiO ₂ or Si ₃ N ₄ insulating layer 33 is grown on the surface of a semiconductor substrate or silicon wafer 31 (see FIG. 3A). Then, using the photo and etching process, the insulating layer 33 of the portion where the field is to be formed is etched to expose the silicon 31 of the field portion (see FIG. 3B). Here, reference numeral C denotes the silicon wafer 31 exposed by etching.

Next, a silicon epitaxial layer 35 is selectively grown only on the portion C where the silicon is exposed (see FIG. 3C). That is, the selective silicon epitaxial layer 35 is grown using the exposed silicon surface as a seed.

For reference, an epitaxial wafer refers to a wafer in which a silicon layer is vapor-grown on a surface by heating polished wafers in a high frequency or infrared ray in an EPI furnace, where the resistivity is different from that of the silicon wafer. Here, the polished wafer refers to a wafer whose surface has a mirror surface through a polishing process in etched wafers.

Specifically, the epitaxial wafer (or epitaxial wafer) refers to a wafer in which another single crystal layer is grown on a surface of a conventional silicon wafer, and has fewer surface defects than the conventional silicon wafer, and can control the concentration or type of impurities. Will have. Such epitaxial process is the most basic process and the core process in semiconductor manufacturing at present, and is used in silicon wafer manufacturing to enable high quality and high value. In addition, the epitaxial layer may be grown in various ways, and among them, chemical vapor deposition (CVD) is most commonly used.

Next, the silicon epitaxial layer 35 is sufficiently overgrowth 37a so that the silicon epitaxial layer 35 is grown by the selective epitaxial layer so as to completely cover the insulating layer 33. 3d). In this case, when the silicon epitaxial layer 37a grows thicker than the insulating layer 33, the silicon epitaxial layer 37a may grow epitaxially not only in the upper side but also in the lateral direction, and thus may be grown on the surface of the insulating layer 33.

Next, the silicon epitaxial layer 37a is planarized using a CMP process to leave only the silicon epitaxial thickness 37b necessary for manufacturing a semiconductor device (see FIG. 3E).

Next, a pad oxide film 39 and an isolation nitride 41 are sequentially stacked (see FIG. 3F). The growth of the pad oxide layer 39 and the isolation nitride layer 41 is to apply a conventional shallow trench isolation (STI) process.

Next, the silicon of the portion D where the field is to be formed is etched again using a photo and etching process (see FIG. 3G). At this time, it is etched vertically by the depth of the lower insulating layer 33.

Next, the field portion D is filled with an insulating material 43a and densified (see FIG. 3H).

Next, the isolation insulating film 43b is formed by planarizing the insulating material 43a using the CMP method again (see FIG. 3I).

Next, the separation nitride film 41 and the pad oxide film 39 are removed by an etching process (see FIG. 3J).

3A to 3J, the SOI using epitaxial silicon is completed, and the subsequent process is the same as that of a subsequent semiconductor device.

FIG. 4 illustrates a semiconductor device fabricated on an SOI using epitaxial silicon in accordance with an embodiment of the present invention, typical of the active region 45 on the SOI fabricated by the process of FIGS. 3A-3J described above. An example in which semiconductor devices such as MOS are manufactured using a subsequent step is shown.

While the invention has been described above, these examples are intended to illustrate rather than limit this invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the embodiments are possible without departing from the technical details of the invention. Therefore, the scope of protection of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

According to the present invention, it is possible to manufacture a semiconductor device on an SOI without defects, and to proceed to a consistent process from SOI to semiconductor device manufacturing.

1 is a view showing a SOI manufactured by a wafer bonded method according to the prior art.

2A to 2D are diagrams illustrating a process of manufacturing an SOI in the SIMOX method according to the prior art, respectively.

3A to 3J are diagrams illustrating an SOI manufacturing process using epitaxial silicon, respectively, according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a semiconductor device manufactured on SOI using epitaxial silicon according to an embodiment of the present invention.

Claims (7)

Iii) forming an insulating layer on the silicon wafer surface and selectively removing the insulating layer to expose the silicon wafer surface in the field region; Ii) growing a silicon epitaxial layer on the silicon wafer surface of the field region; Iii) overgrowth the silicon epitaxial layer to completely cover the insulating layer; Iii) planarizing the overgrown silicon epitaxial layer; Iii) selectively removing said silicon epitaxial layer to expose a silicon wafer surface in the field region; Iii) filling and planarizing the field region with an insulating material; And Iii) forming an element in an active region between the field regions Method of manufacturing a semiconductor device using epitaxial silicon comprising a. The method of claim 1, And the insulating layer is an oxide film (SiO ₂ ) or a nitride film (Si ₃ N ₄ ). According to claim 1, wherein step ii), A method of manufacturing a semiconductor device using epitaxial silicon, characterized in that to grow a selective silicon epitaxial layer using the exposed silicon wafer surface as a seed (seed). The method of claim 1, further comprising sequentially depositing a pad oxide film and a nitride film on the silicon epitaxial layer between the steps iii) and iii). 5. The method of claim 4, further comprising removing the pad oxide film and the nitride film between the steps iii) and iii). 6. The method of claim 1, The planarization of the silicon epitaxial layer and the insulating material using a chemical mechanical polishing (CMP) method of manufacturing a semiconductor device using epitaxial silicon. Silicon wafers; An insulating layer formed on a surface of the silicon wafer in a region other than a field region; A silicon epitaxial layer formed over the insulating layer; A separation insulating layer filled in the field region and performing element isolation; And Transistors provided in an active region between the field regions; Semiconductor device using a silicon epitaxial comprising a.