KR20050043137A - A semiconductor device using epitaxial silicon, and a manufacturing method thereof - Google Patents
A semiconductor device using epitaxial silicon, and a manufacturing method thereof Download PDFInfo
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- KR20050043137A KR20050043137A KR1020030077925A KR20030077925A KR20050043137A KR 20050043137 A KR20050043137 A KR 20050043137A KR 1020030077925 A KR1020030077925 A KR 1020030077925A KR 20030077925 A KR20030077925 A KR 20030077925A KR 20050043137 A KR20050043137 A KR 20050043137A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 87
- 239000010703 silicon Substances 0.000 title claims abstract description 87
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000011810 insulating material Substances 0.000 claims abstract description 7
- 208000012868 Overgrowth Diseases 0.000 claims abstract description 4
- 235000012431 wafers Nutrition 0.000 claims description 54
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 239000011800 void material Substances 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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Abstract
본 발명은 에피택셜 실리콘 성장 및 평탄화 기술을 이용하여 결함 없이 형성되는 SOI(Silicon-On-Insulator) 반도체 소자 및 그 제조 방법에 관한 것이다. 본 발명에 따른 에피택셜 실리콘을 이용한 반도체 소자의 제조 방법은, ⅰ) 실리콘 웨이퍼 표면에 절연층을 형성하고, 상기 절연층을 선택적으로 제거하여 필드 영역의 실리콘 웨이퍼 표면을 노출시키는 단계; ⅱ) 상기 필드 영역의 실리콘 웨이퍼 표면에 실리콘 에피택셜층을 성장시키는 단계; ⅲ) 상기 절연층을 완전히 덮도록 상기 실리콘 에피택셜층을 과도 성장(overgrowth)시키는 단계; ⅳ) 상기 과도 성장된 실리콘 에피택셜층을 평탄화하는 단계; ⅴ) 상기 실리콘 에피택셜층을 선택적으로 제거하여 필드 영역의 실리콘 웨이퍼 표면을 노출시키는 단계; ⅵ) 상기 필드 영역을 절연 물질로 충진하고 평탄화하는 단계; 및 ⅶ) 상기 필드 영역 사이의 액티브 영역에 소자를 형성하는 단계를 포함한다. 본 발명에 따르면, 기존의 SIMOX 기술이나 웨이퍼 본딩 기술에서 발생할 수 있는 이온주입에 의한 결함과 접합 시에 발생하는 보이드 결함 없이도 SOI 상에서 반도체 소자를 일관된 공정으로 제조할 수 있다.The present invention relates to a silicon-on-insulator (SOI) semiconductor device formed without defects using epitaxial silicon growth and planarization techniques, and a method of manufacturing the same. A method of manufacturing a semiconductor device using epitaxial silicon according to the present invention includes the steps of: i) forming an insulating layer on a silicon wafer surface and selectively removing the insulating layer to expose a silicon wafer surface in a field region; Ii) growing a silicon epitaxial layer on the silicon wafer surface of the field region; Iii) overgrowth the silicon epitaxial layer to completely cover the insulating layer; Iii) planarizing the overgrown silicon epitaxial layer; Iii) selectively removing said silicon epitaxial layer to expose a silicon wafer surface in the field region; Iii) filling and planarizing the field region with an insulating material; And iii) forming an element in an active region between the field regions. According to the present invention, a semiconductor device can be manufactured in a consistent process on SOI without defects caused by ion implantation and void defects occurring at the time of bonding in the existing SIMOX technology or wafer bonding technology.
Description
본 발명은 에피택셜 실리콘을 이용한 반도체 소자 및 그 제조 방법에 관한 것으로, 보다 구체적으로, 에피택셜 실리콘 성장 및 평탄화 기술을 이용하여 결함 없이 형성되는 SOI(Silicon-On-Insulator) 반도체 소자 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using epitaxial silicon and a method of manufacturing the same. More specifically, a silicon-on-insulator (SOI) semiconductor device and a method of manufacturing the same, which are formed without defects using epitaxial silicon growth and planarization techniques. It is about.
반도체 소자가 고집적화됨에 따라, 소자 성능과 인터커넥션(interconnection) 지연에 영향을 미치는 기생 정전용량(parasitic capacitance)을 감소시킬 수 있고, 방사(radiation) 내성을 향상시킬 수 있는 기술에 대한 요구가 증대되고 있다. 따라서 0.1㎛ 이하의 차세대 실리콘 디바이스는 단순한 실리콘 웨이퍼보다 일반적으로 1) 속도 향상, 2) 낮은 전력 소비, 및 3) 추가적인 축적(Scaling)의 용이성으로 인해 SOI(Silicon-On- Insulator) 상에 형성되고 있다.As semiconductor devices become more integrated, there is an increasing demand for technologies that can reduce parasitic capacitance, which affects device performance and interconnect latency, and improve radiation immunity. have. As a result, next-generation silicon devices smaller than 0.1 μm are typically formed on silicon-on-insulators (SOIs) due to 1) faster speeds, 2) lower power consumption, and 3) ease of additional scaling than simple silicon wafers. have.
이러한 SOI는 기존의 웨이퍼와는 달리 산화막으로 2장의 웨이퍼를 접합시킨 웨이퍼를 말하며, 실리콘 웨이퍼 속에 절연막을 삽입시킨 개념으로서, 실리콘 웨이퍼 기판 위에 절연막이 있고, 다시 그 위에 집적 회로가 제작될 단결정 실리콘 필름이 있는 상태를 말한다. 이러한 SOI는 고온 특성, 저소비 전력 특성 및 고속 특성을 이용한 응용 분야인 TFT-LCD CMOS, Bipolar CCD(Charge Coupled device Detectors), HDTV, 광검출기(Photo-detector) 등에 사용되고 있다.Unlike conventional wafers, the SOI refers to a wafer in which two wafers are bonded to each other by an oxide film. An SOI is an insulating film inserted into a silicon wafer. An SOI is an insulating film on a silicon wafer substrate, and a single crystal silicon film on which an integrated circuit is manufactured. Say that there is. The SOI is used in TFT-LCD CMOS, Bipolar CCD (Charge Coupled Device Detectors), HDTV, Photo-detector, etc., which are applications using high temperature, low power consumption, and high speed characteristics.
이러한, 실리콘 웨이퍼에 SOI 구조를 실현하기 위한 몇 가지 방법이 있으나, 그 중에서도 웨이퍼 본딩(Wafer bonded) 기술과 SIMOX(Separation by IMplanted OXygen) 기술은 반도체 산업에서 현재 상업적으로 이용 가능한 기술들이다.There are several methods for realizing SOI structures on silicon wafers, among others, wafer bonded and SIMOX (Separation by IMplanted OXygen) technologies that are currently commercially available in the semiconductor industry.
이하, 도 1 및 도 2a 내지 도 2d를 참조하여, 종래 기술에 따른 SOI 기술을 구체적으로 설명한다.Hereinafter, the SOI technology according to the related art will be described in detail with reference to FIGS. 1 and 2A to 2D.
도 1은 종래의 기술에 따른 웨이퍼 본딩 방식으로 제조된 SOI를 나타내는 도면이다.1 is a diagram illustrating an SOI manufactured by a wafer bonding method according to the related art.
상기 웨이퍼 본딩 기술은 두 장의 프라임 웨이퍼(prime wafer)(11a, 11b)를 본딩하고, 단지 뒷면을 에치백(etchback)하거나 또는 소정의 분리(cleaving) 기술에 의해 분리하는 기술을 말한다.The wafer bonding technique refers to a technique of bonding two prime wafers 11a and 11b and only etching back the back side or separating by a predetermined cleaving technique.
상기 웨이퍼 본딩 방법은 실리콘 웨이퍼 표면에 산화막(12a, 12b)이 형성된 웨이퍼 두장(11a, 11b)을 SiO2 막(12a, 12b)이 서로 마주보게 한 다음에 반데르발스 힘(vander Walls force)을 이용하여 상기 두장의 웨이퍼(11a, 11b)를 붙인 후, 소자가 제조되는 부분의 표면을 필요한 실리콘 두께만 남기고 평탄화하는 방법이다. 이러한 웨이퍼 본딩 방법은 접합되는 두 웨이퍼 사이에 보이드(void)가 가능성이 매우 높다는 문제점이 있다. 여기서, 도면부호 A는 두 장의 웨이퍼 사이에서 발생하는 보이드를 나타낸다.The wafer bonding method is an oxide film (12a, 12b) and then van der Waals forces (vander Walls force) in the wafer two sheets (11a, 11b) formed a see the SiO 2 film (12a, 12b) facing each other on the silicon wafer surface to After the two wafers 11a and 11b are bonded together, the surface of the part where the device is manufactured is planarized, leaving only the required thickness of silicon. This wafer bonding method has a problem that voids are very likely between two wafers to be bonded. Here, reference numeral A denotes a void occurring between two wafers.
한편, 도 2a 내지 도 2d는 각각 종래 기술에 따른 SIMOX 방식으로 SOI를 제조하는 공정을 나타내는 도면들이다.Meanwhile, FIGS. 2A to 2D are diagrams illustrating a process of manufacturing an SOI using the SIMOX method according to the prior art, respectively.
상기 SIMOX 기술은 실리콘 웨이퍼에 산소를 주입하고, 고온 열처리를 하는 기술이다. 구체적으로, 이러한 SIMOX 기술은 2E18/㎠ 정도의 O2 +를 불순물(dose)로 하여 실리콘 웨이퍼(21a)에 약 0.5㎛의 깊이로 이온 주입하면(도 2a 참조), 상기 실리콘 웨이퍼(21a) 내에 이온 주입층(22a)이 형성되며(도 2b 참조), 다음에 1100?? 이상의 고온에서 질소(N2)로 어닐링하면(도 2c 참조), 실리콘(21b) 표면 아래에 SiO2 층(SiO2 매립층)(22b)이 형성되게 되며(도 2d 참조), 이후, 다시 실리콘 에피택셜층을 약 0.5㎛ 정도 성장시키는 방법이다. 이러한 SIMOX 기술은 고불순물, 고에너지 이온주입에 따른 영향으로 하부 SiO2와 상부 실리콘층 계면(도면부호 B 및 B' 참조)에 결함이 발생할 가능성이 높다는 문제점이 있다.The SIMOX technology is a technique of injecting oxygen into a silicon wafer and performing high temperature heat treatment. Specifically, such a SIMOX technology, when ion implanted into the silicon wafer 21a with a depth of about 0.5 μm using O 2+ of about 2E 18 / cm 2 (see FIG. 2A), the silicon wafer 21a An ion implantation layer 22a is formed in the inside (see FIG. 2B), and then 1100 ?? When annealed with nitrogen (N 2 ) at the high temperature (see FIG. 2C), a SiO 2 layer (SiO 2 buried layer) 22b is formed below the surface of the silicon 21b (see FIG. 2D), and then again, silicon epi It is a method of growing a tactile layer about 0.5 micrometer. The SIMOX technology has a problem in that defects are more likely to occur at the interface between the lower SiO 2 and the upper silicon layer (see B and B ′) due to the high impurity and high energy ion implantation.
즉, 기존의 웨이퍼 본딩이나 SIMOX와 같은 방법에 의한 SOI 웨이퍼는 반도체 소자의 제조 과정에서 발생하는 이온주입(implantation)에 의한 결함과 접합 시에 발생하는 보이드 결함 등이 발생하게 된다는 문제점이 있다.That is, conventional SOI wafers by wafer bonding or SIMOX have a problem in that defects due to ion implantation occurring in the manufacturing process of semiconductor devices and void defects occurring during bonding are generated.
상기 문제점을 해결하기 위한 본 발명의 목적은 에피택셜 실리콘 성장 및 평탄화 기술을 이용하여 결함 없이 SOI 상에 반도체 소자를 제조하는 방법을 제공하기 위한 것이다.An object of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device on an SOI without defects using epitaxial silicon growth and planarization techniques.
상기 목적을 달성하기 위한 수단으로서, 본 발명에 따른 에피택셜 실리콘을 이용한 반도체 소자의 제조 방법은,As a means for achieving the above object, a method of manufacturing a semiconductor device using epitaxial silicon according to the present invention,
ⅰ) 실리콘 웨이퍼 표면에 절연층을 형성하고, 상기 절연층을 선택적으로 제거하여 필드 영역의 실리콘 웨이퍼 표면을 노출시키는 단계;Iii) forming an insulating layer on the silicon wafer surface and selectively removing the insulating layer to expose the silicon wafer surface in the field region;
ⅱ) 상기 필드 영역의 실리콘 웨이퍼 표면에 실리콘 에피택셜층을 성장시키는 단계;Ii) growing a silicon epitaxial layer on the silicon wafer surface of the field region;
ⅲ) 상기 절연층을 완전히 덮도록 상기 실리콘 에피택셜층을 과도 성장(overgrowth)시키는 단계;Iii) overgrowth the silicon epitaxial layer to completely cover the insulating layer;
ⅳ) 상기 과도 성장된 실리콘 에피택셜층을 평탄화하는 단계;Iii) planarizing the overgrown silicon epitaxial layer;
ⅴ) 상기 실리콘 에피택셜층을 선택적으로 제거하여 필드 영역의 실리콘 웨이퍼 표면을 노출시키는 단계; Iii) selectively removing said silicon epitaxial layer to expose a silicon wafer surface in the field region;
ⅵ) 상기 필드 영역을 절연 물질로 충진하고 평탄화하는 단계; 및Iii) filling and planarizing the field region with an insulating material; And
ⅶ) 상기 필드 영역 사이의 액티브 영역에 소자를 형성하는 단계Iii) forming an element in an active region between the field regions
를 포함한다.It includes.
여기서, 상기 절연층은 산화막(SiO2) 또는 질화막(Si3N4) 인 것이 바람직하다.Here, the insulating layer is preferably an oxide film (SiO 2 ) or a nitride film (Si 3 N 4 ).
여기서, 상기 ⅱ) 단계는, 상기 노출된 실리콘 웨이퍼 표면을 씨드(seed)로 하여 선택적 실리콘 에피택셜층을 성장시키는 것을 특징으로 한다.In the step ii), the selective silicon epitaxial layer is grown using the exposed silicon wafer surface as a seed.
여기서, 상기 ⅳ) 단계와 ⅴ) 단계 사이에는 상기 실리콘 에피택셜층 위에 패드 산화막 및 질화막을 순차적으로 적층하는 단계를 더욱 포함할 수 있고, 이 경우 상기 ⅵ) 단계와 ⅶ) 단계 사이에는 상기 패드 산화막 및 질화막을 제거하는 단계를 더욱 포함할 수 있다.The method may further include sequentially laminating a pad oxide film and a nitride film on the silicon epitaxial layer between the steps iii) and iii), and in this case, the pad oxide film between the steps iii) and iii). And removing the nitride film.
그리고, 상기 실리콘 에피택셜층 및 절연 물질의 평탄화에는 화학 기계적 연마(CMP) 방식을 이용할 수 있다.In addition, a chemical mechanical polishing (CMP) method may be used to planarize the silicon epitaxial layer and the insulating material.
한편, 상기 목적을 달성하기 위한 다른 수단으로서, 본 발명에 따른 에피택셜 실리콘을 이용한 반도체 소자는, On the other hand, as another means for achieving the above object, a semiconductor device using epitaxial silicon according to the present invention,
실리콘 웨이퍼;Silicon wafers;
필드 영역을 제외한 영역의 상기 실리콘 웨이퍼 표면에 형성되는 절연층;An insulating layer formed on a surface of the silicon wafer in a region other than a field region;
상기 절연층 위에 형성되는 실리콘 에피택셜층;A silicon epitaxial layer formed over the insulating layer;
상기 필드 영역에 충진되며, 소자 분리를 행하는 분리 절연층 ; 및A separation insulating layer filled in the field region and performing element isolation; And
상기 필드 영역 사이의 액티브 영역에 제공되는 트랜지스터들;Transistors provided in an active region between the field regions;
을 포함한다.It includes.
본 발명에 따르면, 종래의 SIMOX 기술이나 웨이퍼 본딩 기술에서 발생할 수 있는 이온주입에 의한 결함과 접합 시에 발생하는 보이드 결함 없이도 SOI 상에 반도체 소자를 일관된 공정으로 진행시킬 수 있다.According to the present invention, a semiconductor device can be processed in a consistent process on an SOI without defects caused by ion implantation and void defects occurring at the time of bonding in the conventional SIMOX technology or wafer bonding technology.
이하, 첨부된 도면을 참조하여, 본 발명의 실시예에 따른 에피택셜 실리콘을 이용한 반도체 소자 및 그 제조 방법을 상세히 설명한다.Hereinafter, a semiconductor device using epitaxial silicon and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3j는 각각 본 발명의 실시예에 따라 에피택셜 실리콘을 이용한 SOI 제조 공정을 나타내는 도면들이다.3A to 3J are diagrams illustrating an SOI manufacturing process using epitaxial silicon, respectively, according to an exemplary embodiment of the present invention.
먼저, 반도체 기판 또는 실리콘 웨이퍼(31) 표면에 SiO2 또는 Si3N4 절연층(33)을 성장시킨다(도 3a 참조). 이후, 사진 및 식각 공정을 이용하여, 필드가 형성될 부분의 절연층(33)을 식각하여, 필드 부분의 실리콘(31)이 노출되게 한다(도 3b 참조). 여기서, 도면부호 C는 식각에 의해 노출된 실리콘 웨이퍼(31)를 나타낸다.First, an SiO 2 or Si 3 N 4 insulating layer 33 is grown on the surface of a semiconductor substrate or silicon wafer 31 (see FIG. 3A). Then, using the photo and etching process, the insulating layer 33 of the portion where the field is to be formed is etched to expose the silicon 31 of the field portion (see FIG. 3B). Here, reference numeral C denotes the silicon wafer 31 exposed by etching.
다음으로, 상기 실리콘이 노출된 부분(C)에만 선택적으로 실리콘 에피택셜층(Epitaxial layer: 35)을 성장(growth)시킨다(도 3c 참조). 즉, 상기 노출된 실리콘 표면을 씨드(seed)로 하여 선택적 실리콘 에피택셜층(35)을 성장시킨다. Next, a silicon epitaxial layer 35 is selectively grown only on the portion C where the silicon is exposed (see FIG. 3C). That is, the selective silicon epitaxial layer 35 is grown using the exposed silicon surface as a seed.
참고로, 에피택셜 웨이퍼는 Polished Wafers를 EPI로 내에서 고주파 또는 적외선으로 가열하여 표면에 실리콘층을 기상 성장시킨 웨이퍼를 말하며, 이때, 저항율은 실리콘 웨이퍼와 틀려지게 된다. 여기서, Polished Wafer는 식각된 웨이퍼(Etched Wafers)에서 폴리싱(Polishing) 공정을 통하여 표면이 경면을 가지게 된 웨이퍼를 말한다.For reference, an epitaxial wafer refers to a wafer in which a silicon layer is vapor-grown on a surface by heating polished wafers in a high frequency or infrared ray in an EPI furnace, where the resistivity is different from that of the silicon wafer. Here, the polished wafer refers to a wafer whose surface has a mirror surface through a polishing process in etched wafers.
구체적으로, 상기 에피택셜 웨이퍼(또는 에피 웨이퍼)는 기존의 실리콘 웨이퍼 표면에 또 다른 단결정층을 성장시킨 웨이퍼를 말하며, 기존의 실리콘 웨이퍼보다 표면 결함이 적고, 불순물의 농도나 종류의 제어가 가능한 특성을 지니게 된다. 이러한 에피 공정은 현재 반도체 제조에서 가장 기본이 되는 공정이면서, 핵심이 되는 공정이며, 실리콘 웨이퍼 제조에 이용되어 고품질, 고부가가치화가 가능하다. 또한, 상기 에피택셜층의 성장은 다양한 방법으로 가능하며, 그중에서도 화학적 기상 증착(Chemical Vapor Deposition: CVD)법을 가장 일반적으로 사용하고 있다.Specifically, the epitaxial wafer (or epitaxial wafer) refers to a wafer in which another single crystal layer is grown on a surface of a conventional silicon wafer, and has fewer surface defects than the conventional silicon wafer, and can control the concentration or type of impurities. Will have. Such epitaxial process is the most basic process and the core process in semiconductor manufacturing at present, and is used in silicon wafer manufacturing to enable high quality and high value. In addition, the epitaxial layer may be grown in various ways, and among them, chemical vapor deposition (CVD) is most commonly used.
다음으로, 상기 선택적 에피택셜에 의해 실리콘 에피택셜층(35)이 성장하여 상기 절연층(33)을 완전히 커버할 수 있도록 실리콘 에피택셜층(35)을 충분히 과도 성장(overgrowth: 37a)시킨다(도 3d 참조). 이때, 상기 실리콘 에피택셜층(37a)이 상기 절연층(33)보다 더 두껍게 성장하게 되면, 상부 쪽 뿐만 아니라 측면 방향으로도 에피택셜 성장하기 때문에 상기 절연층(33) 표면 위로 성장시킬 수 있다.Next, the silicon epitaxial layer 35 is sufficiently overgrowth 37a so that the silicon epitaxial layer 35 is grown by the selective epitaxial layer so as to completely cover the insulating layer 33. 3d). In this case, when the silicon epitaxial layer 37a grows thicker than the insulating layer 33, the silicon epitaxial layer 37a may grow epitaxially not only in the upper side but also in the lateral direction, and thus may be grown on the surface of the insulating layer 33.
다음으로, 상기 실리콘 에피택셜층(37a)을 CMP 공정을 이용하여 평탄화하여 반도체 소자 제조에 필요한 실리콘 에피택셜 두께(37b)만 남긴다(도 3e 참조).Next, the silicon epitaxial layer 37a is planarized using a CMP process to leave only the silicon epitaxial thickness 37b necessary for manufacturing a semiconductor device (see FIG. 3E).
다음으로, 패드 산화막(Pad Oxide; 39) 및 분리 질화막(Isolation Nitride: 41)을 순차적으로 적층한다(도 3f 참조). 이러한 패드 산화막(39) 및 분리 질화막(41)성장은 통상적인 STI(Shallow Trench Isolation) 공정을 적용하게 된다.Next, a pad oxide film 39 and an isolation nitride 41 are sequentially stacked (see FIG. 3F). The growth of the pad oxide layer 39 and the isolation nitride layer 41 is to apply a conventional shallow trench isolation (STI) process.
다음으로, 다시 사진 및 식각 공정을 이용하여 필드가 형성될 부분(D)의 실리콘을 식각한다(도 3g 참조). 이때, 하부의 절연층(33)이 있는 깊이만큼 수직으로 식각한다.Next, the silicon of the portion D where the field is to be formed is etched again using a photo and etching process (see FIG. 3G). At this time, it is etched vertically by the depth of the lower insulating layer 33.
다음으로, 상기 필드 부분(D)을 절연 물질(43a)로 충진하고, 고밀화(densification)시킨다(도 3h 참조).Next, the field portion D is filled with an insulating material 43a and densified (see FIG. 3H).
다음으로, 다시 CMP 방식을 이용하여 상기 절연 물질(43a)을 평탄화함으로써 상기 분리 절연막(43b)을 형성한다(도 3i 참조).Next, the isolation insulating film 43b is formed by planarizing the insulating material 43a using the CMP method again (see FIG. 3I).
다음으로, 상기 분리 질화막(41) 및 패드 산화막(39)을 식각 공정에 의해 제거한다(도 3j 참조).Next, the separation nitride film 41 and the pad oxide film 39 are removed by an etching process (see FIG. 3J).
전술한 도 3a 내지 도 3j의 공정을 통해 에피택셜 실리콘을 이용한 SOI가 완성되며, 이후의 공정은 일반적인 반도체 소자의 후속 제조 공정과 동일하다.3A to 3J, the SOI using epitaxial silicon is completed, and the subsequent process is the same as that of a subsequent semiconductor device.
도 4는 본 발명의 실시예에 따라 에피택셜 실리콘을 이용한 SOI 상에 제조된 반도체 소자를 나타내는 도면으로서, 전술한 도 3a 내지 도 3j의 공정에 의해 제조된 SOI 상의 액티브 영역(45)에 통상적인 후속 공정을 이용하여 MOS 등의 반도체 소자를 제조한 일례를 나타내고 있다.FIG. 4 illustrates a semiconductor device fabricated on an SOI using epitaxial silicon in accordance with an embodiment of the present invention, typical of the active region 45 on the SOI fabricated by the process of FIGS. 3A-3J described above. An example in which semiconductor devices such as MOS are manufactured using a subsequent step is shown.
위에서 발명을 설명하였지만, 이러한 실시예는 이 발명을 제한하려는 것이 아니라 예시하려는 것이다. 이 발명이 속하는 분야의 숙련자에게는 이 발명의 기술 사항을 벗어남이 없어 실시예에 대한 다양한 변화나 변경 또는 조절이 가능함이 자명할 것이다. 그러므로 본 발명의 보호 범위는 첨부된 청구 범위에 의해서만 한정될 것이며, 위와 같은 변화예나 변경예 또는 조절예를 모두 포함하는 것으로 해석되어야 할 것이다.While the invention has been described above, these examples are intended to illustrate rather than limit this invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the embodiments are possible without departing from the technical details of the invention. Therefore, the scope of protection of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.
본 발명에 따르면, 결함 없이 SOI 상에 반도체 소자를 제조할 수 있고, 또한, SOI부터 반도체 소자 제조까지 일관된 공정으로 진행시킬 수 있다.According to the present invention, it is possible to manufacture a semiconductor device on an SOI without defects, and to proceed to a consistent process from SOI to semiconductor device manufacturing.
도 1은 종래의 기술에 따른 웨이퍼 본딩(wafer bonded) 방식으로 제조된 SOI를 나타내는 도면이다.1 is a view showing a SOI manufactured by a wafer bonded method according to the prior art.
도 2a 내지 도 2d는 각각 종래 기술에 따른 SIMOX 방식으로 SOI를 제조하는 공정을 나타내는 도면들이다.2A to 2D are diagrams illustrating a process of manufacturing an SOI in the SIMOX method according to the prior art, respectively.
도 3a 내지 도 3j는 각각 본 발명의 실시예에 따라 에피택셜 실리콘을 이용한 SOI 제조 공정을 나타내는 도면들이다.3A to 3J are diagrams illustrating an SOI manufacturing process using epitaxial silicon, respectively, according to an exemplary embodiment of the present invention.
도 4는 본 발명의 실시예에 따라 에피택셜 실리콘을 이용한 SOI 상에 제조된 반도체 소자를 나타내는 도면이다.4 is a diagram illustrating a semiconductor device manufactured on SOI using epitaxial silicon according to an embodiment of the present invention.
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KR100753670B1 (en) * | 2005-10-28 | 2007-08-31 | 매그나칩 반도체 유한회사 | Silicon-on-insulator wafer and method of fabricating the same |
US7790567B2 (en) | 2007-12-17 | 2010-09-07 | Electronics And Telecommunications Research Institute | Semiconductor device and method for forming the same |
US7915700B2 (en) | 2006-09-29 | 2011-03-29 | Electronics And Telecommunications Research Institute | Monolithic integrated composite device having silicon integrated circuit and silicon optical device integrated thereon, and fabrication method thereof |
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CN113133326A (en) * | 2019-11-11 | 2021-07-16 | 韩商则舒穆公司 | Method for manufacturing SOI substrate |
KR20210108073A (en) * | 2020-02-25 | 2021-09-02 | (주)더숨 | Producing method of silicon on insulator substrate |
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KR100753670B1 (en) * | 2005-10-28 | 2007-08-31 | 매그나칩 반도체 유한회사 | Silicon-on-insulator wafer and method of fabricating the same |
US7915700B2 (en) | 2006-09-29 | 2011-03-29 | Electronics And Telecommunications Research Institute | Monolithic integrated composite device having silicon integrated circuit and silicon optical device integrated thereon, and fabrication method thereof |
US7790567B2 (en) | 2007-12-17 | 2010-09-07 | Electronics And Telecommunications Research Institute | Semiconductor device and method for forming the same |
US8017420B2 (en) | 2008-12-05 | 2011-09-13 | Electronics And Telecommunications Research Institute | Method of forming optical waveguide |
US7927988B2 (en) | 2008-12-22 | 2011-04-19 | Electronics And Telecommunications Research Institute | Method of fabricating semiconductor device |
US8394705B2 (en) | 2009-12-09 | 2013-03-12 | Electronics And Telecommunications Research Institute | Method of manufacturing semiconductor device having optical devices |
CN113133326A (en) * | 2019-11-11 | 2021-07-16 | 韩商则舒穆公司 | Method for manufacturing SOI substrate |
KR20210108073A (en) * | 2020-02-25 | 2021-09-02 | (주)더숨 | Producing method of silicon on insulator substrate |
KR20210111488A (en) * | 2020-03-03 | 2021-09-13 | (주)더숨 | Producing method of multi silicon on insulator substrate and multi silicon on insulator substrate |
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