CN102130039A - Method for preparing semiconductor substrate with insulated buried layer by adopting gettering process - Google Patents
Method for preparing semiconductor substrate with insulated buried layer by adopting gettering process Download PDFInfo
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- CN102130039A CN102130039A CN2010106080618A CN201010608061A CN102130039A CN 102130039 A CN102130039 A CN 102130039A CN 2010106080618 A CN2010106080618 A CN 2010106080618A CN 201010608061 A CN201010608061 A CN 201010608061A CN 102130039 A CN102130039 A CN 102130039A
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Abstract
The invention relates to a method for preparing a semiconductor substrate with an insulated buried layer by adopting a gettering process. The method comprises the following steps of: providing a device substrate and a support substrate; forming an insulated layer on the surface of the device substrate; carrying out thermal treatment on the device substrate by adopting a two-step thermal treatment process; bonding the device substrate with the insulated layer and the support substrate so that the insulated layer is clamped between the device substrate and the support substrate; carrying out annealing and reinforcing on a bonding interface; and chamfering, grinding, thinning and polishing the bonded device substrate. The invention has the advantages that: the device substrate is treated with a gettering process before bonding, a cleaning region is formed on the surface of the device substrate, and then the cleaning region is transferred onto another support substrate to obtain a bonding material with high crystal quality. In addition, the two-step thermal treatment step is adopted only in the process of carrying out thermal treatment on the device substrate, and a third high temperature thermal treatment step and the follow-up reinforced and bonded interface are integrated into one step, therefore, the process complexity is reduced, the process cost is saved, and the process efficiency is improved.
Description
Technical field
The invention relates to a kind of method for preparing silicon-on-insulator material, particularly a kind of method that adopts the gettering process preparation to have the Semiconductor substrate of insulating buried layer.
Background technology
Along with reducing of the characteristic size of integrated circuit, defect Control in the silicon single crystal is become to be even more important.Defective in the silicon chip is the primary defective that produces in the process of crystal growth, as crystal primary partical (COPs) mainly from two aspects on the one hand; Be the defective that produces in the wafer heat process on the other hand,,, make component failure if these defectives in the active region of silicon chip surface, will have destruction to the performance of device as oxygen precipitation.In addition, silicon chip will be subjected to the contamination as metals such as Cu, Ni and Fe inevitably in the process of processing and integrated circuit manufacturing, the diffusion of these metal impurities in silicon is very fast, if be present in the active area of device, to cause the inefficacy of device, the metal impurities of therefore eliminating silicon chip surface effectively are vital.Oxygen precipitation and induce the gettering point that defective can be used as metal impurities makes metal impurities assemble at fault location, if but oxygen precipitation and induce defective and appear at the device active region also can influence the electric property of device.Therefore, in device technology, on the one hand need in silicon chip, produce a large amount of oxygen precipitations, play the effect of gettering, wish again that on the other hand oxygen precipitation does not appear at the active region of silicon chip, the basic concept of Here it is intrinsic gettering (Internal Gettering).Internal Gettering of Silicon Wafers technology by heat treatment, forms the clean zone (Denuded Zone-DZ) of hypoxemia and low metal at silicon chip surface, and forms oxygen precipitation and induce defective to absorb metal impurities in wafer bulk.Through the silicon chip of DZ PROCESS FOR TREATMENT, device prepares in the DZ zone, can improve the yield of device effectively.
In addition, thick film SOI material (top layer silicon is usually greater than 1 μ m) is widely used in high voltage power device and MEMS (micro electro mechanical system) (MEMS) field at present, particularly in the development of aspects such as automotive electronics, demonstration, wireless telecommunications rapidly.Because the control of power supply and conversion, automotive electronics and consumer power device aspect make that to the requirement of adverse circumstances, high temperature, big electric current, high power consumption aspect the strict demand aspect reliability has to adopt the SOI device.The user of thick film SOI material mainly comprises U.S. Maxim, ADI, TI (USA), Japanese NEC, Toshiba, Panasonic, Denso, TI (Japan), FUJI, Omron etc., European Philips, X-Fab etc. at present.In these SOI materials user the inside, very big application is mainly derived from the drive circuit in the various application: as the amplifier circuit that is applied to be mainly mobile phone acceptance section of Maxim; Panasonic, TI, FUJI, Toshiba, NEC etc. are mainly used in the scan drive circuit in the display driver circuit; The application of DENSO is mainly at automotive electronics, wireless radio frequency circuit etc.; The application of Toshiba even in the power control circuit of air-conditioning; Omron is mainly aspect transducer; ADI is also mainly at high temperature circuit, transducer etc.; The application of Phillips then mainly is the LDMOS in the power device, is used for consumer electronics such as automobile audio, audio frequency, audio frequency amplifier etc.; The Magnchip of Korea S (Hynix) then is used for display driver circuit that digital camera uses and for the PDP display driver circuit of LG production etc. for Kopin produces.
But, for the SOI material, because the existence of oxygen buried layer, if it is heat-treated, the oxygen element of oxygen buried layer will outdiffusion, makes that on the contrary oxygen element content raises in its top layer silicon, and therefore traditional gettering process is not suitable for the SOI material, also cause the top layer silicon of SOI material not have this DZ zone, make that like this yield of devices of SOI preparation is relatively low.
Summary of the invention
Technical problem to be solved by this invention is that a kind of gettering process that can be applicable to the Semiconductor substrate that has insulating buried layer is provided.
In order to address the above problem, the invention provides a kind of method that adopts the gettering process preparation to have the Semiconductor substrate of insulating buried layer, comprise the steps: to provide device substrate and support substrates; Surface in device substrate forms insulating barrier; First heat treatment step is to form crystal region on the device substrate surface; Second heat treatment step, temperature are lower than the first heat-treatment of annealing step, so that the saturated oxygen element in the device substrate beyond the clean zone gathers nucleation; The device substrate and the support substrates bonding that will have insulating barrier are clipped between device substrate and the support substrates insulating barrier; The para-linkage interface is implemented annealing and is reinforced, make the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing, make the oxygen element that gathers nucleation in the last cooling step form bigger oxygen precipitation simultaneously, described oxygen precipitation can absorb the metal impurities in the clean zone simultaneously; Device substrate behind the para-linkage is implemented chamfer grinding, attenuate and polishing.As optional technical scheme, described device substrate is a monocrystalline substrate.
As optional technical scheme, comprise the steps: that further after device substrate was implemented chamfer grinding, attenuate and glossing, the para-linkage rear interface was implemented to replenish annealing and reinforced.
As optional technical scheme, further comprise the steps: before device substrate is implemented chamfer grinding, attenuate and glossing, on the surface that support substrates comes out, to form protective layer.
The invention has the advantages that adopt gettering process that device substrate is handled, the surface forms clean zone, subsequently this clean area is transferred on another sheet support substrates, obtains having the bonding material of high-crystal quality before bonding.And two step heat treatment steps in the technology of heat treatment device substrate, have only been adopted, and the step of the 3rd step high temperature heat treatment step and follow-up reinforcing bonded interface is integrated into a step, thereby reduced process complexity, saved the technology cost and improved process efficiency.
Description of drawings
Shown in the accompanying drawing 1 the implementation step flow chart of the specific embodiment of the invention,
Accompanying drawing 2A is to shown in the accompanying drawing 2E being the process schematic representation of the specific embodiment of the invention.
Embodiment
Next introduce a kind of embodiment that adopts gettering process to prepare the method for the Semiconductor substrate that has insulating buried layer of the present invention in conjunction with the accompanying drawings in detail.
Be the implementation step flow chart of this method shown in the accompanying drawing 1, comprise: step S10 provides device substrate and support substrates; Step S11 forms insulating barrier on the surface of device substrate; Step S12, heat treatment device substrate, thus form clean regional on the surface of described device substrate; Step S13 will have the device substrate and the support substrates bonding of insulating barrier, and insulating barrier is clipped between device substrate and the support substrates; Step S14, the para-linkage interface is implemented annealing and is reinforced, and makes the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing; Step S15, the device substrate behind the para-linkage is implemented chamfer grinding, attenuate and polishing; Step S16, para-linkage rear interface implement to replenish annealing and reinforce.
Accompanying drawing 2A is to shown in the accompanying drawing 2E being the process schematic representation of the specific embodiment of the invention.
Shown in the accompanying drawing 2A, refer step S10 provides device substrate 100 and support substrates 190.Described device substrate 100 is used to form the device layer of final products, so its material should be a for example monocrystalline silicon of common semi-conducting material, also can be that other are as compound semiconductor etc.And support substrates 190 is owing to only play a supporting role, so selection range is wider, except monocrystalline silicon and common compound semiconductor materials, also can is sapphire even can is metal substrate.In the present embodiment, device substrate 100 is monocrystalline silicon with the material of support substrates 190.
Shown in the accompanying drawing 2B, refer step S11 forms insulating barrier 110 on the surface of device substrate 100.Described insulating barrier 110 is used to form the insulating buried layer of final products, and its material can be silica or silicon nitride etc., and growing method can be chemical vapour deposition (CVD) or thermal oxidation (be used for the monocrystalline substrate surface and form insulating layer of silicon oxide).
Shown in the accompanying drawing 2C, refer step S12, heat treatment device substrate 100, thus form clean regional 101 on the surface of described device substrate 100.
Above step can further be decomposed into first and second heat treatment steps, and wherein first heat treatment is high-temperature annealing step, and second heat treatment is relative process annealing step.High-temperature annealing step forms crystal region on the device substrate surface; The process annealing step makes the saturated oxygen element in the device substrate in addition of clean zone gather nucleation.Gettering process of the prior art also should comprise a high-temperature annealing step after the process annealing step, present embodiment is integrated into a step with the step of the 3rd step high temperature heat treatment step and follow-up reinforcing bonded interface, can reduce process complexity, save the technology cost and improve process efficiency.
Specifically; the target temperature of high-temperature annealing step is any temperature value in 900 ℃～1400 ℃ scopes; the target temperature of optimizing is 1250 ℃; the lasting annealing time that rises to behind the target temperature is 0.5～20 hour; be optimized for 4 hours; programming rate is 0.5～20 ℃/minute, and the programming rate of optimization is 3 ℃/minute, and the protective gas in the temperature-rise period is optimized for Ar/O
2Mist can be other gas or mist, and the atmosphere that continues annealing is N
2, Ar (perhaps other inert gases), H
2, O
2, N
2/ O
2Mist, Ar/O
2Mist, Ar/H
2Mist and N
2In/Ar the mist any one.Heat up for the first time and annealing process in, the outdiffusion of device substrate 100 near surf zone interstitial oxygen concentrations, the width of the temperature and time decision clean area 101 of this step annealing, clean after treatment regional 101 width is generally 10～50 μ m.
The cooling rate of process annealing step is 0.5～20 ℃/minute, the cooling rate of optimizing is 3 ℃/minute, the target temperature of cooling is any temperature value in 500～900 ℃ of scopes, the target temperature of optimizing is 750 ℃, the lasting annealing time of reducing to behind the target temperature is 0.5～64 hour, the optimization time is 8 hours, and annealing atmosphere is an oxygen-free atmosphere, specifically can be N
2, Ar (perhaps other inert gases), H
2The perhaps mist of above gas.In this cooling step, saturated oxygen element gathers nucleation in the device substrate 100 in addition of clean zone 101 with making.
The enforcement order of above step S11 and S12 can be put upside down.The advantage that step S11 is at first implemented is that the insulating barrier 110 that generates in advance can form protection to device substrate 100 surfaces, and can shorten heat treatment period, thereby reduces cost.And under the situation that step S11 implements after step S12, be in the execution mode of monocrystalline silicon in device substrate 100, can after the process annealing step, implement in-situ oxidation, the oxidizing temperature of optimization is 1050 ℃.Oxidization time is determined that by needed oxidated layer thickness oxidizing atmosphere is dried oxygen or wet oxygen, or Ar/O
2Mist will form layer of oxide layer on its surface after the oxidation, and this oxide layer can be used as insulating barrier 110.
Shown in the accompanying drawing 2D, refer step S13 will have the device substrate 100 and support substrates 190 bondings of insulating barrier 110, and insulating barrier 110 is clipped between device substrate 100 and the support substrates 190.
In support substrates 190 is in the execution mode of monocrystalline substrate, can be chosen in before the bonding monocrystalline silicon support substrates 190 to be ground and pre-treatment such as polishing, with its thickness of attenuate.With 8 inches monocrystalline substrate is example, 750 microns of substrate thickness, the substrate total thickness deviation is less than 4 microns, the target thickness of substrate thinning is 650 microns, at first grind this monocrystalline substrate of attenuate, milling apparatus is preferably the single face grinder, unit type is DFG 841 type grinders, at first roughly grind quick attenuate, grinding wheel speed is greater than 2000rpm, and correct grinding reduces to grind the damage that causes subsequently, and grinding wheel speed is greater than 2000rpm, grind back substrate thickness and more than 3 microns, be thinned to 660 microns here greater than target thickness.Support substrates 190 after grinding is polished, and can be that twin polishing also can be a single-sided polishing, also can be two-sided+single-sided polishing, is optimized for two-sided+single-sided polishing here.At first twin polishing, unit type are Peter Wolters AC2000 type Twp-sided polishing machine, and whole polishing process was divided into for two steps, at first rough polishing, finishing polish subsequently, and always polishing removal amount is 8 microns; Adopt single-sided polishing with accurate control silicon wafer thickness subsequently, unit type is IPEC 372 type single side polishing machines, and whole polishing process is divided into rough polishing and two steps of finishing polish equally, and the polishing removal amount is not more than 2 microns, after revising, can make the substrate total thickness deviation less than 1 micron.
Before can also being chosen in bonding support substrates 190 is carried out the insulating processing, make its appearance cover one deck insulation etch resistant layer, particularly make its back side cover this etch resistant layer, optimize insulating treatment process and get final product, also can adopt PECVD deposit silicon dioxide silicon nitride etc. for the ordinary oxygen metallization processes.Etch resistant layer thickness is generally one micron.Because technology backward is ruggedization under lower temperature, support substrates 190 possibly can't stop the corrosion of TMAH solution in chamfer angle technique, form a lot of etch pits overleaf, therefore generates one deck insulation etch resistant layer in advance, makes its effectively back side of protection support substrates.
After support substrates 190 carried out pre-treatment, device substrate 100 and support substrates 190 are cleaned and bondings.Bonding can be that common hydrophilic bonding also can be a hydrophobic bonding, it also can be the auxiliary hydrophilic bonding of plasma, be preferably the auxiliary hydrophilic bonding of hydrophilic bonding and plasma, here be combined into example with hydrophilic bond, use SC1 and SC2 solution to clean this substrate successively, before the bonding, on EVG801 bonding machine, adopt rotation to clean device substrate 100 and support substrates 190 substrates, to remove the particle that the surface may exist and to adsorb more hydrone, subsequently device substrate 100 and support substrates 190 are bonded together.
Refer step S14, the para-linkage interface is implemented annealing and is reinforced, and makes the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing.It is 900～1400 ℃ that temperature is reinforced in annealing, and the temperature of optimization is 1150 ℃, and the annealing consolidation time is 0.5～10 hour, be optimized for 6 hours, programming rate is 0.5～20 ℃/minute, and the programming rate of optimization is 3 ℃/minute, and annealing atmosphere is optimized for dried oxygen or wet oxygen.This step also makes the oxygen element that gathers nucleation in the last process annealing step form bigger oxygen precipitation, and described oxygen precipitation can absorb the metal impurities in the clean zone simultaneously.
Adopt above annealing reinforcing condition then to need not to replenish the step of reinforcing, promptly need not implementation step S16.If in this step, select more gentle annealing conditions, then need replenish at subsequent implementation step S16.The temperature of reinforcing of for example will annealing is chosen in 500～1200 ℃, is optimized for 900 ℃, and consolidation time is 1～10 hour, is optimized for 4 hours, and it is N that atmosphere is reinforced in annealing
2, Ar (perhaps other inert gases), O
2, N
2/ O
2Mist, Ar/O
2Mist etc.The consolidation effect at below more gentle annealing conditions para-linkage interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing equally.
Shown in the accompanying drawing 2E, refer step S15, the device substrate 100 behind the para-linkage is implemented chamfer grinding, attenuate and polishing.Accompanying drawing 2E is the state after above-mentioned process implementing finishes, it is pointed out that through in the steps such as attenuate and polishing to the control of removal amount, can guarantee that the device substrate 100 that is kept among the accompanying drawing 2E all is to be made of clean zone 101.
Step S16, para-linkage rear interface implement to replenish annealing and reinforce.If what adopted among the step S14 is relatively mild annealing reinforcement process, then need to select to implement this step, to strengthen the bond strength between support substrates 190 and the insulating barrier 110, forming covalent bond at the interface.The annealing temperature of this step is 900～1400 ℃, and the annealing temperature of optimization is 1150 ℃, and annealing time is 0.5～10 hour, be optimized for 4 hours, programming rate is 0.5-20 ℃/minute, and the programming rate of optimization is 3 ℃/minute, and annealing atmosphere is optimized for dried oxygen or wet oxygen.For the device substrate 100 that constitutes by single crystal silicon material, in the process of this oxidation, also further formed layer of oxide layer on device substrate 100 surfaces, can further control the thickness of the device substrate 100 that is consumed by the thickness of controlled oxidation layer, reach the purpose of accurate control device layer thickness.HF solution removal oxide layer is adopted in the annealing back, obtains the final substrate that has insulating buried layer, and its device layer is made of the clean zone 101 of device substrate 100.
The advantage of technique scheme is, before bonding, adopt gettering process that device substrate 100 is handled, the surface forms clean zone 101, should transfer on another sheet support substrates 190 in cleaning zone 101 subsequently, obtains having the bonding material of high-crystal quality.And two step heat treatment steps in the technology of heat treatment device substrate 100, have only been adopted, and the step of the 3rd step high temperature heat treatment step and follow-up reinforcing bonded interface is integrated into a step, thereby reduced process complexity, saved the technology cost and improved process efficiency.
In sum; though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; the persond having ordinary knowledge in the technical field of the present invention; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining that claims apply for.
Claims (4)
1. a method that adopts the gettering process preparation to have the Semiconductor substrate of insulating buried layer is characterized in that, comprises the steps:
Device substrate and support substrates are provided;
Surface in device substrate forms insulating barrier;
First heat treatment step is to form crystal region on the device substrate surface;
Second heat treatment step, temperature are lower than the first heat-treatment of annealing step, so that the saturated oxygen element in the device substrate beyond the clean zone gathers nucleation;
The device substrate and the support substrates bonding that will have insulating barrier are clipped between device substrate and the support substrates insulating barrier;
The para-linkage interface is implemented annealing and is reinforced, make the firm degree of bonded interface can satisfy the requirement of follow-up chamfer grinding, attenuate and glossing, make the oxygen element that gathers nucleation in the last cooling step form bigger oxygen precipitation simultaneously, described oxygen precipitation can absorb the metal impurities in the clean zone simultaneously;
Device substrate behind the para-linkage is implemented chamfer grinding, attenuate and polishing.
2. method according to claim 1 is characterized in that, described device substrate is a monocrystalline substrate.
3. method according to claim 1 is characterized in that, comprises the steps: that further after device substrate was implemented chamfer grinding, attenuate and glossing, the para-linkage rear interface was implemented to replenish annealing and reinforced.
4. method according to claim 1 is characterized in that, further comprises the steps: to form protective layer on the surface that support substrates comes out before device substrate is implemented chamfer grinding, attenuate and glossing.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010608061 CN102130039B (en) | 2010-12-27 | 2010-12-27 | Method for preparing semiconductor substrate with insulated buried layer by adopting gettering process |
| JP2013546558A JP5752264B2 (en) | 2010-12-27 | 2010-12-31 | Method for manufacturing a semiconductor substrate with an insulating layer by an impurity gettering process |
| KR1020137019860A KR101512393B1 (en) | 2010-12-27 | 2010-12-31 | Method for preparing semiconductor substrate with insulating buried layer by gettering process |
| US13/976,486 US9299556B2 (en) | 2010-12-27 | 2010-12-31 | Method for preparing semiconductor substrate with insulating buried layer gettering process |
| PCT/CN2010/080599 WO2012088710A1 (en) | 2010-12-27 | 2010-12-31 | Method for preparing semiconductor substrate with insulating buried layer by gettering process |
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| CN 201010608061 CN102130039B (en) | 2010-12-27 | 2010-12-27 | Method for preparing semiconductor substrate with insulated buried layer by adopting gettering process |
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| CN102130039A true CN102130039A (en) | 2011-07-20 |
| CN102130039B CN102130039B (en) | 2013-04-10 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104925749A (en) * | 2015-04-17 | 2015-09-23 | 上海华虹宏力半导体制造有限公司 | Silicon wafer bonding method |
| CN107973269A (en) * | 2017-12-18 | 2018-05-01 | 中国电子科技集团公司第四十六研究所 | A kind of production method of MEMS device sandwich construction silicon chip |
| CN117316764A (en) * | 2023-11-28 | 2023-12-29 | 上海威固信息技术股份有限公司 | Semiconductor silicon wafer processing method |
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