CN110010458A - Control the method and semiconductor wafer of semiconductor crystal wafer surface topography - Google Patents
Control the method and semiconductor wafer of semiconductor crystal wafer surface topography Download PDFInfo
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- CN110010458A CN110010458A CN201910257002.1A CN201910257002A CN110010458A CN 110010458 A CN110010458 A CN 110010458A CN 201910257002 A CN201910257002 A CN 201910257002A CN 110010458 A CN110010458 A CN 110010458A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Abstract
The invention discloses the methods and semiconductor wafer of control semiconductor crystal wafer surface topography, wherein, the method of control semiconductor crystal wafer surface topography includes: to carry out thinning single surface processing to the front of semiconductor crystal wafer, so as to the convex surface for making surface formation center high rim low；Rough polishing processing, middle throwing processing and smart throwing processing are successively carried out to two surfaces of semiconductor crystal wafer by thinning single surface processing, to obtain semiconductor wafer.Semiconductor wafer surface flatness can effectively improve using this method, reduce thickness deviation, improve multiple-piece single-sided polishing technique level of processing, the requirement for semiconductor wafer can satisfy integrated circuit line width that treated.
Description
Technical field
The invention belongs to semiconductor crystal wafer fields, specifically, the present invention relates to control semiconductor crystal wafer surface shapes
The method and semiconductor wafer of looks.
Background technique
Semiconductor wafer, truncation, round as a ball monocrystal rod usually are prepared with as semiconductor monocrystal silicon rod, and monocrystal rod is ground line
It is cut into the one or more flat surfaces being properly positioned in subsequent handling for chip.Then crystal ingot is cut into difference
It is subjected to reducing wafer thickness, removes the damage as caused by cutting processing and forms the independence of many processings of high reflection surface
Semiconductor wafer.In common chip Shape correction, to reduce in the risk for being further processed period damage wafers, each
The circumferential edges rounding of wafer.Then use abrasive (grinding slurry) and the abrasive disk of a set of rotation in the positive and negative table of chip
Attrition process is carried out on face.Attrition process reduces the thickness of chip to remove the surface damage caused by cutting and make every wafer
Opposite side surface it is flat and parallel.In addition to this, chip also replaces twin grinding using two-sided thining method.I.e. one
All opposite to each other to abrasive wheel (grinding wheel), chip therebetween is clamped, makes its vertical orientation.Grinding wheel is transported relative to chip high speed
Dynamic, chip can obtain good flatness.
Attrition process one is completed, and chip is subjected to corrosion treatment, is further decreased the thickness of chip and is removed by previous
Mechanical damage caused by processing.Then with polishing pad, colloidal silica slurry (polishing slurries) and chemical mordant polishing
A side surface (" front " that is often referred to chip) in each wafer is to ensure that chip has high reflection, undamaged table
Face.The two-step method of general rough polishing and the finishing polish for reducing non-secular reflected light (optical haze) using coarse grained abrasive polishes chip.
The patent semiconductor wafer processing of MEMC Electronic Materials, Inc.'s publication, patent No. CN1272222A, hair
The front and back that semiconductor wafer is thinned with grinding wheel is illustrated, quickly reduces the thickness of semiconductor wafer.Then abrasive sand is used
Grinding semiconductor chip tow sides are starched, the thickness of semiconductor wafer is further reduced.Then semiconductor die is polished with polishing fluid
Piece tow sides make chip reach scheduled final thickness.The patent also elaborates, is also thinned using grinding wheel partly leads before polishing
Body wafer front side technology, for reducing the polishing time.Since semiconductor wafer, the removal rate ratio of chip is thinned in grinding wheel
Comparatively fast, therefore the patent uses thinning technique, for before twin grinding process and before polishing process, it is therefore an objective to reduce two-sided grind
Grind the process time of process time and polishing process processing semiconductor wafer.Although grinding wheel reduction process is for semiconductor wafer
Removal rate can also have an impact semiconductor damage to wafers layer, nanotopography, profile than very fast.What is deteriorated partly leads
The damaging layer of body wafer surface, nanotopography, profile, which can generate polishing process, to be deteriorated as a result, making nothing after wafer polishing
Method obtains the chip of good mirror surface, nanotopography, profile.The patent is not described how thinning technique controls chip
Damaging layer, nanotopography, profile.
The patent of German SILTRONIC company invention: it is partly led for polishing semiconductor wafer method and being manufactured with this method
Body chip, the patent No. (CN101148025B).The invention is related to for polishing semiconductor between upper polishing disk and lower polishing disk
The method of chip, wherein the semiconductor wafer is in the cavity of a turntable in the case where inputting polishing agent by twin polishing.
This method comprises: twin polishing semiconductor wafer in the first polishing step, which is terminated with a negative excess,
Wherein, which is the difference after first polishing step between the thickness of the semiconductor wafer and the thickness of the turntable；?
Twin polishing semiconductor wafer in second polishing step is skimmed in second polishing step from the side of the semiconductor wafer
Material less than 1 μm.The present invention also relates to semiconductor wafer, which is made of silicon, is had one and is polished just
Face and the back side being polished have through the SBIRmax value less than 100nm the global flatness in the front expressed, and
There is the partly flat degree in front expressed by 35nm or smaller PSFQR value in a fringe region, wherein always examine
Consider the edge exclusion amount of 2mm.
The profile of the patent first step polishing control semiconductor wafer of German SILTRONIC company invention, make chip at
Concavity.Second step controls the surface topography of chip again, to reach relatively good flatness and ESFQR.
From the point of view of experience according to twin polishing technique, since twin polisher generally processes 5-15 wafer (depending on setting
Standby price fixing size), the shape (bumps) for being difficult to control twin polishing is compared in this bath formula processing.Since twin polishing is general
Polishing removal amount is 10-15 μm, and polishing speed is slow, and each bath polishing time is generally at 20-30 minutes.For for a long time
Polishing, wafer topography are often difficult to control.
Semiconductor crystal wafer passes through wire cutting, chamfering, double side grinding process, and silicon chip surface obtains relatively good smooth
Degree.After super-corrosion process, especially after sour etching technique, the flatness of wafer surface can deteriorate, this is for polishing process
It is unfavorable.Single side and twin polisher be for example: Lapmaster, Speedfam, Fujikoshi etc. are to the smooth of wafer
Degree, surface damage layer, nanotopography etc. propose relatively high requirement.Such as, thickness deviation consistent to flatness etc..
Traditional polishing process needs to correct throwing before polishing using the three step polishing processes that rough polishing-essence throwing-mirror surface is thrown
Light pad.So-called amendment polishing pad is i.e.: skive sanding and polishing pad, until polishing pad meets the flatness of semiconductor wafer
It is required that.If not modifying polishing pad, silicon chip surface will form concave surface.This is because polishing pad generally uses polyurethane material,
In polishing process, polishing fluid enters silicon wafer center from silicon chip edge, and in the initial stage, polishing fluid center grinding rate is big, edge
The case where grinding rate is small, and silicon wafer generates concave surface, deterioration is recessed to enter 4-5 μm.Seriously affect the flat of semiconductor crystal wafer
Whole degree.And polishing efficiency can be reduced by repeatedly correcting polishing pad not only, while can also shorten the service life of polishing pad.
Therefore, the processing technique of semiconductor wafer requires further improvement at present.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.For this purpose, of the invention
One purpose is to propose a kind of method and semiconductor wafer for controlling semiconductor crystal wafer surface topography, uses this method can be with
Semiconductor crystal wafer surface smoothness is effectively improved, thickness deviation is reduced, improves multiple-piece single-sided polishing technique level of processing, place
Semiconductor crystal wafer after reason can satisfy the requirement of integrated circuit line width.
According to an aspect of the present invention, the invention proposes it is a kind of control semiconductor crystal wafer surface topography method,
According to an embodiment of the invention, this method comprises:
Thinning single surface processing is carried out to the front of semiconductor crystal wafer, to form the front by center to edge
Gradually thinning convex surface；
Rough polishing processing, middle throwing processing are successively carried out to two surfaces of semiconductor crystal wafer by thinning single surface processing
It is handled with smart throwing, to obtain semiconductor wafer.
In addition, it is according to the above embodiment of the present invention control semiconductor crystal wafer surface topography method can also have as
Under additional technical characteristic:
In some embodiments of the invention, A point on the workbench for the thinning single surface machine that the thinning single surface processing uses
Position is -1 μm~-10 μm, and preferably -1-3 μm, B point is set to -1 μm~-10 μm, preferably -7-9 μm.
In some embodiments of the invention, the thinning single surface processing uses granularity for 0.5-4 μm of grinding wheel, preferably adopts
The grinding wheel for being 0.5-1 μm with granularity.
In some embodiments of the invention, the micro- meter per second of the grinding wheel feed speed 0.1-1.
In some embodiments of the invention, the revolving speed of the grinding wheel is 1000-3000rpm.
In some embodiments of the invention, the revolving speed of the workbench is between 100-300rpm.
In some embodiments of the invention, the centre-height on the convex surface is 3-5 μm.
In some embodiments of the invention, in 1 μm under the flatness of the semiconductor wafer.
According to the second aspect of the invention, the invention also provides semiconductor wafers, according to an embodiment of the invention, described
Semiconductor wafer handles to obtain using method described in preceding embodiment.
Detailed description of the invention
Fig. 1 is the schematic illustration of thinning single surface processing according to an embodiment of the invention.
Fig. 2 is the surface topography signal of semiconductor crystal wafer after thinning single surface processing according to an embodiment of the invention
Figure.
Fig. 3 is according to an embodiment of the invention to semiconductor crystal wafer progress cross section test after being thinned
Result figure.
Fig. 4 is the result figure according to an embodiment of the invention that test surfaces damaging layer is carried out to semiconductor crystal wafer.
Fig. 5 is the result figure according to an embodiment of the invention that test TTV, THK are carried out to chip after polished semiconductor.
Fig. 6 is the result figure according to an embodiment of the invention that cross section test is carried out to semiconductor wafer.
Fig. 7 is the result figure according to an embodiment of the invention that SFQR test is carried out to semiconductor wafer.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
The present invention is that the following discovery based on inventor is completed:
Traditional polishing process includes that rough polishing-essence throwing-mirror surface throws three steps, and the polishing pad that polishing process uses generally is adopted
With polyurethane material, during the polishing process, polishing fluid enters semiconductor crystal wafer center from semiconductor crystal wafer edge, initial
The grinding rate in stage, semiconductor crystal wafer center is big, and edge polishing rates are small.Therefore, before polishing with needed in polishing process
Polishing pad is constantly corrected, if not correcting polishing pad, semiconductor crystal wafer surface will not be respectively formed concave surface due to grinding, dislike
3-5 μm can be fallen in the case of change.Seriously affect the flatness of semiconductor crystal wafer.And repeatedly correcting polishing pad can not only reduce
Polishing efficiency, while can also shorten the service life of polishing pad.
For this purpose, according to an aspect of the present invention, the invention proposes a kind of control semiconductor crystal wafer surface topographies
Method, according to an embodiment of the invention, this method comprises:
Thinning single surface processing is carried out to the front of semiconductor crystal wafer, to form the front by center to edge
Gradually thinning convex surface,
Rough polishing processing, middle throwing processing are successively carried out to two surfaces of semiconductor crystal wafer by thinning single surface processing
It is handled with smart throwing, to obtain semiconductor wafer.
The method of the control semiconductor crystal wafer surface topography of the above embodiment of the present invention passes through in advance to semiconductor crystal wafer
The front of piece carries out thinning single surface processing, to form the front by center to edge gradually thinning convex surface.Then
Rough polishing processing, middle throwing processing and smart throwing processing are carried out again, and reduce or save amendment polishing pad in above-mentioned polishing process
Process, and then can use the concave surface that is not respectively formed of polishing pad grinding and offset thinning single surface and handle preformed convex surface.By
This, thinning single surface processing is combined by the method for the above embodiment of the present invention with polishing treatment, handles shape using thinning single surface
At convex surface offset polishing treatment during reduce or save amendment polishing pad process and the concave surface that is formed, improve half to reach
The purpose of conductor wafer flatness, and then it is made to meet the requirement of integrated circuit line width.Therefore, the above method of the invention can be with
The process for effectively reducing or saving amendment polishing pad, extends the service life of polishing pad, while can also significantly improve polishing
Efficiency.It is heavier, the thickness deviation of semiconductor crystal wafer can be effectively reduced using the above method, improve flatness.In turn
The level of processing for improving multiple-piece single-sided polishing technique, meets the requirement of integrated circuit line width.
The method that the control semiconductor crystal wafer surface topography of the above embodiment of the present invention is described below in detail.
According to a particular embodiment of the invention, firstly, in order to enable the surface of semiconductor crystal wafer forms convex surface, the present invention
Using thinning single surface treatment process.Specifically, thinning single surface processing is carried out to the front of semiconductor crystal wafer, to make surface
The low convex surface of formation center high rim.
According to a particular embodiment of the invention, above-mentioned thinning single surface processing is carried out using the thinned machine of 8 series of DISCO, in turn
Precisely thinned purpose can be improved.
Further, in order to effectively and accurately offset do not correct polishing pad and cause semiconductor crystal wafer surface formed
Recess, inventor has carried out careful screening and research to the technique that thinning single surface polishes, and then obtains by adjusting technological parameter
The convex surface for the preset height that semiconductor crystal wafer surface can be made to be formed.
According to a particular embodiment of the invention, inventor adjusts half by adjusting the levelness of A, B two o'clock on workbench
The pattern of semiconductor wafer piece.Specifically, in the method for the above embodiment of the present invention, the thinning single surface machine of thinning single surface processing use
Workbench on A point be set to -1 μm~-10 μm, B point is set to -1 μm~-10 μm.In carrying out thinning single surface treatment process,
Semiconductor crystal wafer is adsorbed on turntable, and semiconductor crystal wafer is face-up, and first A point is thinned, and B point is thinned again therewith.By
This can make semiconductor crystal wafer surface be effectively formed convex surface after being thinned, and the centre-height on the convex surface is suitable for, can
Worn down by further polishing treatment, to obtain the high semiconductor wafer of surface smoothness.
Specific example according to the present invention, it is preferable that A point on the workbench for the thinning single surface machine that thinning single surface processing uses
Position is -1~-3 μm, and B point is set to -7~-9 μm.The point position A and B point on workbench by accurately controlling thinning single surface machine
It is 3-5 μm of convex surface that position, which can form centre-height in the front of semiconductor crystal wafer,.And then by further progress polishing at
Reason can wear down the height convex surface completely, obtain the higher semiconductor wafer of flatness.When general adjustment reduction process adjustment,
If silicon wafer central protuberance is too high as more than 5 microns, the position of B can be turned up, to meet 3-5 microns of silicon wafer central protuberance of work
Skill demand.
According to a particular embodiment of the invention, further, thinning single surface processing uses granularity for 0.5-4 μm of grinding wheel.
It is possible thereby to effectively realize thinned effect.Furthermore it is preferred that using granularity for 0.5-1 μm μm of grinding wheel, (grinding wheel mesh number is
6000-10000).The grinding wheel smaller using diamond partial size as a result, can make the damaging layer ratio on semiconductor crystal wafer surface
Smaller, damaging layer is preferred less than 1 μm.
According to a particular embodiment of the invention, further, the feed speed for controlling above-mentioned grinding wheel is the micro- meter per second of 0.1-1.
It is possible thereby to preferably control semiconductor crystal wafer pattern and reduce semiconductor crystal wafer surface damage layer.The feed speed is simultaneously
It will not influence the concaveconvex shape of silicon wafer, only will affect the roughness and damaging layer of silicon chip surface.It is preferred that feed speed 0.1-0.5 is micro-
Meter per second is advisable.If feed speed is too fast, it is difficult to be thinned.
According to a particular embodiment of the invention, in addition, it is necessary to which the revolving speed for controlling above-mentioned grinding wheel is 1000-3000rpm, and
The revolving speed of workbench is between 100-300rpm.This has no effect on the concaveconvex shape of silicon chip surface, only will affect wafer thinning
Rate.If too fast, grinding wheel is easy to collapse scarce.
In general, semiconductor crystal wafer surface can be made to form central depths if do not corrected completely in polishing process
About 3-5 μm of concave surface.And the thinning single surface method and technological parameter of the above embodiment of the present invention are used, just it can obtain
Heart height is 3-5 μm of convex surface, and then can effectively offset and not correct about 3-5 μm of depth of the concave surface that polishing generates.Thus originally
Invention not only can effectively save subsequent polishing treatment by carrying out thinning single surface processing to semiconductor crystal wafer surface in advance
The step of correcting polishing pad in the process, significantly improves the service life of polishing pad, but also can significantly improve polishing treatment effect
Rate reduces polishing treatment operation difficulty.The flatness on semiconductor crystal wafer surface can also be most importantly significantly improved, is reduced
Thickness deviation improves multiple-piece single-sided polishing technique level of processing, meets the requirement of integrated circuit line width.
In addition, in the method for the above embodiment of the present invention in order to enable semiconductor crystal wafer front formed be suitable for it is convex
Face needs to comprehensively consider A, B two o'clock on the workbench of thinning single surface machine with respect to the position of the plane of reference, the type that machine is thinned, grinding wheel
Granularity, feeding decrease speed, grinding wheel speed and rotating speed of table.And by by the Numerical Control of above-mentioned each parameter in the present invention
In the numberical range that above-described embodiment uses, the convex surface that centre-height is 3-5 μm can be efficiently and accurately obtained, and this is convex
The surface damage layer in face is lower than 0.2 μm.It is possible thereby to reduce or save amendment polishing during effectively canceling out polishing treatment
Pad the concave surface formed.And then obtain the semiconductor wafer of total thickness deviation (TTV) less than 1 μm.
According to a particular embodiment of the invention, finally to above-mentioned two tables of semiconductor crystal wafer handled by thinning single surface
Face successively carries out rough polishing processing, middle throwing processing and smart throwing processing, to obtain semiconductor wafer.
According to a particular embodiment of the invention, rough polishing processing, middle throwing processing and smart throwing processing are carried out to semiconductor crystal wafer
In the process, polishing pad times of revision can be suitably reduced, or can be with the completely left out amendment process to polishing pad.Utilize reduction
Polishing pad times of revision saves the above-mentioned single side of concave surface counteracting that polishing pad amendment process is formed on semiconductor crystal wafer surface
The convex surface that reduction processing is formed on semiconductor crystal wafer surface.And then obtain the semiconductor wafer that flatness is high, thickness deviation is low.
According to a particular embodiment of the invention, rough polishing processing, middle throwing processing and smart throwing processing are carried out to semiconductor crystal wafer
The technological parameter used is existing parameter.It, can be according to semiconductor crystal wafer table in the polishing process of above-mentioned three step
The height on the convex surface formed on face suitably reduces polishing pad times of revision or completely left out polishing pad amendment process.
According to a particular embodiment of the invention, in the processing of above-mentioned rough polishing using NITTAHASS SUBA rough polishing pad,
NITTHASS rough polishing liquid；Using throwing pad and middle throwing liquid in NITTAHASS in middle throwing processing；Fujimi3950 is used in smart throwing processing
Fine polishing liquid and ssw1 essence throw pad；Polissoir uses revasum monolithic polissoir.
As a result, using the method for the control semiconductor crystal wafer surface topography of the above embodiment of the present invention, can precisely control
Semiconductor wafer damaging layer, nanotopography and surface topography processed.Specifically, for the silicon wafer of 200mm, in polishing treatment
Before make semiconductor crystal wafer surface formed convex.After the completion of single side monolithic (SSP) polishing, silicon wafer will become concave,
Convex before polishing can be offset, does not correct polishing pad purpose to reach.The amendment for omitting polishing pad, so that extending polishing pad makes
Use the service life.In addition, the above method can effectively reduce the damaging layer on semiconductor crystal wafer surface, such as to can control damaging layer small
In 1 μm, semiconductor crystal wafer polishing time is reduced, improves polishing efficiency.
According to the second aspect of the invention, the invention also provides semiconductor wafers, according to an embodiment of the invention, described
Semiconductor wafer handles to obtain using method described in preceding embodiment.Thus the semiconductor wafer has flatness height, thickness
Deviation is small, can satisfy the requirement of integrated circuit line width.
In addition, the method and utilization this method of the control semiconductor crystal wafer surface topography of the above embodiment of the present invention obtain
Semiconductor wafer further have the advantage that
(1) this method can be precisely controlled the damaging layer of semiconductor wafer, nanotopography, surface topography (bumps), especially
It is suitble to the semiconductor wafers of 200mm and 300mm.
(2) reach and do not correct polishing pad purpose, improve polishing efficiency.
(3) for 200mm silicon wafer, multiple-piece single-sided polishing, such as Fujikoshi SPM-23 board, SPEED
The series of FAM 50/59, to the thickness deviation of Silicon Wafer < 0.3-0.5 μm, surfacing.Control flatness, the thickness of silicon chip surface
Deviation improves multiple-piece single-sided polishing technique level of processing, meets the requirement of integrated circuit line width.
(4) damaging layer of silicon chip surface is reduced between 3-10 μm, reduces the silicon wafer polishing time, improves polishing effect
Rate.
Embodiment
(1) thinning single surface process mechanism:
It is mounted in spindle shaft and vertical grinding wheel, grinding wheel can contact semiconductor crystal wafer A, B, C tri- up and down
Point, wherein A, C two o'clock are semiconductor crystal wafer edge, and B point is the central point (See Figure 1) of semiconductor crystal wafer.Semiconductor die
The back side of disk has vacuum tables to adsorb.When grinding wheel vertically declines spindle rotation grinding wheel simultaneously, in semiconductor crystal wafer
Surface contact.When grinding wheel and semiconductor crystal wafer surface contact, semiconductor wafer is rotated around central shaft, it is ensured that can be uniform
Thinned semiconductor wafer surface.
The principle of control semiconductor wafer surface pattern is thinned:
1) board is thinned and has a turntable substantially, turntable generally has 2-3 workbench, matched to have 1-2spindle
Axis has thinned grinding wheel on each spindle axis.
2) levelness of ordinary circumstance lower table (Fig. 1) is as follows:
Taking a virtual plane is the plane of reference
A point: 0 μm
B point: -11 ± 2 μm
C point: -20 ± 2 μm
3) pattern of thinned rear semiconductor crystal wafer can be adjusted by adjusting the levelness of A, B, C point on workbench,
Several patterns as shown in Fig. 2 can specifically be obtained.
The purpose of the present invention is by adjusting A, B, C point position, so that the surface of wafer forms centre after being thinned
The low convex surface pattern of high rim, as shown in Fig. 2 (2).
(2) thinning single surface processing is carried out to the front of semiconductor crystal wafer.
Thinning single surface processing is carried out below for the semiconductor wafer of 200mm, specifically process conditions are as follows:
1, the serial thinning single surface machine of DISCO 8；
2, the position of A point is -2 μm on workbench, and the position of B point is -8 μm；(still selecting virtual plane for the plane of reference)
3, grinding wheel graininess is 0.8 μm (6000 mesh emery wheel)；
4, grinding wheel feeding is carried out in two steps, decrease speed are as follows: first step decrease speed is 0.3 micro- meter per second, second step decline
Speed is 0.1 micro- meter per second；
5, grinding wheel speed 3000rpm；
6, rotating speed of table 150rpm, (workbench adsorbs semiconductor crystal wafer)；
7, cooling processing.
After being handled by above-mentioned thinning single surface, the front of semiconductor wafer forms convex surface.
(3) rough polishing processing, middle throwing processing and smart throwing processing
The middle throwing of rough polishing-- essence throwing is carried out in the semiconductor crystal wafer that surface forms convex surface to above-mentioned handle by thinning single surface.
1) rough polishing treatment process is as follows:
Polishing pad is by pretreatment (warming, hairbrush cleaning etc.), without amendment (skive condition
dress)
| Rough polishing | ||||
| Step | 1 | 2 | 3 | 4 |
| Time (second) | 3 | 0 | 250 | 15 |
| Pressure (PSI) | 0 | 0 | 50 | 0 |
| Pure water (milliliter) | 2000 | 0 | 0 | 200 |
| Chemical liquids 1 (milliliter) | 0 | 0 | 0 | 800 |
| Polishing fluid 1 (milliliter) | 100 | 0 | 100 | 0 |
| Chemical liquids 2 (milliliter) | 0 | 0 | 115 | 0 |
| Polishing fluid 2 (milliliter) | 0 | 0 | 0 | 0 |
| Price fixing revolving speed (rpm) | 90 | 90 | 150 | 90 |
2) it is as follows that technique is thrown in；Polishing pad is by pretreatment (warming, hairbrush cleaning etc.), without amendment (diamond
Grinding wheel condition dress)
| Middle throwing | ||||
| Step | 1 | 2 | 3 | 4 |
| Time (second) | 3 | 0 | 220 | 15 |
| Pressure (PSI) | 0 | 0 | 40 | 0 |
| Pure water (milliliter) | 2000 | 0 | 0 | 200 |
| Chemical liquids 1 (milliliter) | 0 | 0 | 0 | 800 |
| Polishing fluid 1 (milliliter) | 100 | 0 | 100 | 0 |
| Chemical liquids 2 (milliliter) | 0 | 0 | 115 | 0 |
| Polishing fluid 2 (milliliter) | 0 | 0 | 0 | 0 |
| Price fixing revolving speed (rpm) | 90 | 90 | 120 | 90 |
3) essence throws technique:
| Essence is thrown | ||||
| Step | 1 | 2 | 3 | 4 |
| Time (second) | 3 | 0 | 220 | 15 |
| Pressure (PSI) | 0 | 0 | 40 | 0 |
| Pure water (milliliter) | 2000 | 0 | 0 | 200 |
| Chemical liquids 1 (milliliter) | 0 | 0 | 0 | 800 |
| Polishing fluid 1 (milliliter) | 0 | 0 | 0 | 0 |
| Chemical liquids 2 (milliliter) | 0 | 0 | 0 | |
| Polishing fluid 2 (milliliter) | 200 | 0 | 150 | 0 |
| Price fixing revolving speed (rpm) | 90 | 90 | 120 | 90 |
(4) result:
1) semiconductor crystal wafer surface to step (2) after reduction processing carry out ADE test cross section and
The test of wafer surface damage layer depth, is as a result shown in Fig. 3 and Fig. 4.
2) a series of pattern of the semiconductor wafer obtained after polishing treatments to step (4) is tested, and is as a result seen
Fig. 5-7.
(5) conclusion:
1) as shown in figure 3, the centre-height that semiconductor crystal wafer surface forms convex surface is 4-5 μm.As shown in figure 4, partly leading
The surface damage layer of body chip is lower than 0.2 μm.
2) Fig. 5 is the outside drawing of semiconductor crystal wafer (similar 3D schemes)；Fig. 6 be diametrically on thickness change
Figure；Fig. 7 is that semiconductor crystal wafer is divided into a lot of small pieces, the change value of thickness in every piece of area.It is found that semiconductor from Fig. 6
Wafer thickness change is 0.30 μm, illustrates that flatness is fine；From figure 7 it can be seen that the change value of thickness in every piece of area
It is very small, further illustrate that flatness is fine.As a result, by Fig. 5-7 it can be proved that using the embodiment of the present invention method, energy
Enough it is effectively improved the flatness of semiconductor crystal wafer.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
It can be combined in any suitable manner in a or multiple embodiment or examples.In addition, without conflicting with each other, the technology of this field
The feature of different embodiments or examples described in this specification and different embodiments or examples can be combined by personnel
And combination.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (9)
1. a kind of method for controlling semiconductor crystal wafer surface topography characterized by comprising
Thinning single surface processing is carried out to the front of semiconductor crystal wafer, to form the front by center to edge gradually
Thinning convex surface；
Rough polishing processing, middle throwing processing and essence are successively carried out to two surfaces of semiconductor crystal wafer by thinning single surface processing
Throwing processing, to obtain semiconductor wafer.
2. the method according to claim 1, wherein the work for the thinning single surface machine that thinning single surface processing uses
Make A point on platform and is set to -1 μm~-10 μm, preferably -1~-3 μm；B point is set to -1 μm~-10 μm preferably -7~-9 μm.
3. according to the method described in claim 2, it is characterized in that, thinning single surface processing uses granularity for 0.5-4 μm
Grinding wheel, it is preferred to use the grinding wheel that granularity is 0.5-1 μm.
4. according to the method described in claim 3, it is characterized in that, the micro- meter per second of the grinding wheel feed speed 0.1-1.
5. according to the method described in claim 4, it is characterized in that, the revolving speed of the grinding wheel is 1000-3000rpm.
6. according to the method described in claim 5, it is characterized in that, the revolving speed of the workbench is between 100-300rpm.
7. according to the method described in claim 6, it is characterized in that, the centre-height on the convex surface is 3-5 μm.
8. the method according to the description of claim 7 is characterized in that the total thickness deviation of the semiconductor wafer is less than 1 μm.
9. a kind of semiconductor wafer, which is characterized in that the semiconductor wafer uses the described in any item methods of claim 1-8
Processing obtains.
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