CN101791779A

CN101791779A - Semiconductor silicon wafer manufacture process

Info

Publication number: CN101791779A
Application number: CN 200910241461
Authority: CN
Inventors: 库黎明; 闫志瑞; 索思卓; 陈海滨; 盛方毓
Original assignee: Beijing General Research Institute for Non Ferrous Metals; Grinm Semiconductor Materials Co Ltd
Current assignee: Beijing General Research Institute for Non Ferrous Metals; Grinm Semiconductor Materials Co Ltd
Priority date: 2009-12-03
Filing date: 2009-12-03
Publication date: 2010-08-04

Abstract

The invention discloses a semiconductor silicon wafer manufacture process which comprises the steps of: 1, carrying out double-side rough polishing on the silicon wafer after grinding and corroding, wherein the removal amount is 5-100 micrometers; 2, after double-side rough polishing, carrying out double-side medium polishing, wherein the hardness of polishing cloth or the grain size of grains of a polishing solution is less than that of the rough polishing, and the polishing removal amount is 1-100 micrometers; and 3, directly carrying out single-face final polishing on the silicon wafer subjected to the double-sidepolishing, wherein the polishing removal amount is less than 0.5 micrometer. The silicon wafer with high planeness can be obtained by the process, and the once yield of the product is improved. The invention has the advantage of providing a manufacture method of the large-size silicon wafer for improving the geometric parameter level of the silicon wafer surface.

Description

Semiconductor silicon wafer manufacture process

Technical field

The present invention relates to a kind of semiconductor silicon wafer manufacture process, the large-diameter silicon wafer manufacturing process after especially a kind of the improvement is come the machine silicon polished silicon wafer, improves a kind of process of the geometric parameter level on silicon polished surface, processing back.

Background technology

With the 300mm silicon chip is that the chip live width of base material develops into 65nm and 32nm by 90nm, and constantly diminishing of live width proposed more and more higher requirement to silicon chip producer, as at geometric parameter, particle, metal and nanotopography.This requires silicon chip producer constantly to optimize processing technology, thinks deeply the various aspects the silicon chip working process from the aspect of microcosmic more.

Although 90nm and 65nm or littler live width technology mainly all are on geometric parameter, particle parameter and the nanotopography that is embodied in silicon chip surface to the requirement of technique for processing silicon chip, as GBIR, SFQR, particle and nanotopography (Nanotopography), but reducing the requirement of technique for processing silicon chip of live width is strict more.In order to reach these requirements, the processing method of 300mm silicon chip will be different from the processing method of 90nm and above live width to a great extent, improves its geometric parameter as introducing monolithic grinding, raising twin polishing and smart methods such as equipment precision of throwing.

The 300mm silicon wafer polishing all adopts twin polishing, in the twin polishing process up and down two deep bids, sun gear and edge gear can move independently, silicon chip freely is suspended in the middle of the deep bid, can improve the geometric parameter on surface so widely.Carry out edge polishing and last precise polished after the twin polishing, the final polishing of silicon chip is generally two step single-sided polishings, middle throwing and smart the throwing.Middle effect of throwing is to remove the mechanical damage that twin polishing is not removed, and the big words of middle throwing removal amount can be destroyed geometric parameter.In order to overcome this problem, the general way that reduces removal amount that adopts reduces destructiveness, simultaneously, a lot of equipment producers carry out a large amount of research to the fixing head of silicon chip, reduce the degree that geometric parameter worsens by various ways, for example segmentation and regionalization comes the temperature of controlled pressure head ceramic wafer, thereby reaches the shape of control ceramic wafer, change the stressed distribution of silicon chip, the geometric parameter that makes silicon chip surface to negative tendency of changes in zero.But the temperature of controlled pressure head ceramic wafer reaches and stops the deterioration of silicon chip geometric parameter to require the non-normal manner of control accuracy, is subjected to all multifactor influences.

Therefore, in order to solve the problem of the geometric parameter variation that single-sided polishing brought of large-sized silicon wafers after the twin polishing, must provide a kind of improved semiconductor silicon wafer manufacture process

Summary of the invention

The purpose of this invention is to provide a kind of semiconductor silicon wafer manufacture process.This technology is removed the surperficial mechanical harm layer after the corrosion of mill slake, has avoided the problem of the excessive geometric parameter variation that causes of single-sided polishing removal amount.Strong assurance the machining accuracy of product.

In order to realize above-mentioned purpose, the present invention adopts following technical scheme:

This semiconductor silicon wafer manufacture process, this technology comprises the steps:

(1) silicon chip after grinding or the corrosion is slightly thrown with Twp-sided polishing machine;

(2) silicon chip is carried out throwing in the twin polishing;

(3) silicon chip being carried out single face finally polishes;

In process step of the present invention (1), the silicon chip after grinding or the corrosion slightly to be thrown with Twp-sided polishing machine, it is higher bigger with removal amount to remove speed in the polishing process, and purpose is tentatively to reduce the mechanical damage layer thickness that abrasive machine processing brings;

In process step of the present invention (1), the polishing removal amount is that removal amount is 5～100 microns;

In process step of the present invention (2), polishing cloth hardness that two-sided middle throwing is used or polishing fluid particle diameter are less than two-sided thick throwing, and the polishing removal amount is 1～100 micron;

In a word, in process step of the present invention (1) and (2),, obtain the silicon chip surface of high-flatness, help next step final single-sided polishing by two step twin polishing technologies;

In process step of the present invention (3), the processing removal amount of the final polishing of single face is less than 0.5 micron, and purpose is to make the microroughness of silicon chip surface reach requirement;

In process of the present invention, edge polishing can be placed on before two-sided middle the throwing, and after throwing in also can being placed on, the edge that the protection throwing is good is not destroyed by circle in the pleasure boat sheet of twin polishing process;

In process of the present invention, cleaning of inserting after per step processing technology and drying process purpose are the polishing fluids that remains in silicon chip surface after the removal polishing.

Advantage of the present invention is, can improve the geometric parameter level of silicon chip surface, produces the large-diameter silicon wafer of high-flatness.Measure the AFS3220 that surperficial geometric parameter uses ADE Co. to produce.

The present invention processes at large-diameter silicon wafer, particularly avoids single-sided polishing very practical to the destruction aspect of geometric parameter.The present invention can be used in any large-diameter silicon wafer processing technology of coml.

Description of drawings

Polishing process flow chart in the present silicon chip manufacturing process of Fig. 1.

Fig. 2 semiconductor silicon wafer manufacture process figure provided by the invention.

Fig. 3 uses the geometric parameter (surface thickness variation) of silicon chip surface after the step twin polishing.

Fig. 4 uses the geometric parameter (surface thickness variation) of silicon chip surface after the technology of the present invention.

Among Fig. 2,1 is the grinding corrosion, and 2 be two-sided thick throwing, and 3 be to throw in two-sided, and 4 be edge polishing, and 5 be last polishing (first step is smart throws), 6 be last polishing (the essence throwing of second step) 7, is cleaning-drying that 8 is detection.

The specific embodiment

Embodiment 1

Use P (100) that vertical pulling method produces 12 inches silicon polished 30, on conventional caustic corrosion machine, corrode, remove 20 microns, polish at SPEEDFAM 20B Twp-sided polishing machine the corrosion back, and polishing cloth is SUBA800, hardness is 82 (Asker), 20 microns of polishing removal amounts change polishing cloth into SUBA600 then, and hardness is 61,15 that get after the two-sided thick throwing are polished, and the polishing removal amount is 10 microns.Carry out essence at last and throw, the polishing cloth that the deep bid in two steps uses is 7355 of the production of CHIYODA company, and removal amount is 0.3 micron.Cleaning-drying after per step polishing, thickness measuring equipment is ADE AFS3220.The GBIR that 15 final silicon chips are every as shown in Figure 3.From the figure as can be seen GBIR (total thickness variations) all less than 0.45 micron,

Embodiment 2

Getting remaining 15 finally polishes.The final polishing in two steps, a step throws in the single face, and the polishing cloth that middle throwing is used is SUBA400, and final step is smart the throwing, and always removal amount is 0.8 micron.The GBIR that these 15 silicon chips are every is between 0.35～0.5um, as shown in Figure 4.

These two groups of test cards understand that going on foot twin polishings with two has overcome the problem of throwing the geometric parameter deterioration that is brought in the single face, can satisfy the required precision that large-diameter silicon wafer is made.

Claims

1. semiconductor silicon wafer manufacture process, it comprises section, chamfering, grinding, polishing, it is characterized in that: described polishing process comprises the steps:

(2) silicon chip is carried out throwing in the twin polishing;

(3) silicon chip is carried out single face and finally polish, finally be finished to smart throwing of a step, or smart in two steps the throwing.

2. according to claims 1 described semiconductor silicon wafer manufacture process, it is characterized in that: the removal amount of described two-sided thick throwing is that removal amount is 5～100 microns;

3. according to claims 1 described semiconductor silicon wafer manufacture process, it is characterized in that: polishing cloth hardness of throwing in described or polishing fluid grain diameter are less than two-sided thick throwing.

4. according to claims 3 described semiconductor silicon wafer manufacture process, it is characterized in that: the polishing removal amount of throwing in two-sided is that removal amount is 1～100 micron;

5. according to claims 1 described semiconductor silicon wafer manufacture process, it is characterized in that: described silicon chip is carried out the removal amount of the final polishing of single face less than 0.5 micron.

6. according to claims 1 described semiconductor silicon wafer manufacture process, it is characterized in that: carry out edge polishing before in two-sided, throwing or edge polishing after middle throwing.

7. according to claims 1 described semiconductor silicon wafer manufacture process, it is characterized in that: can insert after per step processing technology and clean and drying process.