CN112059736A - Silicon wafer manufacturing process - Google Patents
Silicon wafer manufacturing process Download PDFInfo
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- CN112059736A CN112059736A CN202010938546.7A CN202010938546A CN112059736A CN 112059736 A CN112059736 A CN 112059736A CN 202010938546 A CN202010938546 A CN 202010938546A CN 112059736 A CN112059736 A CN 112059736A
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- silicon wafer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B08—CLEANING
- B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
- B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
- B08B3/04—Cleaning involving contact with liquid
- B08B3/08—Cleaning involving contact with liquid the liquid having chemical or dissolving effect
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- Chemical Kinetics & Catalysis (AREA)
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- Cleaning Or Drying Semiconductors (AREA)
Abstract
The invention discloses a silicon wafer manufacturing process. The process comprises the following steps: (1) polishing the silicon wafer after grinding and etching; (2) pre-cleaning the silicon wafer after polishing the silicon wafer, and removing abrasive residues on the surface of the silicon wafer; (3) annealing the silicon wafer at low temperature; (4) and (4) finally cleaning the low-temperature annealed silicon wafer, removing the surface metal residues in the step (3), and finally detecting the metal level. According to the silicon wafer manufacturing process, the silicon wafer is annealed at a low temperature by using the annealing furnace before final cleaning, so that metal in the silicon wafer is diffused to the surface, and then is removed by the final cleaning process. The silicon wafer processed by the process can effectively reduce the metal contamination level on the surface of the silicon wafer, particularly, the metal level on the surface is kept stable along with the time extension, and the qualification rate of silicon single crystals is improved.
Description
Technical Field
The invention relates to a silicon wafer manufacturing process, in particular to a silicon wafer manufacturing process for obtaining low metal contamination level.
Background
Semiconductor wafers are the primary substrate material for modern very large scale integrated circuits and are typically manufactured by the processes of crystal pulling, slicing, chamfering, grinding (including grinding and lapping), etching, polishing, cleaning, and inspection. The key parameters affecting the quality of the silicon wafer are mainly geometric parameters, surface particles and surface metal contamination levels, wherein the surface metal contamination levels are influenced by a plurality of factors, such as the level of a cleaning machine, the purity of chemical liquid, a cleaning process, personnel operation and environmental conditions.
In the process of processing the silicon wafer, the surface of the silicon wafer needs to be cleaned in each procedure, and abrasive residues and metal contamination left by the previous processing technology are removed. The current processing generally adopts the processes of polishing, pre-cleaning, geometric parameter testing, final cleaning and particle metal testing, and the final cleaning is carried out after the geometric parameter testing, so that the particles and metal contamination can be removed before leaving the factory in the testing process of the silicon wafer, and the metal contamination is generally controlled at 1E10atom/cm2The level of (c). In the actual production process, the metal test before leaving the factory is in the required range, but after standing for a period of time, the surface metal can be increased and even can exceed the specification requirement, and the main reason is that the metal with more active metals such as copper, nickel and the like can migrate to the surface of the silicon wafer in the standing process, so that the metal contamination level is increased.
Disclosure of Invention
The invention aims to provide a silicon wafer manufacturing process, which utilizes the improved large-diameter silicon wafer manufacturing process to process a silicon polished wafer, can reduce metal contamination on the surface of the silicon wafer and can obtain the silicon wafer with low metal contamination level.
In order to realize the purpose, the following technical scheme is adopted:
a silicon wafer fabrication process, the process comprising the steps of:
(1) polishing the silicon wafer after grinding and etching;
(2) pre-cleaning the silicon wafer after polishing the silicon wafer, and removing abrasive residues on the surface of the silicon wafer;
(3) annealing the silicon wafer at low temperature;
(4) and (4) finally cleaning the low-temperature annealed silicon wafer, removing the surface metal residues in the step (3), and finally detecting the metal level.
In the step (1), the ground silicon wafer is polished, a small-sized silicon wafer (for example, 4 to 6 inches) may be processed by single-side polishing, and a large-sized silicon wafer (for example, 8 to 18 inches) may be polished by double-side polishing and final polishing.
In the step (1), the polishing process uses a conventional polishing process; the removal amount is 15-100 microns.
In the step (1), the silicon wafer may be edge-polished before or after polishing. The edge polishing can be placed before or after the surface polishing depending on the process requirements.
In the step (2), the pre-cleaning adopts a traditional cleaning mode of a first cleaning solution, a second cleaning solution and the like to remove the abrasive residues on the surface, and the surface has no corrosion and no other uneven conditions.
In the step (3), the silicon wafer is annealed at low temperature of 150-600 ℃ for 30 minutes-12 hours. When the annealing temperature is lower than 150 ℃ or the annealing time is less than 30 minutes, metal in the silicon wafer body cannot diffuse to the surface, and when the annealing temperature is higher than 600 ℃ or the annealing time exceeds 12 hours, metal on the surface can diffuse into the silicon wafer body to contaminate the silicon wafer.
In the step (3), the silicon wafer may be subjected to low-temperature annealing using a vertical annealing furnace or a horizontal annealing furnace.
In the step (3), when the silicon wafer is annealed at a low temperature, protective gas such as nitrogen, argon or helium can be introduced into the annealing cavity according to the process requirements.
The invention has the advantages that:
according to the silicon wafer manufacturing process, the silicon wafer is annealed at a low temperature by using the annealing furnace before final cleaning, so that metal in the silicon wafer is diffused to the surface, and then is removed by the final cleaning process. The silicon wafer processed by the process can effectively reduce the metal contamination level on the surface of the silicon wafer, particularly, the metal level on the surface is kept stable along with the time extension, and the qualification rate of silicon single crystals is improved.
The invention is very practical in silicon wafer processing, especially in the manufacture of high-level silicon wafer products. The invention can be used in any commercial silicon wafer processing technology.
Drawings
FIG. 1 is a flow chart of a currently used silicon wafer processing process.
FIG. 2 is a flow chart of a silicon wafer processing process used in the present invention.
FIG. 3 is data of surface metal Cu levels over time after cleaning in example 1.
FIG. 4 is data of surface metal Cu levels over time after cleaning in example 2.
Detailed Description
As shown in fig. 1, the process flow diagram of the currently adopted silicon wafer processing sequentially includes polishing, pre-cleaning, geometric parameter detection, final cleaning, metal level detection, and packaging.
As shown in fig. 2, the silicon wafer processing process flow chart used in the present invention sequentially includes the steps of polishing, pre-cleaning, geometric parameter detection, low temperature annealing, final cleaning, metal level detection, packaging, and the like. According to the silicon wafer manufacturing process, the silicon wafer is annealed at a low temperature by using the annealing furnace before final cleaning, so that metal in the silicon wafer is diffused to the surface, and then is removed by the final cleaning process.
The metal on the surface of the silicon wafer can be measured by using a series of devices such as ICP-MS 8800 and the like produced by Agilent.
Example 1
P (100) produced by the Czochralski method, 15 pieces of 12-inch silicon grinding sheet with resistivity of 1-100 omega cm and thickness of about 800 microns are used, and the silicon wafer processing is carried out by adopting the process flow shown in figure 1. Polishing was first performed on a double-side polisher and a final polisher with a polish removal of 20 microns. Cleaning with pre-cleaning machine and final cleaning machine directly after polishing, wherein the cleaning process adopts hydrofluoric acid (HF: H)2O1: 100), first liquid (NH)4OH∶H2O2∶H2O1: 2: 20), second liquid (HCl: H)2O2∶H2O1: 2: 20) and IPA drying process, 3 pieces of silicon wafers are extracted after cleaning and tested for metal level using ICP-MS 7900 from agilent corporation.
Table 1 surface metal level data after cleaning
As can be seen from Table 1, the contents of metallic Cu are all less than 5E9 atom/cm2The level of (c).
And taking the rest 12 silicon wafers, putting the silicon wafers into 6 cleaned FOSB in a first-stage clean room, carrying out internal and external packaging, and placing the FOSB in the clean room. And taking out one piece of the box every 24 hours to carry out a metal Cu test on the silicon wafer, wherein the test result of Cu is shown in figure 3. As can be seen from FIG. 3, the metal Cu level on the wafer surface increased with the increase of the standing time and finally stabilized at a constant level.
Example 2
The same 12 silicon wafers as in example 1 were processed by using the silicon wafer processing flow chart used in the present invention shown in FIG. 2. The operations of the steps of pre-cleaning, geometric parameter detection, final cleaning, metal level detection and the like are the same as those in embodiment 1, and the difference is that: and (3) annealing the silicon wafer at low temperature by using an annealing furnace before final cleaning, wherein the annealing temperature is 250 ℃, the annealing time is 2 hours, and nitrogen is introduced into an annealing cavity.
After the low-temperature treatment, the mixture is finally cleaned, is arranged in 6 cleaned FOSB in a first-stage clean room, is internally and externally packaged and is placed in the clean room. And taking out one piece of the box every 24 hours to carry out a metal Cu test on the silicon wafer, wherein the test result of Cu is shown in a figure 4. As can be seen from the figure, the metal Cu level on the surface of the silicon wafer is basically unchanged along with the prolonging of the standing time.
Therefore, the invention can reduce the surface metal level rise caused by metal contamination in the body through the improved manufacturing method, thereby manufacturing the silicon chip product with low metal contamination level.
Claims (7)
1. A silicon wafer manufacturing process is characterized by comprising the following steps:
(1) polishing the silicon wafer after grinding and etching;
(2) pre-cleaning the silicon wafer after polishing the silicon wafer, and removing abrasive residues on the surface of the silicon wafer;
(3) annealing the silicon wafer at low temperature;
(4) and (4) finally cleaning the low-temperature annealed silicon wafer, removing the surface metal residues in the step (3), and finally detecting the metal level.
2. The silicon wafer manufacturing process according to claim 1, wherein in the step (1), the ground silicon wafer is polished by a single-side polishing process or a double-side polishing plus final polishing process.
3. The silicon wafer manufacturing process according to claim 1, wherein in the step (1), the removal amount by polishing is 15 to 100 μm.
4. The silicon wafer manufacturing process according to claim 1, wherein in the step (1), the silicon wafer is edge-polished before or after polishing.
5. The process for manufacturing a silicon wafer according to claim 1, wherein in the step (3), the silicon wafer is annealed at a low temperature of 150 ℃ to 600 ℃ for 30 minutes to 12 hours.
6. The silicon wafer manufacturing process according to claim 1, wherein in the step (3), the silicon wafer is subjected to low-temperature annealing using a vertical annealing furnace or a horizontal annealing furnace.
7. The silicon wafer manufacturing process according to claim 1, wherein in the step (3), when the silicon wafer is subjected to low-temperature annealing, nitrogen, argon or helium is introduced into the annealing cavity as a protective gas according to process requirements.
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Citations (8)
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US6100167A (en) * | 1997-05-29 | 2000-08-08 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron doped silicon wafers |
US20030104680A1 (en) * | 2001-11-13 | 2003-06-05 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron-doped silicon wafers |
CN101656193A (en) * | 2008-08-21 | 2010-02-24 | 北京有色金属研究总院 | Technique for processing silicon chip |
CN101791779A (en) * | 2009-12-03 | 2010-08-04 | 北京有色金属研究总院 | Semiconductor silicon wafer manufacture process |
CN102403251A (en) * | 2011-11-30 | 2012-04-04 | 合肥晶澳太阳能科技有限公司 | Prewashing solution of crystal silicon wafer and prewashing technology thereof |
CN102528597A (en) * | 2010-12-08 | 2012-07-04 | 有研半导体材料股份有限公司 | Manufacturing process of large-diameter silicon wafer |
CN105576094A (en) * | 2014-10-16 | 2016-05-11 | 江苏凯旋涂装自动化工程有限公司 | LED epitaxial wafer processing technology |
CN109935528A (en) * | 2017-12-15 | 2019-06-25 | 有研半导体材料有限公司 | A kind of silicon chip surface processing method |
-
2020
- 2020-09-08 CN CN202010938546.7A patent/CN112059736A/en active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100167A (en) * | 1997-05-29 | 2000-08-08 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron doped silicon wafers |
US20030104680A1 (en) * | 2001-11-13 | 2003-06-05 | Memc Electronic Materials, Inc. | Process for the removal of copper from polished boron-doped silicon wafers |
CN101656193A (en) * | 2008-08-21 | 2010-02-24 | 北京有色金属研究总院 | Technique for processing silicon chip |
CN101791779A (en) * | 2009-12-03 | 2010-08-04 | 北京有色金属研究总院 | Semiconductor silicon wafer manufacture process |
CN102528597A (en) * | 2010-12-08 | 2012-07-04 | 有研半导体材料股份有限公司 | Manufacturing process of large-diameter silicon wafer |
CN102403251A (en) * | 2011-11-30 | 2012-04-04 | 合肥晶澳太阳能科技有限公司 | Prewashing solution of crystal silicon wafer and prewashing technology thereof |
CN105576094A (en) * | 2014-10-16 | 2016-05-11 | 江苏凯旋涂装自动化工程有限公司 | LED epitaxial wafer processing technology |
CN109935528A (en) * | 2017-12-15 | 2019-06-25 | 有研半导体材料有限公司 | A kind of silicon chip surface processing method |
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Address after: 101300 south side of Shuanghe Road, Linhe Industrial Development Zone, Shunyi District, Beijing Applicant after: Youyan semiconductor silicon materials Co.,Ltd. Address before: 101300 south side of Shuanghe Road, Linhe Industrial Development Zone, Shunyi District, Beijing Applicant before: GRINM SEMICONDUCTOR MATERIALS Co.,Ltd. |
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