JPH0319688B2 - - Google Patents
Info
- Publication number
- JPH0319688B2 JPH0319688B2 JP9927082A JP9927082A JPH0319688B2 JP H0319688 B2 JPH0319688 B2 JP H0319688B2 JP 9927082 A JP9927082 A JP 9927082A JP 9927082 A JP9927082 A JP 9927082A JP H0319688 B2 JPH0319688 B2 JP H0319688B2
- Authority
- JP
- Japan
- Prior art keywords
- mirror
- bsd
- wafer
- hold time
- surface layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010438 heat treatment Methods 0.000 claims description 16
- 239000002344 surface layer Substances 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 25
- 238000000034 method Methods 0.000 description 10
- 238000002474 experimental method Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 4
- 239000006061 abrasive grain Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
本発明は半導体デバイスに使用する鏡面ウエー
ハを製造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing mirrored wafers for use in semiconductor devices.
通常、IC、VLS1用のシリコン基板には鏡面ウ
エーハを使用する。鏡面ウエーハにはシリコン単
結晶棒よりスライス、ラツプ、面取り、エツチン
グ後研摩したシリコン基板とシリコン単結晶棒よ
り、スライス、ラツプ、面取り、エツチングした
シリコン基板がある。 Normally, mirrored wafers are used as silicon substrates for ICs and VLS1. Mirror wafers include silicon substrates that are sliced, lapped, chamfered, and etched from silicon single crystal rods and then polished, and silicon substrates that are sliced, lapped, chamfered, and etched from silicon single crystal rods.
通常のCZ法によるシリコン単結晶は石英ルツ
ボを使用するために酸素を10〜20×1017atoms／
c.c.（ASTM表示）程度含有している。CZ単結晶
より加工した鏡面ウエーハの結晶欠陥（OSF）
は酸素濃度が高い程発生し易い。 Silicon single crystals produced by the normal CZ method use a quartz crucible, so oxygen is added at 10 to 20 × 10 17 atoms/
Contains about cc (ASTM indication). Crystal defects (OSF) in mirror-finished wafers processed from CZ single crystal
The higher the oxygen concentration, the more likely it is to occur.
本出願人が特願昭56−142335に詳細に説明した
ごとく、半導体デバイス後のホールドタイムや良
品率について実験を行い、鏡面ウエーハを1100℃
〜1280℃で１時間以上熱処理後、該鏡面ウエーハ
の表面層を除去することによりMOSメモリーIC
のホールドタイム不良を低下することができた。 As explained in detail by the applicant in Japanese Patent Application No. 142335/1986, we conducted experiments on the hold time and non-defective rate after semiconductor devices, and heated mirror-finished wafers at 1100°C.
After heat treatment at ~1280℃ for more than 1 hour, the surface layer of the mirrored wafer is removed to create a MOS memory IC.
It was possible to reduce hold time defects.
その後、継続してバツクサイドダメージ（以下
BSDという）と熱処理について種々の実験を行
つた結果、CZ単結晶を加工して得た鏡面ウエー
ハに、BSDを付与した後、1100℃〜1200℃で１
時間以上、３〜10％の酸素を含む窒素ガス又は不
活性ガス雰囲気中で熱処理し、該鏡面ウエーハの
BSD加工面と反対面の表面層を鏡面研磨により
除去することで、多大な効果が得られることを見
出した。 After that, continue to do backside damage (below)
As a result of conducting various experiments on heat treatment and heat treatment, we found that after applying BSD to mirror-finished wafers obtained by processing CZ single crystals,
The mirror wafer is heat-treated in a nitrogen gas or inert gas atmosphere containing 3 to 10% oxygen for more than an hour.
We have discovered that a significant effect can be obtained by removing the surface layer on the opposite side to the BSD processed surface by mirror polishing.
即ち、石英ルツボを使用したCZ引上法で得た
半導体シリコン棒より、シリコン基板を製造する
方法において、該半導体シリコン棒をスライスし
てウエーハ化した後、鏡面加工後、このウエーハ
にBSDを付与し、さらに、３％〜10％の酸素を
含む窒素ガス又は不活性ガス雰囲気中で1100℃〜
1200℃で１時間以上熱処理を施し、該鏡面ウエー
ハのBSD加工面の反対側の表面層を鏡面研磨に
より除去することで、多大な効果を得たのであ
る。 That is, in a method for manufacturing a silicon substrate from a semiconductor silicon rod obtained by the CZ pulling method using a quartz crucible, the semiconductor silicon rod is sliced into wafers, and after mirror polishing, BSD is applied to this wafer. Furthermore, at 1100℃~1100℃ in a nitrogen gas or inert gas atmosphere containing 3%~10% oxygen.
A great effect was obtained by performing heat treatment at 1200°C for over 1 hour and removing the surface layer on the opposite side of the BSD processed surface of the mirror wafer by mirror polishing.
以下各実施例について説明する。 Each example will be described below.
実施例 １
酸素濃度14〜18×1017atoms／c.c.（ASTM表
示）を含有するCZ無転位単結晶より、スライス
工程、面取工程、ラツプ工程、エツチング工程を
実施したＰ形（100）７〜10Ω−cm、100φ、525μ
のウエーハに平均粒径10μの砥粒を1.5Kg／cm2の空
気圧で噴射して、BSD加工した。該鏡面ウエー
ハを洗浄後、Arに酸素を５％加えた雰囲気中で
1150℃で６時間熱処理を施し、該鏡面ウエーハを
希弗酸により酸化膜を除き、BSD加工面の反対
面の表面層を鏡面研摩により10〜20μ除去した。Example 1 P-type (100) 7~ which was subjected to slicing process, chamfering process, lapping process, and etching process from CZ dislocation-free single crystal containing oxygen concentration 14~18×10 17 atoms/cc (ASTM display) 10Ω-cm, 100φ, 525μ
A wafer was subjected to BSD processing by injecting abrasive grains with an average particle size of 10μ at an air pressure of 1.5Kg/cm 2 . After cleaning the mirror wafer, it was cleaned in an atmosphere of Ar with 5% oxygen added.
Heat treatment was performed at 1150° C. for 6 hours, the oxide film was removed from the mirror wafer with dilute hydrofluoric acid, and 10 to 20 μm of the surface layer on the opposite side to the BSD processed surface was removed by mirror polishing.
第１図は本実施例による鏡面ウエーハを使つた
MOS型メモリーICデバイスを製作した場合（Ａ
曲線）と、BSDを付与した後、Arのみの雰囲気
中で1150℃６時間熱処理後、表面層を除去した場
合（Ｂ曲線）と、BSDを付与し、熱処理を施さ
ず、表面層を除去した場合（Ｃ曲線）のホールド
タイムの比較を示している。 Figure 1 shows a sample using a mirrored wafer according to this example.
When manufacturing a MOS type memory IC device (A
Curve), BSD applied and then heat treated at 1150°C for 6 hours in an Ar-only atmosphere, and then the surface layer removed (Curve B), and BSD applied and the surface layer removed without heat treatment. A comparison of the hold times in the case (C curve) is shown.
第１図の横軸はホールドタイム（単位ｍｓ）、
縦軸は試料数を示す。第１図からわかる様に、ホ
ールドタイムはＡ曲線の場合がＢ曲線、Ｃ曲線よ
り長く、ホールドタイム不良を顕著に低下するこ
とができた。このことより、BSDを付与して酸
素を５％含む雰囲気中で1150℃６時間熱処理を施
し、10〜20μ表面層を除去することが、ホールド
タイムの向上に重要であることを示している。 The horizontal axis in Figure 1 is the hold time (unit: ms),
The vertical axis shows the number of samples. As can be seen from FIG. 1, the hold time for curve A was longer than for curves B and C, and the hold time failure could be significantly reduced. This shows that applying BSD and performing heat treatment at 1150° C. for 6 hours in an atmosphere containing 5% oxygen to remove a 10-20 μm surface layer is important for improving the hold time.
実施例 ２
Arに酸素を３％加えた雰囲気を用いて、実施
例１と全く同様の実験を実施した。得られたウエ
ーハをMOSメモリーICに加工後、そのホールド
タイムを測定した結果、その向上は実施例１と同
様であり、ホールドタイム不良が顕著に低下し
た。Example 2 An experiment completely similar to Example 1 was carried out using an atmosphere of Ar with 3% oxygen added. After processing the obtained wafer into a MOS memory IC, the hold time was measured. As a result, the improvement was the same as in Example 1, and the hold time failure was significantly reduced.
実施例 ３
Arに酸素を10％加えた雰囲気を用いて、実施
例１と全く同様の実験を実施した。得られたウエ
ーハをMOSメモリーICに加工後、そのホールド
タイムを測定した結果その向上は実施例１と同様
であり、ホールドタイム不良が顕著に低下した。Example 3 An experiment exactly the same as in Example 1 was conducted using an atmosphere of Ar with 10% oxygen added. After processing the obtained wafer into a MOS memory IC, its hold time was measured. As a result, the improvement was the same as in Example 1, and the hold time defects were significantly reduced.
実施例 ４
Arに酸素を２％加えた雰囲気を用いて、実施
例１と全く同様の実験を実施した。得られたウエ
ーハをMOSメモリーICに加工後、そのホールド
タイムを測定したところ、その結果は第１図Ｂ曲
線とほゞ同じであり、その向上はほとんど認めら
れなかつた。Example 4 An experiment exactly the same as in Example 1 was conducted using an atmosphere of Ar with 2% oxygen added. After processing the resulting wafer into a MOS memory IC, the hold time was measured, and the result was almost the same as curve B in Figure 1, with almost no improvement observed.
実施例 ５
Arに酸素を15％加えた雰囲気を用いて、実施
例１と全く同様の実験を実施した。得られたウエ
ーハをMOSメモリーICに加工後、そのホールド
タイムを測定したところ、その結果は第１図Ｃ曲
線とほゝ同じであり、その向上はほとんど認めら
れなかつた。Example 5 An experiment completely similar to Example 1 was carried out using an atmosphere of Ar with 15% oxygen added. After processing the resulting wafer into a MOS memory IC, the hold time was measured, and the result was almost the same as curve C in Figure 1, with almost no improvement observed.
実施例 ６
エツチング工程後、鏡面研摩工程を加え、その
他は実施例１と全く同様の実験を実施した。得ら
れたウエーハをMOSメモリーICに加工後、その
ホールドタイムを測定した結果、その向上は実施
例１と同様であり、ホールドタイム不良が顕著に
低下した。Example 6 After the etching process, a mirror polishing process was added, and otherwise an experiment was carried out in exactly the same manner as in Example 1. After processing the obtained wafer into a MOS memory IC, the hold time was measured. As a result, the improvement was the same as in Example 1, and the hold time failure was significantly reduced.
実施例 ７
実施例１において、エツチング工程後、鏡面研
摩工程を加え、同様なBSD加工、同様な熱処理
を施し、表面層を鏡面研摩により0.5〜5μ除去し
た。得られたウエーハをMOSメモリーICに加工
後、そのホールドタイムを測定した結果、その向
上は実施例１と同様であり、ホールドタイム不良
が顕著に低下した。Example 7 In Example 1, a mirror polishing step was added after the etching step, and similar BSD processing and similar heat treatment were performed to remove 0.5 to 5 μm of the surface layer by mirror polishing. After processing the obtained wafer into a MOS memory IC, the hold time was measured. As a result, the improvement was the same as in Example 1, and the hold time failure was significantly reduced.
実施例 ８
実施例１において、熱処理を施して後、BSD
加工を実施し、表面層を鏡面研摩により0.5〜5μ
除去した。得られたウエーハをMOSメモリーIC
に加工後、そのホールドタイムを測定したとこ
ろ、その結果は第１図Ｃ曲線とほゞ同じであり、
その向上はほとんど認めなれなかつた。Example 8 In Example 1, after heat treatment, BSD
Perform processing and mirror polish the surface layer to 0.5~5μ
Removed. The obtained wafer is made into MOS memory IC.
After processing, the hold time was measured and the result was almost the same as curve C in Figure 1.
The improvement was almost imperceptible.
実施例 ９
実施例１において、BSD加工を実施せず、熱
処理を施し表面層を鏡面研摩により0.5〜5μ除去
した。得られたウエーハをMOSメモリーICに加
工後、そのホールドタイムを測定したところ、結
果は第１図Ｂ曲線とほゞ同じであり、その向上は
ほとんど認められなかつた。Example 9 In Example 1, BSD processing was not performed, but instead heat treatment was performed and 0.5 to 5 μm of the surface layer was removed by mirror polishing. After processing the obtained wafer into a MOS memory IC, the hold time was measured, and the result was almost the same as curve B in Figure 1, with almost no improvement observed.
上記各実施例のBSD加工には平均粒径10μの砥
粒を用いたが、平均粒径3μの砥粒の場合でも同
様の結果が得られた。 Although abrasive grains with an average grain size of 10 μm were used for the BSD processing in each of the above examples, similar results were obtained with abrasive grains with an average grain size of 3 μm.
又、熱処理の場合の雰囲気ガスとしてArガス
の代りにN2ガスを用いても同様の結果であり、
又、前記各実施例の熱処理時間は６時間である
が、該熱処理時間を１時間〜10時間の範囲で行つ
ても同様な結果が得られた。 Also, similar results were obtained when N2 gas was used instead of Ar gas as the atmospheric gas during heat treatment.
Further, although the heat treatment time in each of the above Examples was 6 hours, similar results were obtained even if the heat treatment time was performed in the range of 1 hour to 10 hours.
以上各実施例および第１図にも記載したごと
く、本発明の方法により作製された鏡面ウエーハ
をMOSメモリーICに加工した場合、そのホール
ドタイムは格段に向上し、ホールドタイムによる
不良が顕著に低下する効果が得られ、良品率が向
上した。 As described in each of the examples above and in Fig. 1, when a mirror-finished wafer manufactured by the method of the present invention is processed into a MOS memory IC, the hold time is significantly improved, and the number of defects due to hold time is significantly reduced. This resulted in an improvement in the rate of non-defective products.
第１図はMOS型メモリーICデバイスのホール
ドタイム特性を示す。横軸はホールドタイム（単
位ｍｓ）、縦軸は試料数を示す。曲線Ａは本発明
による鏡面ウエーハを使つてMOS型メモリーIC
デバイスを製作した場合、曲線ＢはBSD加工を
付与後、Arのみの雰囲気中で熱処理後、表面層
を除去した場合、曲線ＣはBSD加工を付与し、
熱処理を実施せずに表面層を除去した場合の各ホ
ールドタイム特性を示す。
Figure 1 shows the hold time characteristics of a MOS type memory IC device. The horizontal axis shows the hold time (unit: ms), and the vertical axis shows the number of samples. Curve A is a MOS type memory IC using the mirrored wafer according to the present invention.
When a device is manufactured, curve B shows that after BSD processing is applied, heat treatment is performed in an atmosphere of only Ar, and the surface layer is removed, curve C is that after BSD processing is applied, and the surface layer is removed.
Each hold time characteristic is shown when the surface layer is removed without heat treatment.
Claims (1)
製造する方法において、CZ単結晶を加工して鏡
面化したウエーハにBSD（バツクサイドダメー
ジ）を付与し該鏡面ウエーハを３〜10％の酸素を
含む窒素ガス又は不活性ガス雰囲気中で1100℃〜
1200℃で１時間以上熱処理を施し、該鏡面ウエー
ハのBSD加工面の反対側の表面層を鏡面研摩に
より除去することを特徴とする半導体デバイス用
シリコン基板の製造方法。 ２ 表面層を0.5μ〜20μ除去することを特徴とす
る特許請求の範囲第１項の半導体デバイス用シリ
コン基板の製造方法。[Claims] 1. A mirrored wafer used for semiconductor devices,
In the manufacturing method, BSD (backside damage) is applied to a mirror-finished wafer processed from a CZ single crystal, and the mirror-finished wafer is heated at 1100°C in a nitrogen gas or inert gas atmosphere containing 3 to 10% oxygen.
A method for producing a silicon substrate for a semiconductor device, which comprises performing heat treatment at 1200° C. for one hour or more, and removing the surface layer of the mirror-finished wafer on the side opposite to the BSD-processed surface by mirror polishing. 2. The method of manufacturing a silicon substrate for a semiconductor device according to claim 1, wherein the surface layer is removed by 0.5 μ to 20 μ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9927082A JPS58216425A (en) | 1982-06-11 | 1982-06-11 | Preparation of semiconductor silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9927082A JPS58216425A (en) | 1982-06-11 | 1982-06-11 | Preparation of semiconductor silicon substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58216425A JPS58216425A (en) | 1983-12-16 |
| JPH0319688B2 true JPH0319688B2 (en) | 1991-03-15 |
Family
ID=14242988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9927082A Granted JPS58216425A (en) | 1982-06-11 | 1982-06-11 | Preparation of semiconductor silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58216425A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62238629A (en) * | 1986-04-09 | 1987-10-19 | Nec Corp | Manufacture of semiconductor substrate |
| JPH01244621A (en) * | 1988-03-25 | 1989-09-29 | Shin Etsu Handotai Co Ltd | Method of cleaning surface of silicon single crystal substrate |
| JPH0222823A (en) * | 1988-07-11 | 1990-01-25 | Toshiba Corp | Manufacture of silicon substrate |
-
1982
- 1982-06-11 JP JP9927082A patent/JPS58216425A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58216425A (en) | 1983-12-16 |
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