JP3177937B2 - Manufacturing method of semiconductor silicon wafer - Google Patents
Manufacturing method of semiconductor silicon waferInfo
- Publication number
- JP3177937B2 JP3177937B2 JP22859694A JP22859694A JP3177937B2 JP 3177937 B2 JP3177937 B2 JP 3177937B2 JP 22859694 A JP22859694 A JP 22859694A JP 22859694 A JP22859694 A JP 22859694A JP 3177937 B2 JP3177937 B2 JP 3177937B2
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- wafer
- semiconductor silicon
- micrograph
- silicon wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Mechanical Treatment Of Semiconductor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、局部的な残留歪みのな
い半導体シリコンウェーハ（以下、単にウェーハという
ことがある）を製造することができる方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor silicon wafer having no local residual distortion (hereinafter, may be simply referred to as a wafer).
【０００２】[0002]
【関連技術】通常、ウェーハは鏡面研磨加工後、洗浄し
て出荷される。しかしながら、鏡面研磨加工後のウェー
ハでは、選択エッチングすると顕在化する傷状のもの、
すなわち潜傷とよばれるものがしばしば現れる。鏡面研
磨されたウェーハのダメージとしてはスクラッチが知ら
れているが、スクラッチと潜傷との違いは、前者が目視
で判別できるのに対し、後者は目視では判別不能である
点である。ウェーハの面上に潜傷が存在すると、そこに
形成される半導体素子の性能、歩留りに悪影響を及ぼし
問題となることがある。2. Related Art Normally, wafers are washed after mirror polishing and then shipped. However, in the case of wafers after mirror polishing, scratches that become apparent upon selective etching,
That is, what is called a latent wound often appears. Scratches are known as damage to mirror-polished wafers. The difference between scratches and latent scratches is that the former can be determined visually, while the latter cannot be determined visually. The presence of latent scratches on the surface of the wafer may adversely affect the performance and yield of semiconductor devices formed thereon, which may be a problem.
【０００３】[0003]
【発明が解決しようとする課題】本発明者は、この潜傷
が、研磨剤や研磨パッドに混在する非常にミクロな異物
によってウェーハ表面が押圧または擦過される際に発生
する比較的弱い局部的な残留歪みであることを解明し
た。そこで、本発明者は、この潜傷を消去する手段につ
いて更に研究を重ねた結果、ウェーハの低温、短時間の
熱処理によってこの潜傷が消去できることを見出し本発
明に到達した。The inventor of the present invention has found that this latent scratch is a relatively weak localized area that is generated when a wafer surface is pressed or rubbed by a very fine foreign substance mixed in an abrasive or a polishing pad. It was clarified that the residual strain was great. The inventor of the present invention has further studied the means for erasing the latent flaw, and as a result, found that the latent flaw can be eliminated by a low-temperature, short-time heat treatment of the wafer, and reached the present invention.
【０００４】本発明は、比較的弱い局部的な残留歪みで
ある潜傷を簡単に消去することのできる半導体シリコン
ウェーハの製造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor silicon wafer capable of easily eliminating latent scratches, which are relatively weak local residual strains.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、本発明方法においては、鏡面研磨加工しついで洗浄
した後の半導体シリコンウェーハを不活性ガスまたは酸
素ガス雰囲気中で４００〜８００℃で１〜３０分間熱処
理し、潜傷を消去するようにした。In order to solve the above-mentioned problems, in the method of the present invention, a semiconductor silicon wafer which has been subjected to mirror polishing and then washed is subjected to an inert gas or an acid.
Heat treatment was performed at 400 to 800 ° C. for 1 to 30 minutes in a raw gas atmosphere to eliminate latent scratches.
【０００６】上記熱処理は、５００〜８００℃が好まし
く、６００〜７００℃がさらに好ましい。上記熱処理時
間の上限は、２０分以下が好ましく、１０分以下がさら
に好ましく、５分以下が最も好ましい。[0006] The heat treatment is preferably performed at 500 to 800 ° C, more preferably at 600 to 700 ° C. The upper limit of the heat treatment time is preferably 20 minutes or less, more preferably 10 minutes or less, and most preferably 5 minutes or less.
【０００７】熱処理雰囲気については、特別の制限はな
いが、Ｎ2 、Ａｒ等の不活性ガスの他Ｏ2 を用いること
ができる。The heat treatment atmosphere is not particularly limited, but O 2 may be used in addition to an inert gas such as N 2 or Ar.
【０００８】[0008]
【実施例】以下に本発明の実施例をあげて説明する。Embodiments of the present invention will be described below.
【０００９】実施例１ 試料ウェーハ：ＣＺ、ｐ型、＜１００＞、１５０ｍｍ
φ、半導体シリコンウェーハ（鏡面研磨後洗浄） 炉への挿入温度：４００℃ 熱処理：４００℃、２分、窒素雰囲気 炉からの取り出し温度：４００℃ 上記熱処理条件を図９に示す。Example 1 Sample wafer: CZ, p-type, <100>, 150 mm
φ, semiconductor silicon wafer (cleaning after mirror polishing) Insertion temperature into furnace: 400 ° C. Heat treatment: 400 ° C., 2 minutes, temperature taken out of furnace under nitrogen atmosphere: 400 ° C. The above heat treatment conditions are shown in FIG.
【００１０】上記条件にて、試料ウェーハを熱処理し、
ついで選択エッチング〔選択エッチング液、５０％Ｈ
Ｆ：６１％ＨＮＯ3 ：ＣＨ3 ＣＯＯＨ：Ｈ2 Ｏ＝１：１
５：３：３（体積比）、エッチング時間：２分〕を行な
った。そのウェーハ表面の顕微鏡写真をとり、図１とし
て示した。Under the above conditions, the sample wafer is heat-treated,
Then, selective etching [selective etching solution, 50% H
F: 61% HNO 3 : CH 3 COOH: H 2 O = 1: 1
5: 3: 3 (volume ratio), etching time: 2 minutes]. A micrograph of the wafer surface is shown in FIG.
【００１１】実施例２ 試料ウェーハ：ＣＺ、ｐ型、＜１１１＞、１５０ｍｍ
φ、半導体シリコンウェーハ（鏡面研磨後洗浄）Example 2 Sample wafer: CZ, p-type, <111>, 150 mm
φ, semiconductor silicon wafer (cleaning after mirror polishing)
【００１２】実施例１の試料ウェーハのかわりに、上記
試料ウェーハを用いた以外は、実施例１と同様にして熱
処理、選択エッチングを行ない、そのウェーハ表面の顕
微鏡写真をとって、図２として示した。Heat treatment and selective etching were performed in the same manner as in Example 1 except that the above-mentioned sample wafer was used instead of the sample wafer of Example 1, and a micrograph of the wafer surface was taken and shown in FIG. Was.
【００１３】実施例３ 炉への挿入温度：４００℃ 昇温：６℃／分 熱処理：６５０℃、２分、窒素雰囲気 炉からの取り出し温度：４００℃ 降温：１０℃／分 上記熱処理条件を図１０に示す。Example 3 Insertion temperature into furnace: 400 ° C. Temperature rise: 6 ° C./min Heat treatment: 650 ° C., 2 minutes, nitrogen atmosphere Removal temperature from furnace: 400 ° C. Temperature drop: 10 ° C./min It is shown in FIG.
【００１４】実施例１の熱処理条件のかわりに、上記熱
処理条件を用いた以外は、実施例１と同様にして熱処
理、選択エッチングを行ない、そのウェーハ表面の顕微
鏡写真をとって図３として示した。A heat treatment and a selective etching were carried out in the same manner as in Example 1 except that the above heat treatment conditions were used instead of the heat treatment conditions of Example 1, and a micrograph of the wafer surface was shown in FIG. .
【００１５】実施例４ 試料ウェーハ：ＣＺ、ｐ型、＜１１１＞、１５０ｍｍ
φ、半導体シリコンウェーハ（鏡面研磨後洗浄）Example 4 Sample wafer: CZ, p-type, <111>, 150 mm
φ, semiconductor silicon wafer (cleaning after mirror polishing)
【００１６】実施例３の試料ウェーハのかわりに、上記
試料ウェーハを用いた以外は、実施例３と同様にして熱
処理、選択エッチングを行ない、そのウェーハ表面の顕
微鏡写真をとって図４として示した。A heat treatment and a selective etching were carried out in the same manner as in Example 3 except that the above-mentioned sample wafer was used instead of the sample wafer of Example 3, and a micrograph of the wafer surface was shown in FIG. .
【００１７】実施例５ 炉への挿入温度：４００℃ 昇温：６℃／分 熱処理：８００℃、２分、窒素雰囲気 炉からの取り出し温度：４００℃ 降温：１０℃／分 上記熱処理条件を図１１に示す。Example 5 Insertion temperature into furnace: 400 ° C. Temperature rise: 6 ° C./min Heat treatment: 800 ° C., 2 minutes, nitrogen atmosphere Removal temperature from furnace: 400 ° C. Temperature drop: 10 ° C./min 11 is shown.
【００１８】実施例１の熱処理条件のかわりに、上記熱
処理条件を用いた以外は、実施例１と同様にして熱処
理、選択エッチングを行ない、そのウェーハ表面の顕微
鏡写真をとって図５として示した。Heat treatment and selective etching were carried out in the same manner as in Example 1 except that the above heat treatment conditions were used instead of the heat treatment conditions in Example 1, and a micrograph of the wafer surface was shown in FIG. .
【００１９】実施例６ 試料ウェーハ：ＣＺ、ｐ型、＜１１１＞、１５０ｍｍ
φ、半導体シリコンウェーハ（鏡面研磨後洗浄）Example 6 Sample wafer: CZ, p-type, <111>, 150 mm
φ, semiconductor silicon wafer (cleaning after mirror polishing)
【００２０】実施例５の試料ウェーハのかわりに、上記
試料ウェーハを用いた以外は、実施例５と同様にして熱
処理、選択エッチングを行ない、そのウェーハ表面の顕
微鏡写真をとって図６として示した。Heat treatment and selective etching were carried out in the same manner as in Example 5 except that the above-mentioned sample wafer was used instead of the sample wafer of Example 5, and a micrograph of the wafer surface was shown in FIG. .
【００２１】比較例１ 熱処理を行なわない以外は、実施例１と同様にして、選
択エッチングを行ない、そのウェーハ表面の顕微鏡写真
をとって、図７として示した。Comparative Example 1 Selective etching was performed in the same manner as in Example 1 except that no heat treatment was performed, and a micrograph of the wafer surface was taken and shown in FIG.
【００２２】比較例２ 熱処理を行なわない以外は、実施例２と同様にして、選
択エッチングを行ない、そのウェーハ表面の顕微鏡写真
をとって、図８として示した。上記した各実施例の結果
から、本発明条件の熱処理を行なうことによってウェー
ハ表面の潜傷が消去又は大幅に低減することが確認され
た。比較例の結果から、熱処理を行なわない場合には多
数の潜傷が存在することが確認できた。また、実施例に
おいてはｐ型のウェーハを示したが、ｎ型のウェーハに
ついても全く同様の効果があることは確認している。Comparative Example 2 Selective etching was performed in the same manner as in Example 2 except that no heat treatment was performed, and a microphotograph of the wafer surface was shown in FIG. From the results of each of the above examples, it was confirmed that the latent heat on the wafer surface was eliminated or significantly reduced by performing the heat treatment under the conditions of the present invention. From the results of the comparative examples, it was confirmed that there were many latent scratches when the heat treatment was not performed. Further, although a p-type wafer is shown in the examples, it has been confirmed that the same effect can be obtained for an n-type wafer.
【００２３】[0023]
【発明の効果】以上述べたごとく、本発明によれば、簡
単な工程の追加により、鏡面加工後のウェーハの局部的
な残留歪である潜傷を消去又は大幅に低減することがで
きるという大きな効果を奏する。As described above, according to the present invention, it is possible to eliminate or significantly reduce latent scratches, which are local residual distortions of a mirror-finished wafer, by adding a simple process. It works.
【図１】実施例１において得られたウェーハ表面の顕微
鏡写真である。FIG. 1 is a photomicrograph of a wafer surface obtained in Example 1.
【図２】実施例２において得られたウェーハ表面の顕微
鏡写真である。FIG. 2 is a micrograph of the wafer surface obtained in Example 2.
【図３】実施例３において得られたウェーハ表面の顕微
鏡写真である。FIG. 3 is a micrograph of a wafer surface obtained in Example 3.
【図４】実施例４において得られたウェーハ表面の顕微
鏡写真である。FIG. 4 is a micrograph of a wafer surface obtained in Example 4.
【図５】実施例５において得られたウェーハ表面の顕微
鏡写真である。FIG. 5 is a micrograph of the wafer surface obtained in Example 5.
【図６】実施例６において得られたウェーハ表面の顕微
鏡写真である。FIG. 6 is a micrograph of the wafer surface obtained in Example 6.
【図７】比較例１において得られたウェーハ表面の顕微
鏡写真である。FIG. 7 is a micrograph of the wafer surface obtained in Comparative Example 1.
【図８】比較例２において得られたウェーハ表面の顕微
鏡写真である。FIG. 8 is a micrograph of the wafer surface obtained in Comparative Example 2.
【図９】実施例１及び２における熱処理条件を示す説明
図である。FIG. 9 is an explanatory view showing heat treatment conditions in Examples 1 and 2.
【図１０】実施例３及び４における熱処理条件を示す説
明図である。FIG. 10 is an explanatory diagram showing heat treatment conditions in Examples 3 and 4.
【図１１】実施例５及び６における熱処理条件を示す説
明図である。FIG. 11 is an explanatory diagram showing heat treatment conditions in Examples 5 and 6.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 清 福島県西白河郡西郷村大字小田倉字大平 150 信越半導体株式会社 半導体白河 研究所内 (56)参考文献 特開 平５−55233（ＪＰ，Ａ) 特開 平４−64238（ＪＰ，Ａ) 特開 平４−354136（ＪＰ，Ａ) 特開 平２−220443（ＪＰ，Ａ) 特開 平２−177542（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/26 - 21/268 H01L 21/322 - 21/326 H01L 21/304 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoshi Suzuki 150 Ohira, Odakura, Nishigo-mura, Nishishirakawa-gun, Fukushima Prefecture Shin-Etsu Semiconductor Co., Ltd. Semiconductor Shirakawa Research Laboratories JP-A-4-64238 (JP, A) JP-A-4-354136 (JP, A) JP-A-2-220443 (JP, A) JP-A-2-177542 (JP, A) Int.Cl. 7 , DB name) H01L 21/26-21/268 H01L 21/322-21/326 H01L 21/304
Claims (3)
体シリコンウェーハを不活性ガスまたは酸素ガス雰囲気
中で４００〜８００℃で１〜３０分間熱処理し、潜傷を
消去することを特徴とする半導体シリコンウェーハの製
造方法。1. A semiconductor silicon wafer which has been mirror-polished and then cleaned, is subjected to an inert gas or oxygen gas atmosphere.
A heat treatment at 400 to 800 [deg.] C. for 1 to 30 minutes to eliminate latent scratches.
０分間行なうことを特徴とする請求項１記載の半導体シ
リコンウェーハの製造方法。2. The heat treatment at 500 to 800 ° C. for 1 to 1
2. The method according to claim 1, wherein the method is performed for 0 minutes.
分間行なうことを特徴とする請求項１記載の半導体シリ
コンウェーハの製造方法。3. The heat treatment at 600 to 700 ° C. for 1 to 5
2. The method according to claim 1, wherein the step is performed for one minute.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22859694A JP3177937B2 (en) | 1994-08-30 | 1994-08-30 | Manufacturing method of semiconductor silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22859694A JP3177937B2 (en) | 1994-08-30 | 1994-08-30 | Manufacturing method of semiconductor silicon wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0870009A JPH0870009A (en) | 1996-03-12 |
| JP3177937B2 true JP3177937B2 (en) | 2001-06-18 |
Family
ID=16878840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22859694A Expired - Fee Related JP3177937B2 (en) | 1994-08-30 | 1994-08-30 | Manufacturing method of semiconductor silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3177937B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW350112B (en) * | 1996-12-27 | 1999-01-11 | Komatsu Denshi Kinzoku Kk | Silicon wafer evaluation method |
| JPH10189677A (en) * | 1996-12-27 | 1998-07-21 | Komatsu Electron Metals Co Ltd | Evaluation method for silicon wafer |
| US5915175A (en) * | 1997-06-27 | 1999-06-22 | Siemens Aktiengesellschaft | Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition |
| JP5052728B2 (en) * | 2002-03-05 | 2012-10-17 | 株式会社Ｓｕｍｃｏ | Method for producing silicon single crystal layer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0464238A (en) * | 1990-07-04 | 1992-02-28 | Sharp Corp | Manufacture of semiconductor device |
| JPH04354136A (en) * | 1991-05-31 | 1992-12-08 | Metarex Kenkyusho:Kk | Method of eliminating residual stress |
| JPH0555233A (en) * | 1991-08-28 | 1993-03-05 | Nec Corp | Manufacture of semiconductor device |
-
1994
- 1994-08-30 JP JP22859694A patent/JP3177937B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0870009A (en) | 1996-03-12 |
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