JPH0729878B2 - Silicon wafer - Google Patents
Silicon waferInfo
- Publication number
- JPH0729878B2 JPH0729878B2 JP2149595A JP14959590A JPH0729878B2 JP H0729878 B2 JPH0729878 B2 JP H0729878B2 JP 2149595 A JP2149595 A JP 2149595A JP 14959590 A JP14959590 A JP 14959590A JP H0729878 B2 JPH0729878 B2 JP H0729878B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon wafer
- silicon
- single crystal
- wafer
- etch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明はLSI等の作製に用いられるシリコンウエーハ、
詳しくはCZ法により引き上げられ、作製されたシリコン
ウエーハの改良に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a silicon wafer used for manufacturing an LSI,
Specifically, it relates to improvement of a silicon wafer produced by pulling up by the CZ method.
〈従来の技術〉 従来のCZ法によるシリコンウエーハは、引き上げられた
単結晶シリコンをスライサーによってスライスして作製
されている。この切断されたシリコンウエーハは、ラッ
プまたは研削が行なわれ、さらに加工歪を除去するた
め、化学的エッチングが行われている。<Prior Art> A conventional CZ silicon wafer is manufactured by slicing pulled single crystal silicon with a slicer. The cut silicon wafer is lapped or ground, and further chemically etched to remove processing strain.
そして、最終仕上げとして、このシリコンウエーハはそ
の表面が鏡面研磨され、洗浄されている。Then, as a final finish, the surface of this silicon wafer is mirror-polished and washed.
〈発明が解決しようとする課題〉 しかしながら、このようなCZ法により作製した従来のシ
リコンウエーハにあっては小さく高密度の欠陥、また
は、大きく低密度の欠陥のいずれかが、存在していた。
これらの欠陥は、鏡面研磨後のアンモニア系洗浄におい
てその表面にエッチピットとなって表れる。<Problems to be Solved by the Invention> However, in a conventional silicon wafer manufactured by such a CZ method, there are either small high density defects or large low density defects.
These defects appear as etch pits on the surface of ammonia-based cleaning after mirror polishing.
そして、この欠陥によりシリコンウエーハの電気的特性
が損なわれていた。The electrical characteristics of the silicon wafer have been impaired by this defect.
また、その結果としてシリコンウエーハの製造における
歩留まりが低下していた。Further, as a result, the yield in the production of silicon wafers has been reduced.
そこで、本発明は、電気特性が向上するとともに、製造
時の歩留まりを高めたシリコンウエーハ提供することを
その目的としている。Therefore, it is an object of the present invention to provide a silicon wafer having improved electrical characteristics and improved yield during manufacturing.
〈課題を解決するための手段〉 本発明は、CZ法によってシリコン単結晶が引き上げら
れ、このシリコン単結晶を素材として作製されたシリコ
ンウエーハにおいて、そのシリコンウエーハの表面にエ
ッチピットが存在しないシリコンウエーハを提供するも
のである。<Means for Solving the Problems> The present invention is a silicon wafer obtained by pulling a silicon single crystal by the CZ method, and in a silicon wafer produced using this silicon single crystal as a material, a silicon wafer having no etch pits on the surface of the silicon wafer. Is provided.
〈作用および効果〉 本発明に係るシリコンウエーハにあっては、鏡面研磨後
のアンモニア系洗浄においてそのシリコンウエーハの表
面には実質上エッチピットは存在しない。すなわち、こ
のシリコンウエーハの表面近傍には上記欠陥が存在しな
いものである。<Operation and Effect> In the silicon wafer according to the present invention, there is substantially no etch pit on the surface of the silicon wafer in the ammonia-based cleaning after mirror polishing. That is, the above defects do not exist near the surface of this silicon wafer.
そして、このようなエッチピットのないシリコンウエー
ハを作製するには、CZ法により引き上げたシリコン単結
晶を所定の冷却速度で冷却する。例えばシリコン単結晶
が1200℃から800℃に冷却されるまでの間の全期間にあ
ってその冷却速度を0.4℃／分より小さくしたものであ
る。Then, in order to manufacture such a silicon wafer having no etch pit, the silicon single crystal pulled by the CZ method is cooled at a predetermined cooling rate. For example, the cooling rate is less than 0.4 ° C./min during the entire period from the cooling of the silicon single crystal from 1200 ° C. to 800 ° C.
この結果、エッチピット、すなわち欠陥のないシリコン
ウエーハが得られる。よって、電気特性は向上し、か
つ、シリコンウエーハの製造上の歩留まりも向上するも
のである。As a result, a silicon wafer having no etch pit, that is, no defect is obtained. Therefore, the electrical characteristics are improved, and the yield in manufacturing the silicon wafer is also improved.
〈実施例〉 以下、本発明の実施例を説明する。<Examples> Examples of the present invention will be described below.
この実施例においては、シリコン単結晶の成長には、CZ
法が用いられている。In this example, CZ was used to grow a silicon single crystal.
Method is used.
この場合、引き上げられたシリコン単結晶が1200℃から
800℃にまで冷却されるその全期間の冷却速度を0.4℃／
分より小さい速度に制御する。または、この冷却速度を
0.5〜1.0℃／分とすることもできる。In this case, the pulled silicon single crystal from 1200 ℃
The cooling rate during the entire period of cooling to 800 ℃ is 0.4 ℃ /
Control to a speed less than a minute. Or this cooling rate
It can also be 0.5 to 1.0 ° C./minute.
そして、このようにして引き上げ形成した高純度の単結
晶シリコンを、通常条件のプロセスを用いてウエーハ加
工し、研磨する。Then, the high-purity single crystal silicon pulled and formed in this manner is processed into a wafer using a process under normal conditions and polished.
このようにして作製したＰ型、（100）方位のシリコン
ウエーハをアンモニア系洗浄液、例えばNH4OH/H2O2/H2O
液（1:1:5）を用いて、エッチング作用を強くするため
に通常よりも高温である85℃で、20分間程度洗浄する。The P-type, (100) -oriented silicon wafer thus produced is treated with an ammonia-based cleaning solution such as NH 4 OH / H 2 O 2 / H 2 O.
Use a liquid (1: 1: 5) and wash for 20 minutes at 85 ° C, which is higher than usual, to strengthen the etching action.
この洗浄を10回繰り返す。この結果、0.1μｍの大きさ
のエッチピットを周知パーティクルカウンタによりカウ
ントすることができる。Repeat this wash 10 times. As a result, etch pits having a size of 0.1 μm can be counted by a well-known particle counter.
この結果、シリコンウエーハの表面においては、例えば
現在顧客からの要求レベルでもある直径0.2μｍ程度の
大きさのエッチピットが形成されることはない。As a result, on the surface of the silicon wafer, for example, an etch pit having a diameter of about 0.2 μm, which is currently required by customers, is not formed.
例えば周知パーティクルカウンタにより測定した場合、
従来のCZ法に係るシリコンウエーハではこのアンモニア
系洗浄を10回繰り返すことにより、エッチピットが1000
個程度確認することができた。これに対して、本実施例
では同様の洗浄後の測定では０個、すなわちエッチピッ
トは確認することができなかったものである。For example, when measured with a well-known particle counter,
With the conventional CZ method silicon wafer, by repeating this ammonia cleaning 10 times, the etch pit becomes 1000
I was able to confirm about one piece. On the other hand, in the present embodiment, the number of 0, that is, etch pits could not be confirmed in the same measurement after cleaning.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 龍田 次郎 埼玉県大宮市北袋町１丁目297番地 三菱 金属株式会社中央研究所内 (72)発明者 島貫 康 埼玉県大宮市北袋町１丁目297番地 三菱 金属株式会社中央研究所内 (72)発明者 田中 俊郎 東京都千代田区岩本町３丁目８番16号 日 本シリコン株式会社内 (56)参考文献 特開 昭56−45894（ＪＰ，Ａ) 特開 昭61−201692（ＪＰ，Ａ) 特開 昭62−202900（ＪＰ，Ａ) 特開 平３−177391（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jiro Tatsuta 1-297 Kitabukuro-cho, Omiya-shi, Saitama, Central Research Laboratory, Mitsubishi Metals Co., Ltd. Central Research Institute Co., Ltd. (72) Inventor Toshiro Tanaka 3-8-16 Iwamotocho, Chiyoda-ku, Tokyo Nihon Silicon Co., Ltd. (56) Reference JP-A-56-45894 (JP, A) JP-A-61 -201692 (JP, A) JP 62-202900 (JP, A) JP 3-177391 (JP, A)
Claims (1)
れ、このシリコン単結晶を素材として作製されたシリコ
ンウエーハにおいて、 そのシリコンウエーハの表面にエッチピットが存在しな
いことを特徴とするシリコンウエーハ。1. A silicon wafer produced by pulling a silicon single crystal by the CZ method, wherein the silicon single crystal is made of a raw material, and the silicon wafer has no etch pits on its surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149595A JPH0729878B2 (en) | 1990-06-07 | 1990-06-07 | Silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149595A JPH0729878B2 (en) | 1990-06-07 | 1990-06-07 | Silicon wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0442893A JPH0442893A (en) | 1992-02-13 |
| JPH0729878B2 true JPH0729878B2 (en) | 1995-04-05 |
Family
ID=15478643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2149595A Expired - Lifetime JPH0729878B2 (en) | 1990-06-07 | 1990-06-07 | Silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0729878B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6913647B2 (en) | 1998-06-26 | 2005-07-05 | Memc Electronic Materials, Inc. | Process for cooling a silicon ingot having a vacancy dominated region to produce defect free silicon |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629216A (en) * | 1994-06-30 | 1997-05-13 | Seh America, Inc. | Method for producing semiconductor wafers with low light scattering anomalies |
| US5709755A (en) * | 1996-08-09 | 1998-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for CMP cleaning improvement |
| US6379642B1 (en) | 1997-04-09 | 2002-04-30 | Memc Electronic Materials, Inc. | Vacancy dominated, defect-free silicon |
| DE69841714D1 (en) | 1997-04-09 | 2010-07-22 | Memc Electronic Materials | Silicon with low defect density and ideal oxygen precipitation |
| CN1280455C (en) | 1997-04-09 | 2006-10-18 | Memc电子材料有限公司 | Low defect density silicon |
| JP4688984B2 (en) * | 1997-12-26 | 2011-05-25 | 株式会社Ｓｕｍｃｏ | Silicon wafer and crystal growth method |
| US6284039B1 (en) | 1998-10-14 | 2001-09-04 | Memc Electronic Materials, Inc. | Epitaxial silicon wafers substantially free of grown-in defects |
| US7105050B2 (en) | 2000-11-03 | 2006-09-12 | Memc Electronic Materials, Inc. | Method for the production of low defect density silicon |
| US6846539B2 (en) | 2001-01-26 | 2005-01-25 | Memc Electronic Materials, Inc. | Low defect density silicon having a vacancy-dominated core substantially free of oxidation induced stacking faults |
| MY157902A (en) | 2006-05-19 | 2016-08-15 | Memc Electronic Materials | Controlling agglomerated point defect and oxygen cluster formation induced by the lateral surface of a silicon single crystal during cz growth |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5645894A (en) * | 1979-09-25 | 1981-04-25 | Nippon Telegr & Teleph Corp <Ntt> | Reducing method for defect of silicon single crystal |
| JPS61201692A (en) * | 1985-03-04 | 1986-09-06 | Mitsubishi Metal Corp | Method for pulling and growing silicon single crystal with less generation of defect |
| JPS62202900A (en) * | 1986-03-03 | 1987-09-07 | Toshiba Corp | Semiconductor silicon wafer and production thereof |
| JP2549445B2 (en) * | 1989-12-05 | 1996-10-30 | 新日本製鐵株式会社 | Method for producing silicon single crystal |
-
1990
- 1990-06-07 JP JP2149595A patent/JPH0729878B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6913647B2 (en) | 1998-06-26 | 2005-07-05 | Memc Electronic Materials, Inc. | Process for cooling a silicon ingot having a vacancy dominated region to produce defect free silicon |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0442893A (en) | 1992-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW229324B (en) | Low cost method of fabricating epitaxial semiconductor devices | |
| US3170273A (en) | Process for polishing semiconductor materials | |
| US5899731A (en) | Method of fabricating a semiconductor wafer | |
| JPH0729878B2 (en) | Silicon wafer | |
| JP3620683B2 (en) | Manufacturing method of semiconductor wafer | |
| JP4066202B2 (en) | Manufacturing method of semiconductor wafer | |
| JP3219142B2 (en) | Polishing agent for polishing semiconductor silicon wafer and polishing method | |
| JP3503444B2 (en) | Method for manufacturing semiconductor wafer having semiconductor wafer etching step | |
| JP3202305B2 (en) | Manufacturing method and inspection method of mirror surface wafer | |
| JP3177937B2 (en) | Manufacturing method of semiconductor silicon wafer | |
| WO2007049435A1 (en) | Semiconductor wafer manufacturing method and semiconductor wafer cleaning method | |
| JPH09266212A (en) | Silicon wafer | |
| JP2000243731A (en) | Manufacture of high-flatness wafer | |
| US6063205A (en) | Use of H2 O2 solution as a method of post lap cleaning | |
| JP2689007B2 (en) | Silicon wafer and method of manufacturing the same | |
| JPS5885534A (en) | Manufacture of semiconductor silicon | |
| JP2894154B2 (en) | Method for measuring the depth of the affected layer on the silicon wafer surface | |
| JP2694305B2 (en) | Method for manufacturing single crystal silicon | |
| JP3359434B2 (en) | Manufacturing method of epitaxial wafer | |
| KR100234231B1 (en) | Method for fabricating epitaxial semiconcutor device | |
| JP2003007672A (en) | Method of etching silicon semiconductor wafer | |
| JP3487489B2 (en) | Manufacturing method of semiconductor wafer | |
| JP3400694B2 (en) | Silicon wafer etching method | |
| JPH0319688B2 (en) | ||
| JP2003077875A (en) | Cleaning method of silicon wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080405 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090405 Year of fee payment: 14 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100405 Year of fee payment: 15 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100405 Year of fee payment: 15 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110405 Year of fee payment: 16 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110405 Year of fee payment: 16 |