JPS5933972B2 - Silicon substrate manufacturing method - Google Patents

Silicon substrate manufacturing method

Info

Publication number
JPS5933972B2
JPS5933972B2 JP9927182A JP9927182A JPS5933972B2 JP S5933972 B2 JPS5933972 B2 JP S5933972B2 JP 9927182 A JP9927182 A JP 9927182A JP 9927182 A JP9927182 A JP 9927182A JP S5933972 B2 JPS5933972 B2 JP S5933972B2
Authority
JP
Japan
Prior art keywords
wafer
oxygen
mirror
heat treatment
bsd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9927182A
Other languages
Japanese (ja)
Other versions
JPS58216426A (en
Inventor
信之 秋山
光雄 河野
俊介 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
Original Assignee
Komatsu Electronic Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Electronic Metals Co Ltd filed Critical Komatsu Electronic Metals Co Ltd
Priority to JP9927182A priority Critical patent/JPS5933972B2/en
Publication of JPS58216426A publication Critical patent/JPS58216426A/en
Publication of JPS5933972B2 publication Critical patent/JPS5933972B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Description

【発明の詳細な説明】 本発明は、半導体デバイスに使用する鏡面ウエー ・・
を製造する方法に関する。
[Detailed Description of the Invention] The present invention provides a mirrored wafer for use in semiconductor devices.
Relating to a method of manufacturing.

通常、IC、VLSI用のシリコン基板には鏡面ウエー
ー゛を使用する。
Usually, mirrored wafers are used for silicon substrates for ICs and VLSIs.

鏡面ウエーー・には、シリコン単結晶棒より、スライス
、ラップ、面取、エッチング後研摩したシリコン基板と
シリコン単結晶棒よりスライス、ラップ、面取り、エッ
チングしたシリコン基板がある。最近はシリコン基板に
ゲツタリング処理を施すことが多い。
Mirror wafers include silicon substrates that have been sliced, lapped, chamfered, and etched from silicon single crystal rods and then polished, and silicon substrates that have been sliced, lapped, chamfered, and etched from silicon single crystal rods. Recently, silicon substrates are often subjected to gettering treatment.

ゲツタリング処理を大別するとエクストリンシツクゲツ
タリングとイントリンシツクゲツタリング(以下IGと
いラ)がある。エクストリンシツクゲツタリングの1つ
にバックサイドダメージ(以下BSDといラ)があり液
体ホーニング、サンドブラスト等によりシリコン基板の
裏面に砥粒を噴射して、ダメージを入れることが一般的
に行われている。このダメージは、砥粒の粒径、砥粒の
噴射圧力をコントロールすることにより、シリコン基板
の裏面に5〜10μのクラック層を付与するタイプと、
その後の半導体デバイス工程中にシリコン基板の裏面に
積層欠陥を発生させるタイプに分けられる。
Gettering processing can be roughly divided into extrinsic gettering and intrinsic gettering (hereinafter referred to as IG). One type of extrinsic getttering is backside damage (hereinafter referred to as BSD), and it is common practice to inject abrasive particles onto the back side of a silicon substrate using liquid honing, sandblasting, etc. to cause damage. . This damage can be done by controlling the particle size of the abrasive grains and the jetting pressure of the abrasive grains to create a crack layer of 5 to 10 microns on the back surface of the silicon substrate.
There are two types of stacking faults that occur on the backside of the silicon substrate during the subsequent semiconductor device process.

クラック層を付与するタイプは半導体デバイス作製工程
中にゲツタリング効果が消失しにくい反面、ソリに代表
されるシリコン基板の変形や、クラック層中に付着した
汚染の影響が残る等の問題点がある。
While the type that provides a crack layer does not easily eliminate the gettering effect during the semiconductor device manufacturing process, there are problems such as deformation of the silicon substrate, typified by warpage, and the residual effects of contamination adhered to the crack layer.

又、積層欠陥を発生させるタイプは、半導体デバイス作
製工程中に基板の変形や、汚染の問題は起らないが、ゲ
ツタリング効果の消失があり、期待した程のICのホー
ルドタイムや良品率の向上は得られない問題点がある。
In addition, the type that generates stacking faults does not cause problems with substrate deformation or contamination during the semiconductor device manufacturing process, but the gettering effect disappears, making it difficult to improve IC hold time and yield rate as expected. There is a problem that it cannot be obtained.

本出願人が特願昭56−142334に詳細に説明した
ごとく、IG付与鏡面ウエーー・について実験を行い、
高温と低温の2ステツプ熱処理後、該鏡面ウエーー・の
表面層を除去することにより、MOSメモリーのホール
ドタイム不良を低下することができた。
As explained in detail in Japanese Patent Application No. 56-142334, the present applicant conducted an experiment on the IG-applied mirror surface wafer.
After the two-step heat treatment at high and low temperatures, the surface layer of the mirror wafer was removed, thereby reducing the hold time failure of the MOS memory.

その後、本発明者等は半導体デバイス作製後のホールド
タイムや良品率の向上について種々の継続実験を行つた
結果、鏡面ウエーー・にBSDを付与した後、該鏡面ウ
エーー・を3〜10%の酸素を含む雰囲気中で高温と低
温の2ステツプ熱処理または3〜10%の酸素を含む雰
囲気中で高温引続いで唆素を含まな(・雰囲気中で低温
の2ステツプ熱処理を施し、該鏡面ウエーー・の表面層
を除去することにより、多大な効果が得られることを見
出した。
Subsequently, the present inventors conducted various continuous experiments to improve the hold time and non-defective rate after semiconductor device fabrication, and found that after applying BSD to the mirrored wafer, the mirrored wafer was exposed to 3 to 10% oxygen. 2-step heat treatment at high temperature and low temperature in an atmosphere containing oxygen, or 2-step heat treatment at high temperature and low temperature in an atmosphere containing 3 to 10% oxygen, followed by low temperature in an atmosphere containing no oxygen. It has been found that significant effects can be obtained by removing the surface layer of

即ち、石英ルツボを使用した引上げ法による半導体シリ
コン棒よりシリコン基板を製造する方法に於いて、該半
導体シリコン棒をウエーノ訛した後、加工々程、例えば
エツチングする工程、研摩する工程、あるいはその中間
工程において、鏡面ウエーハに半導体デバイス工程中に
積層欠陥を発生するタイプのBSDを付与した後、3〜
10%の酸素を含む雰囲気中で、高温と低温の2ステツ
プ熱処理、または3〜10%の酸素を含む雰囲気中で高
温、引続いて酸素を含まな(・雰囲気中で低温の2ステ
ツプ熱処理を施し、その後、シリコン表面層を取り除く
ことにより多大な効果を得たのである。
That is, in a method of manufacturing a silicon substrate from a semiconductor silicon rod by a pulling method using a quartz crucible, after the semiconductor silicon rod is made into a wax material, a processing step such as an etching step, a polishing step, or an intermediate step thereof is performed. In the process, after imparting BSD of the type that causes stacking faults during the semiconductor device process to the mirror-finished wafer,
Two-step heat treatment at high temperature and low temperature in an atmosphere containing 10% oxygen, or two-step heat treatment at high temperature and then low temperature in an atmosphere containing 3 to 10% oxygen. By applying this method and then removing the silicon surface layer, a great effect was obtained.

本発明の特徴は、鏡面ウエーー・にBSD加工後、3〜
10%の酸素を含む雰囲気中で高温と低温の2ステツブ
熱処理、または3〜10%の酸素を含む雰囲気中で高温
引続いて酸素を含まない雰囲気中で低温の2ステツブ熱
処理を施した後、表面層を取り除くことにある。
The feature of the present invention is that after BSD processing on the mirror surface wafer, 3~
After performing a two-step heat treatment at high and low temperatures in an atmosphere containing 10% oxygen, or a two-step heat treatment at a high temperature and then at a low temperature in an oxygen-free atmosphere in an atmosphere containing 3 to 10% oxygen, The purpose is to remove the surface layer.

以下各実施例について説明する。Each example will be described below.

実施例 1 酸素濃度14〜18×1017at0ms/Cc(AS
′RM表示)を含有するCZ無転位単結晶より、スライ
ス工程、面取り工程、ラツプ工程エツチング工程を実施
したP型(100)7〜10Ω{、100ψ、525μ
の鏡面ウエーー・に平均粒径10μの砥粒を1.5kg
/(1−JモVfの空気圧で噴射してBSD加工した。
Example 1 Oxygen concentration 14-18×1017at0ms/Cc (AS
P-type (100) 7-10Ω {, 100ψ, 525μ, which has been subjected to slicing, chamfering, wrapping and etching processes from CZ dislocation-free single crystal containing 'RM display)
1.5kg of abrasive grains with an average particle size of 10μ are applied to the mirror surface wafer.
/(BSD processing was performed by injecting with air pressure of 1-J mo Vf.

該鏡面ウエーー・を洗浄後、Arに酸素を5(F6加え
た雰囲気中で、1150℃で8時間、続いて700℃で
8時間の2ステツプ熱処理を施し、該鏡面ウエ一・・を
希弗酸により酸化膜を除き、BSD加工面の反対面であ
る表面層を鏡面研摩により10〜20μ除去した。第1
図は本実施例による鏡面ウエ一・・を使つてMOS型メ
モリー1Cデバイスを製作した場合(A曲線)と、BS
Dを付与した後、Arのみの雰囲気中で2ステツプ熱処
理後、表面層を除去した場合(B曲線)と、BSDを付
与し、2ステツプ熱処理を実施せずに表面層を除去した
場合(C曲線)のホールドタイムの比較を示している。
After cleaning the specular wafer, it was subjected to a two-step heat treatment of 8 hours at 1150°C and then 8 hours at 700°C in an atmosphere containing 5% oxygen (F6) to Ar to remove the diluted wafer. The oxide film was removed with acid, and 10 to 20μ of the surface layer, which is the opposite side to the BSD processed surface, was removed by mirror polishing.First
The figure shows the case where a MOS type memory 1C device is manufactured using the mirror-finished wafer according to this embodiment (curve A), and the case where the BS
After applying D, the surface layer was removed after 2-step heat treatment in an atmosphere of Ar only (curve B), and when BSD was applied and the surface layer was removed without performing 2-step heat treatment (curve C). A comparison of the hold times of curves) is shown.

第1図の横軸はホールドタイム(単位MS)縦軸ぱ試料
数を示す。第1図かられかる様に、ホールドタイムはA
曲線の場合がB曲線、C曲線より長く、ホールドタイム
不良を顕著に低下することができた。このことにより、
BSDを付与して、酸素を5(f)含む雰囲気中で11
50℃8時間、7000C8時間の2ステツプ熱処理を
施し、10〜20μの表面層を除去することが、ホール
ドタイムの向上に重要であることを示している。実施例
2実施例1と同様の鏡面ウエーー・に同様のBSD加
工を施し、洗浄後、Arに酸素を3%加えた雰囲気中で
、1150℃で8時間、続いて700雰Cで8時間の2
ステツプ熱処理を施し、希弗酸により酸化膜を除き、B
SD加工面の反対面である表面層を鏡面研摩により10
〜20μ除去した。
In FIG. 1, the horizontal axis shows the hold time (unit: MS) and the vertical axis shows the number of samples. As shown in Figure 1, the hold time is A
The curve was longer than curves B and C, and the hold time failure could be significantly reduced. Due to this,
11 in an atmosphere containing 5(f) oxygen with BSD.
This shows that performing a two-step heat treatment of 8 hours at 50°C and 8 hours at 7000C to remove a 10-20μ surface layer is important for improving the hold time. Example 2 A mirror surface wafer similar to that of Example 1 was subjected to the same BSD processing, and after cleaning, it was heated at 1150°C for 8 hours in an atmosphere containing 3% oxygen in Ar and then at 700 atmosphere C for 8 hours. 2
Step heat treatment is performed, the oxide film is removed with dilute hydrofluoric acid, and B
The surface layer, which is the opposite side to the SD processed surface, is polished to a 10%
~20μ removed.

これらのウエーハをMOSメモリーCに加工後、そのホ
ールドタイムを測定した結果、その向上は実施例1と同
様であり、ホールドタイム不良が顕著に低下した。実施
例 3 Arに酸素を10%加えた雰囲気を用いて、実施例1と
全く同様の実験を実施した。
After processing these wafers into MOS memory C, the hold time was measured. As a result, the improvement was the same as in Example 1, and the hold time defects were significantly reduced. Example 3 An experiment exactly the same as in Example 1 was conducted using an atmosphere of Ar with 10% oxygen added.

得られたウエ一・・をMOSメモリー1Cに加工後、そ
のホールドタイムを測定した結果、その向上は実施例1
と同様であり、ホールドタイム不良が顕著に低下した。
実施例 4 Arに酸素を2%加えた雰囲気を用いて、実施例1と全
く同様の実験を実施した。
After processing the obtained wafer into MOS memory 1C, the hold time was measured, and the improvement was found to be the same as in Example 1.
The result was similar to that of the previous example, and the hold time failure was significantly reduced.
Example 4 An experiment exactly the same as in Example 1 was conducted using an atmosphere of Ar with 2% oxygen added.

得られたウエーハをMOSメモリー1Cに加工後、その
ホールドタイムを測定したところ、その結果は第1図B
曲線とほ寸同じであり、その向上はほとんど認められな
かつた。実施例 5 Arf1C酸素を15%加えた雰囲気を用いて、実施例
1と全く同様の実験を実施した。
After processing the obtained wafer into MOS memory 1C, the hold time was measured, and the results are shown in Figure 1B.
It was almost the same as the curve, and there was almost no discernible improvement. Example 5 An experiment completely similar to Example 1 was conducted using an atmosphere containing 15% Arf1C oxygen.

得られたウエーハをMOSメモリー1Cに加工様、その
ホールドタイムを測定したところ、その結果は第1図C
曲線とほ寸同じであり、その向上はほとんど認められな
かつた。実施例 6 実施例1において、エツチング工程後、鏡面研摩工程を
加え、同様なBSD加工、同様な熱処理を施し、表面層
を鏡面研摩により0.5〜5μ除去した。
The obtained wafer was processed into MOS memory 1C, and the hold time was measured, and the results are shown in Figure 1C.
It was almost the same as the curve, and there was almost no discernible improvement. Example 6 In Example 1, a mirror polishing step was added after the etching step, and similar BSD processing and similar heat treatment were performed, and 0.5 to 5 μm of the surface layer was removed by mirror polishing.

得られたウエーー・をMOSメモリー1Cに加工後、そ
のホールドタイムを測定した結果、その向上は実施例1
と同様であり、ホールドタイム不良が顕著に低下した。
実施例 7 実施例1において、エツチング工程後、鏡面研摩工程を
加え、BSD加工を実施せず、同様な熱処理を施し、表
面層を鏡面研摩により0.5〜5μ除去した。
After processing the obtained way into MOS memory 1C, the hold time was measured, and the improvement was found in Example 1.
The result was similar to that of the previous example, and the hold time failure was significantly reduced.
Example 7 In Example 1, a mirror polishing step was added after the etching step, and the same heat treatment was performed without BSD processing, and 0.5 to 5 μm of the surface layer was removed by mirror polishing.

得られたウエーー・をMOSメモリーICに加工後、そ
のホールドタイムを測定したところ、その結果は第1図
B曲線とほ〜同じであり、その向上はほとんど認められ
なかつた。実施例 8 実施例1乃至実施例7において、高温熱処理は各実施例
における酸素量を含む雰囲気中で、低温熱処理は酸素を
含まない雰囲気中で、その他の条件は各実施例の条件と
同様にして実験を行つた。
After processing the obtained wafer into a MOS memory IC, its hold time was measured, and the result was almost the same as the curve B in FIG. 1, with almost no improvement observed. Example 8 In Examples 1 to 7, high-temperature heat treatment was performed in an atmosphere containing an amount of oxygen in each example, low-temperature heat treatment was performed in an atmosphere without oxygen, and other conditions were the same as those in each example. I conducted an experiment.

得られたウエ一・・をMOSメモリー1Cに加工後、ホ
ールドタイムん測定した結果は各実施例における結果と
ほ〜同様であつた。実施例 9 実施例1において、高温熱処理はArのみの雰囲気中で
、低温熱処理は、5(F6の酸素を含むAr雰囲気中で
実験を行なつた。
After processing the obtained wafer into a MOS memory 1C, the hold time was measured and the results were almost the same as those in each example. Example 9 In Example 1, the high-temperature heat treatment was conducted in an atmosphere containing only Ar, and the low-temperature heat treatment was conducted in an Ar atmosphere containing 5 (F6) oxygen.

得られたウエーー・をMOSメモリー1Cに加工後、ホ
ールドタイムを測定したところ、その向上はほとんど認
められなかつた。上記各実施例のBSD加工には平均粒
径10μの砥粒を用いたが、平均粒径3μの砥粒の場合
でも同様の結果が得られた。
After processing the obtained way into a MOS memory 1C, the hold time was measured, and almost no improvement was observed. Although abrasive grains with an average grain size of 10 μm were used for the BSD processing in each of the above examples, similar results were obtained with abrasive grains with an average grain size of 3 μm.

又、熱処理の場合の雰囲気ガスとしてArガスの代りに
N2ガスを用いても同様の結果が得られた。以上各実施
例および第1図にも記載したごとく、本発明の方法によ
り作製された鏡面ウエーー・をMOSメモリー1Cに加
工した場合、そのホールドタイムは格段に向上し、ホー
ルドタイムによる不良が顕著に低下する効果が得られ、
良品率が向上した。
Furthermore, similar results were obtained when N2 gas was used instead of Ar gas as the atmospheric gas during the heat treatment. As described in each of the above embodiments and FIG. 1, when the mirror surface wafer fabricated by the method of the present invention is processed into MOS memory 1C, the hold time is significantly improved, and defects due to hold time are significantly reduced. The effect of reducing
The rate of non-defective products has improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はMOS型メモリー1Cデバイスのホールドタイ
ム特性を示す。 横軸はホールドタイム(単位MS)、縦軸は試料数を示
す。
FIG. 1 shows the hold time characteristics of a MOS type memory 1C device. The horizontal axis shows the hold time (unit: MS), and the vertical axis shows the number of samples.

Claims (1)

【特許請求の範囲】 1 半導体デバイスに使用する鏡面ウエーハを製造する
方法において、鏡面化したウエーハにBSD(バックサ
イドダメージ)を付与し該鏡面ウエーハを、3〜10%
の酸素を含む雰囲気中で高温と低温の2ステップ熱処理
を施し、該鏡面ウエーハのBSD加工面の反対面である
表面層を除去することを特徴とする半導体デバイス用シ
リコン基板の製造方法。 2 半導体デバイスに使用する鏡面ウエーハを製造する
方法において、鏡面化したウエーハにBSD(バックサ
イドダメージ)を付与し、該鏡面ウエーハを、3〜10
%の酸素を含む雰囲気中で高温熱処理を行い、引続いて
酸素を含まない雰囲気中で低温熱処理を施し、該鏡面ウ
エーハのBSD加工面の反対面である表面層を除去する
ことを特徴とする半導体デバイス用シリコン基板の製造
方法。 3 3〜10%の酸素を含む雰囲気中で熱処理を施し、
該鏡面ウエーハの表面層を0.5〜20μ除去すること
を特徴とする特許請求の範囲第1項又は第2項の半導体
デバイス用シリコン基板の製造方法。
[Claims] 1. A method for manufacturing a mirror-finished wafer for use in semiconductor devices, in which BSD (backside damage) is applied to a mirror-finished wafer and the mirror-finished wafer is damaged by 3 to 10%.
A method for manufacturing a silicon substrate for a semiconductor device, which comprises performing two-step heat treatment at high and low temperatures in an atmosphere containing oxygen to remove a surface layer of the mirror-finished wafer, which is the surface opposite to the BSD processed surface. 2. In a method for manufacturing a mirrored wafer used in semiconductor devices, BSD (backside damage) is applied to a mirrored wafer, and the mirrored wafer is
% of oxygen, followed by low-temperature heat treatment in an oxygen-free atmosphere to remove the surface layer of the mirror-finished wafer, which is the surface opposite to the BSD processed surface. A method for manufacturing a silicon substrate for semiconductor devices. 3 Heat treatment in an atmosphere containing 3 to 10% oxygen,
3. The method of manufacturing a silicon substrate for a semiconductor device according to claim 1, wherein 0.5 to 20 μm of the surface layer of the mirror-finished wafer is removed.
JP9927182A 1982-06-11 1982-06-11 Silicon substrate manufacturing method Expired JPS5933972B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9927182A JPS5933972B2 (en) 1982-06-11 1982-06-11 Silicon substrate manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9927182A JPS5933972B2 (en) 1982-06-11 1982-06-11 Silicon substrate manufacturing method

Publications (2)

Publication Number Publication Date
JPS58216426A JPS58216426A (en) 1983-12-16
JPS5933972B2 true JPS5933972B2 (en) 1984-08-20

Family

ID=14243015

Family Applications (1)

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JP9927182A Expired JPS5933972B2 (en) 1982-06-11 1982-06-11 Silicon substrate manufacturing method

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0378870U (en) * 1989-12-04 1991-08-09
JPH0682364U (en) * 1993-05-11 1994-11-25 有限会社ベスト青梅 Door stop device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3014152B2 (en) * 1991-02-07 2000-02-28 三菱電機株式会社 Method for manufacturing semiconductor wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0378870U (en) * 1989-12-04 1991-08-09
JPH0682364U (en) * 1993-05-11 1994-11-25 有限会社ベスト青梅 Door stop device

Also Published As

Publication number Publication date
JPS58216426A (en) 1983-12-16

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