CN116798853A - Growth method of silicon epitaxial wafer - Google Patents

Growth method of silicon epitaxial wafer Download PDF

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Publication number
CN116798853A
CN116798853A CN202310584101.7A CN202310584101A CN116798853A CN 116798853 A CN116798853 A CN 116798853A CN 202310584101 A CN202310584101 A CN 202310584101A CN 116798853 A CN116798853 A CN 116798853A
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silicon
wafer
monocrystalline silicon
single crystal
oxide film
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谈耀忠
张俊宝
陈猛
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Chongqing Advanced Silicon Technology Co ltd
Shanghai Chaosi Semiconductor Co ltd
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Chongqing Advanced Silicon Technology Co ltd
Shanghai Chaosi Semiconductor Co ltd
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67276—Production flow monitoring, e.g. for increasing throughput

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  • Engineering & Computer Science (AREA)
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Abstract

The application relates to a method for growing a silicon epitaxial wafer, which relates to the technical field of semiconductor materials, and comprises the steps of firstly removing a natural oxide film on the surface of a monocrystalline silicon wafer at the temperature of 650 ℃ or lower after a plurality of processing procedures are carried out on the monocrystalline silicon, respectively forming oxygen atoms and monocrystalline silicon on the surface of the monocrystalline silicon by using nitrous oxide after the natural oxide film is removed, wherein the formation of the oxygen atoms is carried out by exposing the monocrystalline silicon wafer to an atmosphere containing the nitrous oxide, the monocrystalline silicon is epitaxially grown at the temperature of 500 ℃ or higher and 700 ℃ or lower, and a plurality of oxygen atom layers and monocrystalline silicon layers are alternately formed when the forming procedures of the oxygen atoms and the monocrystalline silicon are carried out for a plurality of times, and finally, the silicon epitaxial layer is formed. The application reduces the problem that the temperature uniformity of the wafer is poor and particles are arranged on the surface of the wafer due to local heat loss of the wafer.

Description

Growth method of silicon epitaxial wafer
Technical Field
The application belongs to the technical field of semiconductor materials, and particularly relates to a growth method of a silicon epitaxial wafer.
Background
Silicon epitaxial wafers are the most important material for integrated circuits. Is widely used in microprocessor units (MPUs), logic chips, flash memories, dynamic Random Access Memories (DRAMs), and the like. Silicon epitaxial wafers have advantages over polished wafers in improving yield and performance of electronic devices.
In a typical silicon epitaxial wafer fabrication process, a silicon substrate wafer is placed on a base of an epitaxial furnace, epitaxial growth is typically performed at 1100-1150 ℃ using an atmosphere of TCS, HCl and dopants, and the thickness of the epitaxial layer varies with position on the base. Wafers such as single crystal silicon wafers are subjected to various processes such as depositing a layer of a predetermined material on a surface, etching a layer of a predetermined material on a surface, or heat treating the entire wafer. Such processes may be classified into batch processes in which a plurality of wafers are simultaneously accommodated in a chamber as a reactor and single wafer processes in which only one wafer is processed at a time.
However, the conventional method of growing an epitaxial layer on a wafer tends to have problems in that some particulate contaminants or defects may occur at portions lifted from the lower surface of the wafer by the lift pins, and these pin marks are generated because they cause local heat loss of the wafer in consideration of their frequent occurrence in processes involving excessively high temperature heat (e.g., epitaxial growth, heat treatment, etc.), resulting in deterioration of temperature uniformity of the wafer and thus particles on the surface of the wafer.
Disclosure of Invention
In view of the above-mentioned drawbacks, an object of the present application is to provide a method for growing a silicon epitaxial wafer, which can effectively reduce the problem that the wafer surface has particles due to the deterioration of the temperature uniformity of the wafer caused by local heat loss of the wafer.
The application relates to a growth method of a silicon epitaxial wafer, which comprises the following steps:
step 1, a removal procedure of removing a natural oxide film on the surface of a monocrystalline silicon piece is carried out below 650 ℃;
step 2, after the removal of the natural oxide film, forming oxygen atoms and single crystal silicon on the surface of the single crystal silicon wafer by using nitrous oxide, respectively, wherein,
the oxygen atoms are formed by exposing the single crystal silicon wafer to an atmosphere containing the nitrous oxide, and setting the partial pressure of the nitrous oxide to 10Pa or more and 10000Pa or less, and forming an oxygen atom layer at a temperature of 30 ℃ or more and 650 ℃ or less for baking for 5 to 10 minutes,
the monocrystalline silicon is formed by epitaxial growth by baking at a temperature of more than 500 ℃ and less than 700 ℃ for 8-15 minutes, the partial pressure of a silicon source is controlled to be more than 0.5Pa and less than 2000Pa, and the growth rate is controlled to be 1.30 mu m/min-1.70 mu m/min;
and 3, repeating the step 2, and alternately forming a plurality of oxygen atom layers and single crystal silicon layers by performing the step of forming oxygen atoms and single crystal silicon a plurality of times.
Further, in the step 1, the step of removing the natural oxide film is performed by using hydrofluoric acid or hydrofluoric acid vapor.
Further, in forming the oxygen atomic layer, nitrogen or a rare gas is used as a diluent gas in an atmosphere containing dinitrogen monoxide.
Further, the silicon source comprises SiHCL 3 、SiCL 4 、SiH 2 CL 2 SiH (SiH) 4 。
Advantageous effects
The application relates to a method for growing a silicon epitaxial wafer, which relates to the technical field of semiconductor materials, and comprises the steps of firstly removing a natural oxide film on the surface of a monocrystalline silicon wafer at the temperature of 650 ℃ or lower after a plurality of processing procedures are carried out, respectively forming oxygen atoms and monocrystalline silicon on the surface of the monocrystalline silicon wafer by using nitrous oxide after the natural oxide film is removed, wherein the formation of the oxygen atoms is carried out by exposing the monocrystalline silicon wafer to an atmosphere containing the nitrous oxide, the monocrystalline silicon is epitaxially grown at the temperature of 500 ℃ or higher and 700 ℃ or lower, and a plurality of oxygen atom layers and monocrystalline silicon layers are alternately formed when the forming procedures of the oxygen atoms and the monocrystalline silicon are carried out for a plurality of times, and finally, the silicon epitaxial layer is formed. The application reduces the problem that the temperature uniformity of the wafer is poor and particles are arranged on the surface of the wafer due to local heat loss of the wafer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for growing a silicon epitaxial wafer according to the present application;
FIG. 2 is a schematic view showing conditions for forming oxygen atoms and single crystal silicon in a method for growing a silicon epitaxial wafer according to the present application;
description of the embodiments
The present application will be more clearly described with reference to the following examples. The following examples will assist those skilled in the art in further understanding the function of the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, references to "a plurality of" in embodiments of the present application should be interpreted as two or more.
In the semiconductor field, epitaxial wafers are used as an important primary product for manufacturing various types of semiconductor devices, such as heterojunction field effect transistor (Heterojunction Field Effect Transistor) devices and Light-emitting diode (LED) devices. In the epitaxial growth process of the semiconductor substrate, when the thermal expansion coefficients of the substrate and the epitaxial layer are different, after the high-temperature growth process is finished, the shrinkage degree of the epitaxial layer and the substrate is different, so that the obtained epitaxial wafer is convex or concave, the warping degree of the epitaxial wafer is larger, and the subsequent preparation of the semiconductor device is difficult.
The silicon wafer is a grinding process for processing the outer peripheral surface of a single crystal silicon ingot grown by the czochralski method or the like, and is a slicing process for slicing the single crystal silicon ingot thinly into a wafer shape and polishing the wafer to the surface while improving the flatness. Contaminants on the wafer surface are removed after performing a lapping process, an etching process to remove damaged layers inside the wafer, and a polishing process to improve the surface mirror and flatness. Can be prepared by a cleaning process, an oxide film forming process, and a rapid thermal processing process, which will be described later.
In this embodiment, the silicon substrate used in the epitaxial silicon is carefully processed by cutting, grinding, polishing and other processes, and is subjected to severe cleaning and drying before epitaxial growth, but the surface is still damaged, contaminants, oxides and the like, and in order to improve the integrity of the epitaxial layer, in-situ chemical etching polishing should be performed in the reaction chamber before epitaxial growth to obtain a clean silicon surface, the common chemical etchant is dry HCL or HBr, and SiH is used 4 During epitaxial growth, due to SF 6 It has the features of no toxicity, non-selection, low temperature corrosion, etc. and is used as corrosion polishing agent.
As shown in fig. 1 and 2, the present application provides a method for growing a silicon epitaxial wafer, comprising the following steps:
step 1, a step of removing a natural oxide film on the surface of a monocrystalline silicon piece is performed at a temperature of 650 ℃.
Step 2, after the removal of the natural oxide film, forming oxygen atoms and single crystal silicon on the surface of the single crystal silicon wafer by using nitrous oxide, respectively, wherein,
the oxygen atoms are formed by exposing the single crystal silicon wafer to an atmosphere containing the nitrous oxide, and setting the partial pressure of the nitrous oxide to 10Pa or more and 10000Pa or less, and forming an oxygen atom layer at a temperature of 30 ℃ or more and 650 ℃ or less for baking for 5 to 10 minutes,
the monocrystalline silicon is formed by epitaxial growth by baking at a temperature of more than 500 ℃ and less than 700 ℃ for 8-15 minutes, the partial pressure of a silicon source is controlled to be more than 0.5Pa and less than 2000Pa, and the growth rate is controlled to be 1.30 mu m/min-1.70 mu m/min;
and 3, repeating the step 2, and alternately forming a plurality of oxygen atom layers and single crystal silicon layers by performing the step of forming oxygen atoms and single crystal silicon a plurality of times.
Specifically, when a silicon wafer is processed through a plurality of different processes before the natural oxide film is removed at a high temperature, the surface of the silicon wafer is severely contaminated, and generally the surface contamination of the silicon wafer can be roughly classified into three types: organic impurity contamination, particle contamination and metal ion contamination, wherein the organic impurity contamination can be removed by the dissolution of an organic reagent and the ultrasonic cleaning technology, and the particle contamination can be removed by a physical method by adopting a mechanical scrubbing or ultrasonic cleaning technology to remove particles with the particle diameter of more than or equal to 0.4 mu m, and megasonic waves can be utilized to remove particles with the particle diameter of more than or equal to 0.2 mu m; and similar metal ion pollution must be cleaned thoroughly by chemical means.
In this example, the main contaminant particles are mainly oxide films (hydrophilic at about 6 nm) formed on the silicon wafer surface by oxidation of H2O2, which are corroded by NH4OH, oxidation occurs immediately after corrosion, oxidation and corrosion are repeated, so that the particles adhered to the silicon wafer surface fall into the cleaning liquid along with the corrosion layer
The wafer is then slowly heated to a temperature, but preferably not exceeding 650 c, and then maintained at a sufficiently high temperature for a period of time and finally cooled at a suitable rate for eliminating residual stress, stabilizing dimensions, and reducing the propensity for deformation and cracking.
Further, in the step 1, the step of removing the natural oxide film is performed by using hydrofluoric acid or hydrofluoric acid vapor.
In this embodiment, when the natural oxide film on the surface is removed by cleaning with hydrofluoric acid or hydrofluoric acid vapor, the metal adhering to the natural oxide film is dissolved again in the cleaning liquid, and the DHF cleaning can suppress the formation of the natural oxide film, so that the metal such as Al, fe, zn, ni on the surface can be removed relatively easily. However, a part of noble metals such as Cu (oxidation-reduction potential is higher than hydrogen) dissolved in the cleaning liquid along with the natural oxide film adheres to the silicon surface, and DHF cleaning can remove metal hydroxide adhering to the natural oxide film
Since the oxidation-reduction potential E0 of al3+, zn2+, fe2+, ni2+ dane metal ions is-1.663V, -0.763V, -0.440V, and 0.250V is lower than the oxidation-reduction potential of h+ (e0=0.000v) and is in a stable ionic state, the silicon wafer is not substantially adhered to the silicon surface, and the silicon wafer after cleaning is cleaned by placing the silicon wafer in a DHF cleaning solution or an hf+h2o2 cleaning solution to which Cu is added, the Cu concentration on the silicon wafer surface is 1014 atoms/cm 2 by the DHF solution, and 1010 atoms/cm 2 by the hf+h2o2 cleaning solution, that is, the capability of removing metals by the hf+h2o2 cleaning solution is relatively strong, and for this reason, in recent years, hf+h2o2 is often used instead of DHF cleaning.
Further, in forming the oxygen atomic layer, nitrogen or a rare gas is used as a diluent gas in an atmosphere containing dinitrogen monoxide.
Further, the silicon source comprises SiHCL 3 、SiCL 4 、SiH 2 CL 2 SiH (SiH) 4 。
Specifically, the advantages and disadvantages of the above silicon sources are as follows: siHCL 3 With SiCl 4 The silicon source is in a liquid state at normal temperature, has high epitaxial growth reaction temperature, high growth speed, easy purification and safe use, and is a more general silicon source. SiH (SiH) 2 CL 2 With SiH 2 SiH in gas state at normal temperature 2 CL 2 The use is convenient, the application range is wide, but the reaction temperature is lower; siH (SiH) 4 The reaction temperature of (2) is also relatively low, and is a non-corrosive gas, but the two gas silicon sources have the problem of epitaxial defect caused by gas leakage.
In this example, since the concentration of oxygen in the crystalline silicon is limited by the solid solubility, the equilibrium solid solubility of the oxygen in the vicinity of the melting point of the silicon also gradually decreases with decreasing temperature of the crystalline silicon, and since segregation phenomenon occurs during the growth of the crystalline silicon, the oxygen concentration in the actual Czochralski silicon is expressed as high at the head and low at the tail. When silicon melt reacts with the quartz crucible to generate silicon monoxide (SiO) which enters the silicon melt, the SiO is transported to the surface of the melt by means of mechanical convection, natural convection and the like and volatilizes in a gas form. A small amount of SiO will dissolve in the molten silicon, exist in the liquid silicon in the form of oxygen atoms, and finally enter the czochralski silicon, and oxygen exists in the crystal silicon in a gap state, forming Si-O-Si bonding bonds. That is, oxygen in silicon exists in a supersaturated interstitial state in single crystal silicon, and when the silicon single crystal is heat-treated at 300 to 600 ℃, a donor effect related to oxygen is generated, and at this time, the resistivity of n-type crystal silicon is lowered and the resistivity of P-type crystal silicon is raised. When the donor effect is severe, even the P-type crystalline silicon can be converted into n-type crystalline silicon, and this oxygen-related donor is called "thermal donor". Studies have shown that thermal donors are double donors, i.e., each thermal donor can provide 2 electrons to the silicon substrate with energy level chalks at 0.06-0.07eV and 0.13-0.15eV below the conduction band. Therefore, when the concentration of thermal donors generated is high, the performance of the integrated circuit is directly affected.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (4)

1. The growth method of the silicon epitaxial wafer is characterized by comprising the following steps of:
step 1, a removal procedure of removing a natural oxide film on the surface of a monocrystalline silicon piece is carried out below 650 ℃;
step 2, after the removal of the natural oxide film, forming oxygen atoms and single crystal silicon on the surface of the single crystal silicon wafer by using nitrous oxide, respectively, wherein,
the oxygen atoms are formed by exposing the single crystal silicon wafer to an atmosphere containing the nitrous oxide, and setting the partial pressure of the nitrous oxide to 10Pa or more and 10000Pa or less, and forming an oxygen atom layer at a temperature of 30 ℃ or more and 650 ℃ or less for baking for 5 to 10 minutes,
the monocrystalline silicon is formed by epitaxial growth by baking at a temperature of more than 500 ℃ and less than 700 ℃ for 8-15 minutes, the partial pressure of a silicon source is controlled to be more than 0.5Pa and less than 2000Pa, and the growth rate is controlled to be 1.30 mu m/min-1.70 mu m/min;
and 3, repeating the step 2, and alternately forming a plurality of oxygen atom layers and single crystal silicon layers by performing the step of forming oxygen atoms and single crystal silicon a plurality of times.
2. The method of claim 1, wherein the step of removing the natural oxide film is performed by using hydrofluoric acid or hydrofluoric acid vapor in the step 1.
3. The method for growing a silicon epitaxial wafer according to claim 1, wherein the oxygen atomic layer is formed by using nitrogen or a rare gas as a diluent gas in an atmosphere containing dinitrogen monoxide.
4. The method for growing a silicon epitaxial wafer according to claim 1, wherein the silicon source comprises SiHCL 3 、SiCL 4 、SiH 2 CL 2 SiH (SiH) 4 。
CN202310584101.7A 2023-05-23 2023-05-23 Growth method of silicon epitaxial wafer Pending CN116798853A (en)

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