CN110010458B - Method for controlling surface morphology of semiconductor wafer and semiconductor wafer - Google Patents
Method for controlling surface morphology of semiconductor wafer and semiconductor wafer Download PDFInfo
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- CN110010458B CN110010458B CN201910257002.1A CN201910257002A CN110010458B CN 110010458 B CN110010458 B CN 110010458B CN 201910257002 A CN201910257002 A CN 201910257002A CN 110010458 B CN110010458 B CN 110010458B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
Abstract
The invention discloses a method for controlling the surface topography of a semiconductor wafer and the semiconductor wafer, wherein the method for controlling the surface topography of the semiconductor wafer comprises the following steps: carrying out single-side thinning treatment on the front side of the semiconductor wafer so as to form a convex surface with a high center and a low edge on the surface; and sequentially carrying out rough polishing treatment, middle polishing treatment and fine polishing treatment on two surfaces of the semiconductor wafer subjected to the single-side thinning treatment so as to obtain the semiconductor wafer. The method can effectively improve the surface evenness of the semiconductor wafer, reduce the thickness deviation, improve the processing level of the multi-piece single-side polishing process, and the processed semiconductor wafer can meet the requirement of the line width of an integrated circuit.
Description
Technical Field
The invention belongs to the field of semiconductor wafers, and particularly relates to a method for controlling the surface topography of a semiconductor wafer and the semiconductor wafer.
Background
Semiconductor wafers are typically prepared from a rod of silicon single crystal silicon, cut, round, and ground wire cut into single crystal rods having one or more flat surfaces for proper positioning of the wafer in subsequent processes. The ingot is then sliced into individual semiconductor wafers that are individually subjected to a number of processes that reduce the thickness of the wafers, remove damage caused by the slicing process, and form highly reflective surfaces. In a typical wafer shaping process, the circumferential edge of each wafer is rounded in order to reduce the risk of damaging the wafer during further processing. An abrasive process is then performed on both the front and back surfaces of the wafer using an abrasive agent (abrasive slurry) and a set of rotating abrasive discs. The grinding process reduces the thickness of the wafers to remove surface damage caused by dicing and to make the opposite side surfaces of each wafer flat and parallel. In addition, the wafer is also thinned on both sides instead of grinding on both sides. That is, a pair of grinding wheels (grindstones) are opposed to each other, and hold the wafer therebetween so as to be oriented vertically. The grinding wheel moves at a high speed relative to the wafer, and the wafer can obtain good flatness.
Upon completion of the grinding process, the wafer is subjected to an etching process to further reduce the thickness of the wafer and remove mechanical damage caused by the previous processing. One side surface of each wafer (often referred to as the "front side" of the wafer) is then polished with a polishing pad, a colloidal silica slurry (polishing slurry), and a chemical etchant to ensure that the wafer has a highly reflective, damage-free surface. Wafers are typically polished in a two-step process using rough polishing with a coarse abrasive and finish polishing with reduced non-specular reflected light (haze).
The patent semiconductor wafer processing method issued by MEMC electronic materials limited, patent No. CN1272222A, invented the use of grinding wheels to thin the front and back of the semiconductor wafer, and rapidly reduce the thickness of the semiconductor wafer. Then, the front and back surfaces of the semiconductor wafer are ground by the grinding mortar to further reduce the thickness of the semiconductor wafer. The front and back sides of the semiconductor wafer are then polished with a polishing fluid to a predetermined final thickness. This patent also describes the use of grinding wheels to thin the front side of the semiconductor wafer prior to polishing to reduce the polishing process time. Since the grinding wheel thins the semiconductor wafer, the removal rate of the wafer is relatively fast, so that the patent adopts a thinning technique for the purpose of reducing the double-side grinding processing time and the processing time of the polishing process for processing the semiconductor wafer before the double-side grinding process and before the polishing process. The grinding wheel thinning process has a relatively high removal rate for the semiconductor wafer, but also has an influence on a damaged layer, a nano-morphology and a profile of the semiconductor wafer. The deteriorated damage layer, nanotopography, and profile on the surface of the semiconductor wafer may generate deteriorated results on the polishing process, so that a wafer with good mirror surface, nanotopography, and profile cannot be obtained after the wafer is polished. The patent does not teach how the thinning technique controls the damage layer, nanotopography, profile of the wafer.
Patent of Siltronic company, Germany: a method for polishing a semiconductor wafer and a semiconductor wafer manufactured by the method, patent No. (CN 101148025B). The invention relates to a method for polishing a semiconductor wafer between an upper polishing plate and a lower polishing plate, wherein the semiconductor wafer is polished on both sides in a cavity of a rotary plate with the input of a polishing agent. The method comprises the following steps: double-side polishing the semiconductor wafer in a first polishing step, the double-side polishing ending with a negative excess, wherein the excess is the difference between the thickness of the semiconductor wafer after the first polishing step and the thickness of the turntable; the semiconductor wafer is double-side polished in a second polishing step in which less than 1 μm of material is polished off the side of the semiconductor wafer. The invention also relates to a semiconductor wafer made of silicon, having a polished front side and a polished back side, having a global front-side flatness expressed by an SBIRmax value of less than 100nm and a local front-side flatness in an edge region expressed by a PSFQR value of 35nm or less, wherein an edge exclusion of 2mm is always taken into account.
The first step of the german patent, SILTRONIC, controls the profile of a semiconductor wafer to make the wafer concave. And in the second step, the surface appearance of the wafer is controlled so as to achieve better flatness and ESFQR.
From the experience of the double-side polishing process, since the double-side polishing apparatus generally processes 5 to 15 wafers (depending on the size of the surface plate of the apparatus), it is difficult to control the shape (unevenness) of the double-side polishing by the bath type processing. Since double-side polishing typically removes 10-15 μm of polishing, the polishing rate is relatively slow, and each bath polishing time is typically 20-30 minutes. For long-time polishing, the surface topography of the silicon wafer is often difficult to control.
The semiconductor wafer is subjected to linear cutting, chamfering and double-sided grinding processes, and the surface of the silicon wafer obtains relatively good flatness. After the etching process, particularly the acid etching process, the flatness of the wafer surface is deteriorated, which is disadvantageous to the polishing process. Single-side and double-side polishing apparatuses such as: lapmaster, Speedfam, Fujikoshi, etc. put high demands on the flatness, surface damage layer, nanotopography, etc. of the wafer. Such as uniformity of flatness, thickness variation, etc.
The conventional polishing process adopts a three-step polishing process of rough polishing, fine polishing and mirror polishing, and a polishing pad needs to be corrected before polishing. So-called modified polishing pads are: the diamond grinding wheel polishes the polishing pad until the polishing pad meets the flatness requirement of the semiconductor wafer. If the polishing pad is not trimmed, a concave surface is formed on the surface of the silicon wafer. The polishing pad is generally made of polyurethane, and in the polishing process, polishing liquid enters the center of the silicon wafer from the edge of the silicon wafer, and in the initial stage, the polishing liquid has a high center grinding rate and a low edge grinding rate, so that the silicon wafer is concave and is recessed by 4-5 microns in the deterioration condition. Seriously affecting the flatness of the semiconductor wafer. Multiple revisions of the polishing pad not only reduce polishing efficiency, but also shorten the useful life of the polishing pad.
Accordingly, further improvements are needed in the current semiconductor wafer processing technology.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a method for controlling the surface topography of a semiconductor wafer and a semiconductor wafer, by which the surface flatness of the semiconductor wafer can be effectively improved, the thickness deviation can be reduced, the processing level of a multi-piece single-side polishing process can be improved, and the processed semiconductor wafer can meet the line width requirement of an integrated circuit.
According to one aspect of the invention, a method for controlling surface topography of a semiconductor wafer is provided, which, according to an embodiment of the invention, comprises:
performing single-side thinning treatment on the front side of the semiconductor wafer so as to form a convex surface which becomes thinner gradually from the center to the edge on the front side;
and sequentially carrying out rough polishing treatment, middle polishing treatment and fine polishing treatment on two surfaces of the semiconductor wafer subjected to the single-side thinning treatment so as to obtain the semiconductor wafer.
In addition, the method for controlling the surface topography of the semiconductor wafer according to the above embodiment of the present invention may further have the following additional technical features:
in some embodiments of the invention, the single-side thinning treatment adopts a single-side thinning machine with a worktable on which the A point is positioned between-1 μm and-10 μm, preferably between-1 μm and 3 μm, and the B point is positioned between-1 μm and-10 μm, preferably between-7 μm and 9 μm.
In some embodiments of the invention, the single-side thinning treatment uses a grinding wheel with a grain size of 0.5-4 μm, preferably a grinding wheel with a grain size of 0.5-1 μm.
In some embodiments of the invention, the wheel feed rate is 0.1 to 1 micron/second.
In some embodiments of the invention, the rotational speed of the grinding wheel is 1000-.
In some embodiments of the present invention, the rotation speed of the worktable is between 100 and 300 rpm.
In some embodiments of the invention, the convex surface has a center height of 3-5 μm.
In some embodiments of the present invention, the semiconductor wafer is at a flatness of 1 μm.
According to a second aspect of the invention, the invention also proposes a semiconductor wafer, which is obtained by processing according to an embodiment of the invention, by means of a method as described in the preceding embodiment.
Drawings
Fig. 1 is a schematic diagram of a single-sided thinning process according to one embodiment of the invention.
Fig. 2 is a schematic illustration of the surface topography of a semiconductor wafer after single-side thinning processing according to one embodiment of the present invention.
Fig. 3 is a graph of the results of cross section testing of a thinned semiconductor wafer, in accordance with one embodiment of the present invention.
FIG. 4 is a graph of results of testing a surface damage layer on a semiconductor wafer, in accordance with one embodiment of the present invention.
Figure 5 is a graph of the results of testing TTV, THK on a wafer after semiconductor polishing, in accordance with one embodiment of the present invention.
Fig. 6 is a graph showing the results of cross section testing of a semiconductor wafer, in accordance with one embodiment of the present invention.
FIG. 7 is a graph of the results of an SFQR test performed on a semiconductor wafer, in accordance with one embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The present invention has been completed based on the following findings of the inventors:
the traditional polishing process comprises three steps of rough polishing, fine polishing and mirror surface polishing, wherein a polishing pad adopted in the polishing process is generally made of polyurethane, polishing liquid enters the center of a semiconductor wafer from the edge of the semiconductor wafer in the polishing process, and the polishing speed of the center of the semiconductor wafer is high and the polishing speed of the edge is low in the initial stage. Therefore, the polishing pad needs to be continuously corrected before and during polishing, and if the polishing pad is not corrected, the surface of the semiconductor wafer becomes concave due to uneven polishing, and may be recessed by 3 to 5 μm in a deteriorated condition. Seriously affecting the flatness of the semiconductor wafer. Multiple revisions of the polishing pad not only reduce polishing efficiency, but also shorten the useful life of the polishing pad.
To this end, in accordance with one aspect of the present invention, there is provided a method for controlling the topography of a surface of a semiconductor wafer, the method comprising, in accordance with an embodiment of the present invention:
performing single-side thinning treatment on the front side of the semiconductor wafer so as to form a convex surface which becomes thinner gradually from the center to the edge on the front side,
and sequentially carrying out rough polishing treatment, middle polishing treatment and fine polishing treatment on two surfaces of the semiconductor wafer subjected to the single-side thinning treatment so as to obtain the semiconductor wafer.
In the method for controlling the surface morphology of the semiconductor wafer according to the embodiment of the invention, the front surface of the semiconductor wafer is subjected to single-surface thinning treatment in advance, so that the front surface forms a convex surface which becomes thinner gradually from the center to the edge. And then carrying out rough polishing treatment, middle polishing treatment and fine polishing treatment, and reducing or omitting a polishing pad correcting procedure in the polishing process, so that a concave surface formed by uneven grinding of the polishing pad can be used for offsetting a convex surface formed in advance by single-side thinning treatment. Therefore, the method of the embodiment of the invention combines the single-side thinning treatment and the polishing treatment, and the convex surface formed by the single-side thinning treatment is utilized to offset the concave surface formed by reducing or omitting the working procedure of correcting the polishing pad in the polishing treatment process, so as to achieve the purpose of improving the flatness of the semiconductor wafer and further meet the requirement of the line width of the integrated circuit. Therefore, the method of the present invention can effectively reduce or omit the process of correcting the polishing pad, prolong the service life of the polishing pad, and simultaneously, can significantly improve the polishing efficiency. More importantly, the method can effectively reduce the thickness deviation of the semiconductor wafer and improve the flatness. And further, the processing level of the multi-chip single-side polishing process is improved, and the requirement of the line width of the integrated circuit is met.
The method for controlling the surface topography of a semiconductor wafer according to the above-described embodiment of the present invention is described in detail below.
According to the embodiment of the invention, firstly, in order to form the convex surface on the surface of the semiconductor wafer, the invention adopts a single-side thinning treatment process. Specifically, the front side of the semiconductor wafer is subjected to single-side thinning treatment so as to form a convex surface with a high center and a low edge on the surface.
According to the specific embodiment of the invention, the single-side thinning treatment is carried out by using a DISCO 8 series thinning machine, so that the aim of accurate thinning can be improved.
Further, in order to effectively and accurately cancel the dishing formed on the surface of the semiconductor wafer due to the non-correction of the polishing pad, the inventors carefully screened and studied the single-side thinning and polishing process, and further obtained a convex surface with a predetermined height formed on the surface of the semiconductor wafer by adjusting the process parameters.
According to an embodiment of the present invention, the inventors adjusted the profile of a semiconductor wafer by adjusting the levelness of A, B points on the stage. Specifically, in the method according to the above embodiment of the present invention, the point a on the worktable of the single-side thinning machine used for the single-side thinning treatment is set to be-1 μm to-10 μm, and the point B is set to be-1 μm to-10 μm. During the single-side thinning treatment process, the semiconductor wafer is adsorbed on the turntable, the front side of the semiconductor wafer faces upwards, the point A is thinned, and then the point B is thinned. Thus, the surface of the semiconductor wafer can be effectively formed with a convex surface after thinning, and the convex surface has a proper center height and can be removed by further polishing treatment, thereby obtaining a semiconductor wafer with high surface flatness.
According to the specific example of the invention, the single-side thinning machine adopted by the single-side thinning treatment is preferably arranged at the position of-1 to-3 μm at the position of the A point and at the position of-7 to-9 μm at the position of the B point. A convex surface with the center height of 3-5 mu m can be formed on the front surface of the semiconductor wafer by accurately controlling the position of an A point and the position of a B point on a workbench of the single-side thinning machine. Further, by further performing polishing treatment, the highly convex surface can be completely removed, and a semiconductor wafer having high flatness can be obtained. Generally, when the thinning process is adjusted, if the central bulge of the silicon wafer is too high, for example, exceeds 5 micrometers, the position of B can be increased so as to meet the process requirement of the central bulge of the silicon wafer of 3-5 micrometers.
According to the embodiment of the invention, the single-side thinning treatment adopts a grinding wheel with the granularity of 0.5-4 mu m. Whereby the thinning effect can be effectively achieved. In addition, it is preferable to use a grinding wheel having a grain size of 0.5 to 1 μm (the number of grinding wheels is 6000-10000). Thus, the use of a grinding wheel having a relatively small diamond particle diameter can reduce the damage layer on the surface of the semiconductor wafer, and the damage layer is preferably less than 1 μm.
According to the embodiment of the invention, the feeding speed of the grinding wheel is further controlled to be 0.1-1 micron/second. Therefore, the morphology of the semiconductor wafer can be better controlled, and the damage layer on the surface of the semiconductor wafer can be reduced. The feeding speed does not affect the concave-convex shape of the silicon wafer, but only the roughness and the damaged layer of the surface of the silicon wafer. Preferably, the feed rate is 0.1 to 0.5 μm/sec. If the feeding speed is too high, the thickness is difficult to be reduced.
According to the embodiment of the invention, the rotation speed of the grinding wheel is controlled to be between 1000-3000rpm and the rotation speed of the worktable is controlled to be between 100-300 rpm. The method does not affect the concave-convex shape of the surface of the silicon wafer, and only affects the thinning rate of the silicon wafer. If too fast, the grinding wheel is prone to chipping.
In general, if no correction is made in the polishing process, a concave surface having a center depth of about 3 to 5 μm can be formed on the surface of the semiconductor wafer. By adopting the single-side thinning method and the process parameters of the embodiment of the invention, the convex surface with the center height of 3-5 μm can be exactly obtained, and the concave surface with the depth of about 3-5 μm generated by uncorrected polishing can be effectively offset. Therefore, the single-side thinning treatment is carried out on the surface of the semiconductor wafer in advance, so that the step of correcting the polishing pad in the subsequent polishing treatment process can be effectively omitted, the service life of the polishing pad is obviously prolonged, the polishing treatment efficiency can be obviously improved, and the polishing treatment operation difficulty is reduced. Most importantly, the method can also obviously improve the flatness of the surface of the semiconductor wafer, reduce the thickness deviation, improve the processing level of the multi-piece single-side polishing process and meet the requirement of the line width of the integrated circuit.
In the method according to the above embodiment of the present invention, in order to form a proper convex surface on the front surface of the semiconductor wafer, the positions of A, B two points on the table of the single-side thinning machine with respect to the reference surface, the type of the thinning machine, the grinding wheel grain size, the feed-down speed, the grinding wheel rotational speed, and the table rotational speed need to be considered in combination. By controlling the values of the above parameters within the range of values adopted in the above embodiment of the present invention, a convex surface having a center height of 3 to 5 μm and a surface damage layer of less than 0.2 μm can be obtained efficiently and accurately. Thus, the reduction or omission of the correction of the concave surface formed by the polishing pad during the polishing process can be effectively counteracted. Thereby obtaining a semiconductor wafer having a Total Thickness Variation (TTV) of less than 1 μm.
According to the specific embodiment of the invention, the two surfaces of the semiconductor wafer subjected to the single-side thinning treatment are subjected to rough polishing treatment, middle polishing treatment and fine polishing treatment in sequence, so as to obtain the semiconductor wafer.
According to the embodiment of the invention, in the course of rough polishing treatment, middle polishing treatment and fine polishing treatment of the semiconductor wafer, the number of times of polishing pad correction can be properly reduced, or the process of polishing pad correction can be completely omitted. The convex surface formed on the surface of the semiconductor wafer by the single-side thinning treatment is offset by the concave surface formed on the surface of the semiconductor wafer by reducing the polishing pad correction times or omitting the polishing pad correction process. Thereby obtaining a semiconductor wafer with high flatness and low thickness variation.
According to the specific embodiment of the invention, the process parameters adopted for rough polishing, middle polishing and fine polishing of the semiconductor wafer are the existing parameters. In the three-step polishing process described above, the number of times of polishing pad correction can be appropriately reduced or the polishing pad correction process can be completely omitted depending on the height of the convex surface formed on the surface of the semiconductor wafer.
According to the specific embodiment of the invention, NITTAHASS SUBA rough polishing pad and NITTHASS rough polishing solution are adopted in the rough polishing treatment; NITTAHASS middle polishing pads and middle polishing liquid are adopted in middle polishing treatment; in the fine polishing treatment, fujimi3950 fine polishing liquid and ssw1 fine polishing pads are adopted; the polishing device adopts a revasum single-sheet polishing device.
Therefore, by adopting the method for controlling the surface topography of the semiconductor wafer of the embodiment of the invention, the damaged layer, the nano topography and the surface topography of the semiconductor wafer can be accurately controlled. Specifically, for a 200mm silicon wafer, the surface of the semiconductor wafer is formed into a convex shape before the polishing process. After single-side single-wafer (SSP) polishing is completed, the silicon wafer can be changed into a concave type, so that the convex type before polishing can be offset, and the purpose of not correcting the polishing pad is achieved. The polishing pad correction is omitted, thereby extending the polishing pad life. In addition, the method can effectively reduce the damaged layer on the surface of the semiconductor wafer, for example, the damaged layer can be controlled to be less than 1 μm, the polishing time of the semiconductor wafer is reduced, and the polishing processing efficiency is improved.
According to a second aspect of the invention, the invention also proposes a semiconductor wafer, which is obtained by processing according to an embodiment of the invention, by means of a method as described in the preceding embodiment. Therefore, the semiconductor wafer has high flatness and small thickness deviation, and can meet the requirement of the line width of an integrated circuit.
In addition, the method for controlling the surface topography of the semiconductor wafer and the semiconductor wafer obtained by the method of the above embodiments of the present invention also have the following advantages:
(1) the method can accurately control the damage layer, the nanometer appearance and the surface appearance (concave-convex) of the semiconductor wafer, and is particularly suitable for semiconductor silicon wafers of 200mm and 300 mm.
(2) The polishing pad is not corrected, and the polishing efficiency is improved.
(3) For 200mm silicon wafer, multi-piece single-side polishing, such as Fujikoshi SPM-23 machine, SPEED FAM 50/59 series, has thickness deviation of less than 0.3-0.5 μm for silicon wafer, and flat surface. The flatness and thickness deviation of the surface of the silicon wafer are controlled, the processing level of the multi-piece single-side polishing process is improved, and the requirement of the line width of an integrated circuit is met.
(4) The damage layer on the surface of the silicon wafer is reduced to be 3-10 mu m, the polishing time of the silicon wafer is reduced, and the polishing processing efficiency is improved.
Examples
(1) The single-side thinning process mechanism is as follows:
and the grinding wheel is arranged on the spindle and can be vertically vertical to the spindle, and the grinding wheel is contacted with the semiconductor wafer A, B, C at three points, wherein A, C is the edge of the semiconductor wafer, and point B is the center point of the semiconductor wafer (see figure 1 below). The back of the semiconductor wafer is adsorbed by a vacuum table. When the spindle rotates the grinding wheel, the grinding wheel descends vertically and contacts with the surface of the semiconductor wafer. When the grinding wheel is in contact with the surface of the semiconductor wafer, the semiconductor wafer rotates around the central axis of the semiconductor wafer, and the surface of the semiconductor wafer can be uniformly thinned.
The principle of thinning and controlling the surface appearance of the semiconductor wafer is as follows:
1) the ironing machine basically has a turntable, which typically has a 2-3 table, with 1-2spindle shafts fitted with the turntable, each spindle shaft having an ironing wheel.
2) The levelness of the table (fig. 1) is generally as follows:
taking a virtual plane as a reference plane
Point A of 0 μm
B point is-11 +/-2 microns
Point C of-20 +/-2 microns
3) The topography of the thinned semiconductor wafer can be adjusted by adjusting the levelness of the A, B, C point on the platen, and in particular, several topographies such as those shown in fig. 2 can be obtained.
The purpose of the invention is to form a convex surface with high middle part and low edge on the surface of the thinned wafer by adjusting the position of A, B, C points, as shown in fig. 2 (2).
(2) And carrying out single-side thinning treatment on the front side of the semiconductor wafer.
The following single-side thinning treatment is carried out on a semiconductor wafer with the thickness of 200mm, and the specific process conditions are as follows:
1. DISCO 8 series single-side thinning machine;
2. the position of the point A on the workbench is-2 μm, and the position of the point B on the workbench is-8 μm; (the virtual plane is still chosen as the reference plane)
3. The grain size of the grinding wheel is 0.8 mu m (6000-mesh grinding wheel);
4. the grinding wheel feeding is carried out in two steps, and the descending speed is as follows: the first step of descent speed is 0.3 micron/second, the second step of descent speed is 0.1 micron/second;
5. the rotating speed of the grinding wheel is 3000 rpm;
6. the rotation speed of the worktable is 150rpm, and the semiconductor wafer is absorbed by the worktable;
7. and (6) cooling and processing.
By the single-side thinning treatment, the front surface of the semiconductor wafer is formed into a convex surface.
(3) Rough polishing treatment, middle polishing treatment and fine polishing treatment
And performing rough polishing, middle polishing and fine polishing on the semiconductor wafer with the convex surface formed on the surface through the single-side thinning treatment.
1) The rough polishing treatment process comprises the following steps:
the polishing pad is pretreated (warming, brush cleaning, etc.) and is not modified (diamond grinding wheel condition address)
| Rough polishing | ||||
| Step (ii) of | 1 | 2 | 3 | 4 |
| Time (seconds) | 3 | 0 | 250 | 15 |
| Pressure (PSI) | 0 | 0 | 50 | 0 |
| Pure water (ml) | 2000 | 0 | 0 | 200 |
| Chemical liquid 1 (milliliter) | 0 | 0 | 0 | 800 |
| Polishing solution 1 (milliliter) | 100 | 0 | 100 | 0 |
| Chemical liquid 2 (milliliter) | 0 | 0 | 115 | 0 |
| Polishing solution 2 (milliliter) | 0 | 0 | 0 | 0 |
| Fixed plate rotation speed (rpm) | 90 | 90 | 150 | 90 |
2) The middle polishing process comprises the following steps; the polishing pad is pretreated (warming, brush cleaning, etc.) and is not modified (diamond grinding wheel condition address)
| Middle throwing | ||||
| Step (ii) of | 1 | 2 | 3 | 4 |
| Time (seconds) | 3 | 0 | 220 | 15 |
| Pressure (PSI) | 0 | 0 | 40 | 0 |
| Pure water (ml) | 2000 | 0 | 0 | 200 |
| Chemical liquid 1 (milliliter) | 0 | 0 | 0 | 800 |
| Polishing solution 1 (milliliter) | 100 | 0 | 100 | 0 |
| Chemical liquid 2 (milliliter) | 0 | 0 | 115 | 0 |
| Polishing solution 2 (milliliter) | 0 | 0 | 0 | 0 |
| Fixed plate rotation speed (rpm) | 90 | 90 | 120 | 90 |
3) And (3) fine polishing process:
| fine polishing | ||||
| Step (ii) of | 1 | 2 | 3 | 4 |
| Time (seconds) | 3 | 0 | 220 | 15 |
| Pressure (PSI) | 0 | 0 | 40 | 0 |
| Pure water (ml) | 2000 | 0 | 0 | 200 |
| Chemical liquid 1 (milliliter) | 0 | 0 | 0 | 800 |
| Polishing solution 1 (milliliter) | 0 | 0 | 0 | 0 |
| Chemical liquid 2 (milliliter) | 0 | 0 | 0 | |
| Polishing solution 2 (milliliter) | 200 | 0 | 150 | 0 |
| Fixed plate rotation speed (rpm) | 90 | 90 | 120 | 90 |
(4) As a result:
1) and (3) performing ADE test cross section and wafer surface damage layer depth test on the surface of the semiconductor wafer subjected to thinning treatment in the step (2), and obtaining results shown in fig. 3 and 4.
2) The morphology of the semiconductor wafer obtained after the series of polishing treatments in step (4) was tested, and the results are shown in fig. 5 to 7.
(5) And (4) conclusion:
1) as shown in FIG. 3, the height of the center of the convex surface formed on the surface of the semiconductor wafer is 4 to 5 μm. As shown in fig. 4, the surface damage layer of the semiconductor wafer is below 0.2 μm.
2) FIG. 5 is an external view (similar to the 3D view) of a semiconductor wafer; FIG. 6 is a graph of thickness variation along a diameter direction; fig. 7 shows the thickness variation values in each area of a semiconductor wafer divided into a plurality of pieces. As can be seen from FIG. 6, the semiconductor wafer had a thickness variation of 0.30 μm, indicating that the flatness was good; as can be seen from fig. 7, the thickness variation per area is also very small, further illustrating the good flatness. Thus, as can be seen from fig. 5-7, the flatness of the semiconductor wafer can be effectively improved by the method according to the embodiment of the present invention.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (2)
1. A method for controlling surface topography of a semiconductor wafer, comprising:
performing single-side thinning treatment on the front side of the semiconductor wafer so as to form a convex surface which becomes thinner gradually from the center to the edge on the front side;
carrying out rough polishing treatment, middle polishing treatment and fine polishing treatment on two surfaces of the semiconductor wafer subjected to the single-side thinning treatment in sequence so as to obtain a semiconductor wafer,
wherein the position A on a workbench of a single-face thinning machine adopted by the single-face thinning treatment is set to be-1 mu m to-3 mu m; the point B is set to be-7 mu m to-9 mu m, the grinding wheel with the granularity of 0.5 to 1 mu m is adopted for the single-side thinning treatment, the feeding speed of the grinding wheel is 0.1 to 1 micron/second, the rotating speed of the grinding wheel is 1000-3000rpm, the rotating speed of the workbench is 100-300rpm, the central height of the convex surface is 3 to 5 mu m, the surface damage layer of the convex surface is lower than 0.2 mu m, and the total thickness deviation of the semiconductor wafer is less than 1 mu m.
2. A semiconductor wafer processed by the method of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910257002.1A CN110010458B (en) | 2019-04-01 | 2019-04-01 | Method for controlling surface morphology of semiconductor wafer and semiconductor wafer |
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| CN111098218A (en) * | 2019-12-31 | 2020-05-05 | 杭州中欣晶圆半导体股份有限公司 | Activation method for middle and fine polishing cloth of silicon wafer |
| CN112002630A (en) * | 2020-05-11 | 2020-11-27 | 中环领先半导体材料有限公司 | Process for improving surface flatness of large-diameter semiconductor silicon wafer through thinning |
| CN112259442A (en) * | 2020-09-11 | 2021-01-22 | 徐州鑫晶半导体科技有限公司 | Method and device for thinning double surfaces of wafer and storage medium |
| CN112757055B (en) * | 2021-01-07 | 2023-01-03 | 天津中环领先材料技术有限公司 | Large-size wafer thinning process |
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