CN117955446A

CN117955446A - Preparation method of semiconductor structure, semiconductor structure and electronic equipment

Info

Publication number: CN117955446A
Application number: CN202211296651.0A
Authority: CN
Inventors: 庞慰; 杨清瑞
Original assignee: Guangzhou Leyi Investment Co ltd
Current assignee: Guangzhou Leyi Investment Co ltd
Priority date: 2022-10-21
Filing date: 2022-10-21
Publication date: 2024-04-30
Also published as: WO2024083267A1

Abstract

The application provides a preparation method of a semiconductor structure, the semiconductor structure and electronic equipment, relates to the technical field of semiconductor manufacturing, and is used for solving the technical problems of poor performance uniformity and low yield of the semiconductor structure, and the preparation method of the semiconductor structure comprises the following steps: forming a heavily doped monocrystalline silicon layer on a substrate in an epitaxial growth mode; forming a cavity on the first bottom silicon layer; after the substrate is inverted, bonding the doped monocrystalline silicon layer with the first bottom silicon layer; removing at least part of the substrate to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer comprises a doped monocrystalline silicon layer having at least a partial thickness. The application can improve the controllability and accuracy of the doping concentration of the silicon layer in the semiconductor structure, thereby improving the performance consistency and yield of the semiconductor structure, in particular the consistency among chips, in batches and among batches of frequency temperature characteristics.

Description

Preparation method of semiconductor structure, semiconductor structure and electronic equipment

Technical Field

The present application relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure manufacturing method, a semiconductor structure, and an electronic device.

Background

Currently, silicon-based piezoelectric resonators are mostly manufactured by using a Silicon-on-Insulator (CSOI) substrate with a preset Cavity.

Generally, the preparation method of the CSOI substrate comprises the following steps: and (3) bonding the silicon wafer or the SOI silicon wafer serving as the device layer with the silicon substrate on which the cavity is etched after carrying out hot oxygen growth, or bonding the silicon wafer or the SOI silicon wafer serving as the device layer with the substrate on one side of the cavity, and thinning the silicon wafer or the SOI silicon wafer by mechanical grinding, chemical mechanical polishing technology, wet etching, dry etching and other methods, so that a thinner silicon device layer is finally left, thereby manufacturing the CSOI silicon wafer. In the above method, the initial characteristics of the device silicon layer (DEVICE LAYER) in the silicon wafer or SOI wafer determine the CSOI device layer characteristics, and in particular, the doping concentration determines the final frequency temperature characteristics of the silicon-based piezoelectric resonator. The silicon wafer or the Silicon On Insulator (SOI) silicon wafer is manufactured by adopting a Czochralski method, the accuracy of the doping concentration and the uniformity among wafers and among batches are poor, particularly, the accuracy and the uniformity are poorer under the condition that the doping concentration is close to or more than 10 ¹⁹cm^-3, and the sensitivity of the temperature coefficient to the doping concentration is stronger at the moment, so that the uniformity among wafers, among batches and among batches of the frequency temperature coefficient of the piezoelectric silicon-based resonator manufactured by adopting the CSOI is poor, thereby leading to low device yield and high cost. On the other hand, the doping concentration of the silicon wafer manufactured by the Czochralski method is generally difficult to reach more than 10 ²⁰cm^-3, so that the usable range of the frequency temperature coefficient of the silicon is limited, and the zero temperature drift characteristic of the piezoelectric driving silicon-based resonator in certain modes is difficult to realize.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide a method for manufacturing a semiconductor structure, and an electronic device, so as to solve the technical problems of poor performance uniformity (especially poor uniformity of frequency-temperature characteristics) and low yield of the semiconductor structure, and improve the performance uniformity of the semiconductor structure, thereby improving the yield of the semiconductor structure, reducing the cost of the device, and simultaneously improving the available doping concentration range and the corresponding available frequency-temperature coefficient range of the silicon layer in the semiconductor structure.

In order to achieve the above object, the embodiment of the present application provides the following technical solutions:

a first aspect of an embodiment of the present application provides a method for manufacturing a semiconductor structure, including:

forming a heavily doped monocrystalline silicon layer on a substrate in an epitaxial growth mode;

forming a cavity on the first bottom silicon layer;

bonding the doped monocrystalline silicon layer to the first underlying silicon layer after inverting the substrate;

Removing at least part of the substrate to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer at least comprises a portion of the thickness of the doped monocrystalline silicon layer.

In some alternative embodiments, the step of forming the heavily doped monocrystalline silicon layer on the substrate by epitaxial growth specifically includes:

The doped monocrystalline silicon layer is formed on the substrate with a doping concentration that varies with growth thickness.

In some alternative embodiments, the doped monocrystalline silicon layer has at least two sub-doped monocrystalline silicon layers arranged one above the other in the growth thickness direction, different ones of the sub-doped monocrystalline silicon layers having different doping concentrations and/or different dopants.

In some alternative embodiments, the doping concentration of each sub-doped monocrystalline silicon layer is sequentially arranged from large to small or from small to large along the growth thickness direction.

In some alternative embodiments, the doping concentration of the doped monocrystalline silicon layer varies continuously with the growth thickness.

In some alternative embodiments, the doping concentration of the doped monocrystalline silicon layer is greater than the substrate doping concentration, and the doped monocrystalline silicon layer is an N-type heavily doped monocrystalline silicon layer or a P-type heavily doped monocrystalline silicon layer; wherein the doping concentration of the doped monocrystalline silicon layer is greater than or equal to 10 ¹⁹cm^-3.

In some alternative embodiments, the doped monocrystalline silicon layer has a doping concentration greater than or equal to 10 ²⁰cm^-3.

In some alternative embodiments, after the inverting the substrate and before the bonding of the first bottom silicon layer, the method further comprises:

A thermal oxide layer is formed on at least one of the doped monocrystalline silicon layer and the first base silicon layer.

In some alternative embodiments, the substrate includes a first top silicon layer, and the doped monocrystalline silicon layer is formed on a surface of the first top silicon layer.

In some alternative embodiments, the removing at least a portion of the substrate specifically includes: thinning the thickness of the first top silicon layer; or removing the first top silicon layer.

In some alternative embodiments, the forming a heavily doped monocrystalline silicon layer on the substrate by epitaxial growth specifically includes:

and epitaxially growing a heavily doped single-crystal silicon layer on the second top silicon layer of the SOI substrate for the SOI substrate comprising the second top silicon layer, the buried oxide layer and the second bottom silicon layer which are sequentially stacked.

In some alternative embodiments, the removing at least a portion of the substrate specifically includes:

sequentially removing the second bottom silicon layer and the buried oxide layer; or sequentially removing the second bottom silicon layer, the oxygen-buried layer and at least part of the second top silicon layer.

and removing all the substrate and part of the doped monocrystalline silicon layer.

In some alternative embodiments, after forming the heavily doped monocrystalline silicon layer on the substrate by epitaxial growth, or after forming the thin film silicon layer on the first base silicon layer, the method further comprises:

Doping the doped monocrystalline silicon layer or the thin film silicon layer by an ion implantation or thermal diffusion mode; and/or

And carrying out high-temperature annealing on the doped monocrystalline silicon layer or the thin film silicon layer.

In some optional embodiments, if the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer is less than the preset doping concentration, doping the doped monocrystalline silicon layer or the thin film silicon layer by ion implantation or thermal diffusion, or performing high-temperature annealing on the doped monocrystalline silicon layer or the thin film silicon layer to increase the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer; and if the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer is larger than the preset doping concentration, carrying out high-temperature annealing on the doped monocrystalline silicon layer or the thin film silicon layer so as to reduce the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer.

In some alternative embodiments, after removing at least a portion of the substrate to form a thin film silicon layer on the first bottom silicon layer, the method further comprises:

and forming a piezoelectric resonator layer on the surface of the thin film silicon layer.

In some alternative embodiments, after the forming the piezoelectric resonator layer on the surface of the thin film silicon layer, the method further includes:

An upper silicon cap is bonded to the piezoelectric resonator layer.

A second aspect of an embodiment of the present application provides a semiconductor structure, including:

A first bottom silicon layer having a cavity;

the thin film silicon layer is formed on the surface of the first bottom silicon layer through bonding and at least comprises a doped monocrystalline silicon layer which is formed in a part through an epitaxial growth mode, the doped monocrystalline silicon layer is positioned at a position, close to the first bottom silicon layer, in the thin film silicon layer, and the doped monocrystalline silicon layer is a heavy doped layer.

In some alternative embodiments, the doped monocrystalline silicon layer is an N-type heavily doped monocrystalline silicon layer or a P-type heavily doped monocrystalline silicon layer; and the doping concentration of the doped monocrystalline silicon layer is greater than or equal to 10 ¹⁹cm^-3.

In some alternative embodiments, the doping concentration of the doped monocrystalline silicon layer varies with the growth thickness.

In some alternative embodiments, a thermal oxide layer is further included, the thermal oxide layer disposed between the first bottom silicon layer and the doped monocrystalline silicon layer.

In some alternative embodiments, the thermal oxide layer covers a side wall of the cavity opposite the doped monocrystalline silicon layer.

In some alternative embodiments, the thermal oxide layer covers a side surface of the doped monocrystalline silicon layer corresponding to the cavity.

In some alternative embodiments, the thermal oxide layer covers a wall of the cavity and a side surface of the doped monocrystalline silicon layer corresponding to the cavity.

In some alternative embodiments, further comprising:

A piezoelectric resonator layer formed on the surface of the thin film silicon layer;

And a silicon cap bonded to the piezoelectric resonator layer.

In some alternative embodiments, the piezoelectric resonator layer includes a piezoelectric layer and a top electrode sequentially stacked on the surface of the thin film silicon layer.

In some alternative embodiments, the piezoelectric resonator further comprises a bottom electrode disposed on a side of the piezoelectric layer facing away from the top electrode.

In some optional embodiments, a dielectric layer is disposed between the bottom electrode and the thin film silicon layer, where the dielectric layer is at least one of silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride.

In some alternative embodiments, the piezoelectric layer is any one of single crystal aluminum nitride, polycrystalline aluminum nitride, rare earth doped aluminum nitride; wherein the rare earth doped aluminum nitride comprises at least one of scandium, yttrium, magnesium, titanium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, lutetium.

In some alternative embodiments, a first bonding layer is disposed between the upper silicon cap and the piezoelectric layer.

In some alternative embodiments, the upper silicon cap includes a substrate and a second bonding layer disposed on a side of the substrate facing the first bonding layer;

The substrate is also provided with a conductive through hole penetrating through the substrate and the second bonding layer, one side of the upper silicon cap, which is away from the second bonding layer, is provided with a metal pin electrically connected with the conductive through hole, and one side of the substrate, which faces the piezoelectric resonator layer, is also provided with a getter layer.

In some alternative embodiments, the first bonding layer and the second bonding layer are both metal layers.

In some alternative embodiments, a silicon dioxide layer is disposed between the metal pins and the conductive vias and the substrate.

A third aspect of the embodiments of the present application provides an electronic device, including the semiconductor structure provided in the foregoing embodiments.

The preparation method of the semiconductor structure provided by the embodiment of the application comprises the following steps: forming a heavily doped monocrystalline silicon layer on a substrate in an epitaxial growth mode; forming a cavity on the first bottom silicon layer; after the substrate is inverted, bonding the doped monocrystalline silicon layer with the first bottom silicon layer; removing at least part of the substrate to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer comprises a doped monocrystalline silicon layer having at least a partial thickness. In the scheme, the heavily doped monocrystalline silicon layer is formed on the substrate in an epitaxial growth mode, so that the doping concentration of the silicon layer in the semiconductor structure can be improved, the doping concentration is adjustable and controllable, and the performance consistency and the yield of the semiconductor structure can be improved.

The construction of the present application and other objects and advantages thereof will be more readily understood from the description of the preferred embodiment taken in conjunction with the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of a doped monocrystalline silicon layer formed over a substrate in accordance with one embodiment of the present application;

FIG. 3 is a schematic cross-sectional view of a cavity formed in a first bottom silicon layer according to one embodiment of the present application;

FIG. 4 is a schematic cross-sectional view of a thermal oxide layer formed on a doped monocrystalline silicon layer in accordance with an embodiment of the present application;

FIG. 5 is a schematic cross-sectional view illustrating a thermal oxide layer formed on a first bottom silicon layer according to an embodiment of the present application;

FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to one embodiment of the present application;

FIG. 7a is a schematic cross-sectional view of another embodiment of a semiconductor structure according to the present application;

FIG. 7b is a schematic cross-sectional view of another embodiment of a semiconductor structure according to the present application;

FIG. 8 is a schematic cross-sectional view of a doped monocrystalline silicon layer and a first underlying silicon layer having a thermal oxide layer formed thereon in accordance with an embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of the flip chip of FIG. 1 after bonding with FIG. 5;

FIG. 10 is a schematic cross-sectional view of FIG. 9 with a portion of the substrate removed;

FIG. 11 is a schematic cross-sectional view of the substrate of FIG. 9 after removal of the entire substrate;

FIG. 12 is a schematic cross-sectional view of the doped monocrystalline silicon layer of FIG. 11 grown with graded doping concentrations;

FIG. 13 is a schematic cross-sectional view of the doped monocrystalline silicon layer of FIG. 11 grown with continuous variation of doping concentration;

FIG. 14 is a schematic cross-sectional view of the piezoelectric resonator layer formed on FIG. 11;

FIG. 15a is a schematic cross-sectional view of one configuration of the package on the silicon cap of FIG. 14;

FIG. 15b is a schematic cross-sectional view of another structure of the package of FIG. 14 with a silicon cap thereon;

fig. 16 is a schematic top view showing a structure of a tuning fork of a vibration mode in a semiconductor device according to an embodiment of the present application;

Fig. 17 is a schematic top view of another structure of a tuning fork of a vibration mode in a semiconductor device according to an embodiment of the present application;

FIG. 18 is a schematic cross-sectional view of a doped monocrystalline silicon layer formed over an SOI substrate in accordance with another embodiment of the present application;

Fig. 19 is a schematic cross-sectional structure of a thermal oxide layer formed on the basis of fig. 18;

FIG. 20 is a schematic cross-sectional view showing a thermal oxide layer formed only on a doped monocrystalline silicon layer in accordance with another embodiment of the present application;

FIG. 21 is a schematic cross-sectional view of a thermal oxide layer formed on both a doped monocrystalline silicon layer and a first underlying silicon layer in accordance with another embodiment of the application;

FIG. 22 is a schematic cross-sectional view illustrating a thermal oxide layer formed only on a first bottom silicon layer according to another embodiment of the present application;

FIG. 23 is a schematic cross-sectional view of another embodiment of the present application after removing the second top silicon layer from the SOI substrate;

FIG. 24 is a schematic cross-sectional view of another embodiment of the present application after removing the buried oxide layer from the SOI substrate;

Fig. 25 is a schematic cross-sectional view of another embodiment of the present application after removing the second bottom silicon layer from the SOI substrate.

Reference numerals:

101-a substrate; 1011-a second bottom silicon layer; 103-a second top silicon layer;

102-a first bottom silicon layer; 200-doping a monocrystalline silicon layer; 201-a first sub-doped monocrystalline silicon layer;

202-a second sub-doped monocrystalline silicon layer; 203-a third sub-doped monocrystalline silicon layer;

301. 302-a thermal oxide layer; 400-burying an oxygen layer; 500-a piezoelectric resonator layer;

501-top electrode; 502-a piezoelectric layer; 503-bottom electrode;

600-a first bonding layer; 700-capping silicon; 701-substrate;

702-a second bonding layer; 703-metal pins; 704-conductive vias;

705-getter layer; 801-a first dielectric layer; 802-a second dielectric layer.

Detailed Description

As described in the background art, the silicon wafer used as the device layer or the device silicon layer of the SOI in the conventional CSOI fabrication process is generally fabricated by adopting the czochralski method, and when the doping concentration is close to 1x10 ¹⁹cm^-3, the control accuracy of the doping concentration is poor, so that the performance consistency of the silicon wafers and batch pieces is poor, and the fabricated devices have poor performance consistency (especially the consistency of frequency-temperature characteristics) and low yield. On the other hand, the doping concentration of the silicon wafer manufactured by the Czochralski method is generally difficult to reach more than 10 ²⁰cm^-3, so that the frequency temperature coefficient range of silicon is limited, and the zero temperature drift characteristic of the piezoelectric driving silicon-based resonator in certain modes is difficult to realize.

In order to solve the above problems, embodiments of the present application provide a method for manufacturing a semiconductor structure, and an electronic device, in which in the method for manufacturing a semiconductor structure, a heavily doped monocrystalline silicon layer is formed on a substrate by epitaxial growth, so that the doping concentration of the heavily doped monocrystalline silicon layer is easily controlled to be 10 ¹⁹cm^-3 or even 10 ²⁰cm^-3 or more, and meanwhile, the accuracy of the doping concentration of the heavily doped monocrystalline silicon layer can be better controlled. Therefore, the device silicon layer with high-concentration doping and good doping concentration adjustability and controllability can be realized, so that the final frequency temperature characteristic of the semiconductor structure, and the consistency and yield of the frequency temperature characteristic in-chip, inter-chip, in-batch and inter-batch can be improved.

In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions of the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The semiconductor structure provided by the embodiment of the application can be a resonator, a transducer, a driver and the like, and in the application, the semiconductor structure is taken as the resonator (for example, a piezoelectric driving silicon-based resonator) for explanation.

Example 1

Fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the application. Referring to fig. 1, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including:

step S101: and forming a heavily doped monocrystalline silicon layer on the substrate by epitaxial growth.

It will be appreciated that, as shown in fig. 2, before forming the heavily doped monocrystalline silicon layer 200 on the substrate 101 by epitaxial growth, the method further comprises: a substrate 101 is provided. Wherein the substrate 101 may provide a support foundation for structural layers on the substrate 101. The substrate 101 may be made of a crystalline semiconductor material, for example, the substrate 101 may be a silicon (Si) substrate, the substrate 101 may also be a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or the like, where the substrate 101 may be a single-layer structure or a multi-layer composite structure, and the adaptive design is specifically performed according to the actual requirement, which is not limited herein, and in this embodiment, the substrate 101 is described as single-crystal silicon.

In some embodiments, the heavily doped monocrystalline silicon layer 200 is formed on the substrate 101 by epitaxial growth. It can be appreciated that while the monocrystalline silicon layer is grown on the substrate 101 by epitaxy, doping the epitaxially grown silicon layer with a silicon layer, the doping element of the doped monocrystalline silicon layer 200 may be B, as or P, etc.; the doping type may be N-type or P-type (the P-type doping dopant is typically boron, or may be a group iii element such as aluminum, gallium, or indium; the N-type doping dopant is typically phosphorus or a group v element such as arsenic), for example, in fig. 2, a heavily N-type (the doping dopant is phosphorus) doped (the doping concentration is greater than 10 ¹⁹cm^-3) doped monocrystalline silicon layer 200 is grown on the surface of the substrate 101. Typically, the doping concentration of the doped monocrystalline silicon layer is greater than the doping concentration of the substrate.

Further, in the epitaxially formed doped monocrystalline silicon layer, the doping concentration may be further increased by ion implantation or thermal diffusion, or the distribution characteristics of the dopant in the silicon layer may be changed by high temperature annealing (around 1000 ℃).

Step S102: a cavity is formed in the first bottom silicon layer.

Wherein the first bottom silicon layer 102 provides a supporting foundation for the structural layer on the first bottom silicon layer 102; the first bottom silicon layer 102 may be made of a crystalline semiconductor material, for example, the material of the first bottom silicon layer 102 may be silicon (Si), single crystal silicon, silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), gallium arsenide, gallium nitride, etc., and in the embodiment of the present application, the material of the first bottom silicon layer 102 is single crystal silicon.

In some embodiments, a cavity is formed on the first bottom silicon layer 102, where the cavity may be a recessed structure that forms an opening on a surface of the first bottom silicon layer 102, as shown in fig. 3, and the cavity on the first bottom silicon layer 102 may be formed by a dry etching or wet etching process, for example, the depth of the cavity etched on the surface of the first bottom silicon layer 102 may be between several micrometers and hundred micrometers, for example: 5 μm, 50 μm, 100 μm, etc., wherein the specific depth of the cavity may be adaptively designed according to the actual requirements of the semiconductor structure, without specific limitation.

In some embodiments, after forming the heavily doped monocrystalline silicon layer 200 on the substrate 101 by epitaxial growth and forming the cavity on the first base silicon layer 102, further comprises:

A thermal oxide layer is formed on at least one of the doped monocrystalline silicon layer 200 and the first base silicon layer 102. It will be appreciated that the thermal oxide layer 301 may be grown on the surface of the doped monocrystalline silicon layer 200 on the side facing away from the substrate 101, and as shown in fig. 4, by growing the thermal oxide layer 301 on the surface of the doped monocrystalline silicon layer 200, the monocrystalline silicon of the doped monocrystalline silicon layer 200 may be made to have a positive temperature coefficient, thus having a temperature compensation effect on the doped monocrystalline silicon layer 200; of course, the thermal oxide layer 302 may also be formed by growing on the side of the first bottom silicon layer 102 having the cavity, as shown in fig. 5, so that the thermal oxide layer 302 may serve as an adhesion layer, so that the first bottom silicon layer 102 has good adhesion with the substrate 101 during the subsequent bonding process. The material of the thermal oxide layer may be silicon dioxide (SiO ₂).

Step S103: after inverting the substrate, the doped monocrystalline silicon layer is bonded to the first underlying silicon layer.

As shown in fig. 6, the doped monocrystalline silicon layer 200 may be directly bonded to the first base silicon layer 102;

Or as shown in fig. 7a to 9, after forming a thermal oxide layer on at least one of the doped monocrystalline silicon layer 200 and the first base silicon layer 102, the substrate 101 is flip-chip mounted on the first base silicon layer 102 and bonded to the first base silicon layer 102.

In fig. 7a, a thermal oxide layer 301 is formed only on the surface of the doped monocrystalline silicon layer 200, a thermal oxide layer is not formed on the surface of the first bottom silicon layer 102, and after the thermal oxide layer 301 is formed on the doped monocrystalline silicon layer 200, the substrate 101 is flipped over the first bottom silicon layer 102 and bonded to the first bottom silicon layer 102, so that the thermal oxide layer 301 on the surface of the doped monocrystalline silicon layer 200 has a temperature compensation effect on the doped monocrystalline silicon layer 200 while improving the adhesion between the doped monocrystalline silicon layer 200 and the first bottom silicon layer 102, so that the temperature coefficient of silicon of the doped monocrystalline silicon layer 200 is positive.

In fig. 7b, a silicon dioxide layer is grown on the surface of the doped monocrystalline silicon layer 200 and patterned to have its edges fall inside the cavity of the first underlying silicon layer 102, while still achieving bonding between the two prepared substrates by silicon-silicon bonding.

In fig. 8, a thermal oxide layer is grown on both the surface of the doped monocrystalline silicon layer 200 and the first base silicon layer 102, and after the thermal oxide layer is formed, the substrate 101 is flip-chip mounted on the first base silicon layer 102 and bonded to the first base silicon layer 102. In this way, the thermal oxide layer has a temperature compensation effect on the doped monocrystalline silicon layer 200 while improving the adhesiveness between the doped monocrystalline silicon layer 200 and the first bottom silicon layer 102, so that the temperature coefficient of silicon of the doped monocrystalline silicon layer 200 is positive.

In fig. 9, the thermal oxide layer 302 is formed only on the first bottom silicon layer 102, the thermal oxide layer is not formed on the doped monocrystalline silicon layer 200, and then the substrate 101 is flip-chip mounted on the first bottom silicon layer 102 and bonded to the first bottom silicon layer 102, so that the thermal oxide layer 302 can improve the adhesion between the first bottom silicon layer 102 and the doped monocrystalline silicon layer 200.

It will be appreciated that when the first bottom silicon layer 102 is not bonded to the substrate 101 after the cavity is formed thereon, the cavity on the first bottom silicon layer 102 is an open cavity, and when the substrate 101 is flip-chip bonded to the first bottom silicon layer 102, the substrate 101 blocks the opening of the cavity, so that a closed cavity is formed between the substrate 101 and the first bottom silicon layer 102.

Step S104: removing at least part of the substrate to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer comprises a doped monocrystalline silicon layer having at least a partial thickness.

It can be appreciated that after the substrate 101 is flip-chip bonded to the first underlying silicon layer 102, a portion of the substrate 101 is removed, i.e., the thickness of the substrate 101 is reduced; or the entire substrate 101 and part of the doped monocrystalline silicon layer 200 are removed.

In some embodiments, the substrate 101 includes a first top silicon layer, the doped monocrystalline silicon layer 200 is formed on a surface of the first top silicon layer, and at least a portion of the substrate 101 is removed, i.e., the thickness of the first top silicon layer is thinned or the entire first top silicon layer is removed.

In fig. 10, a portion of the first top silicon layer is removed, specifically, a mechanical Polishing and/or Chemical Mechanical Polishing (CMP) process may be used to thin the thickness of the first top silicon layer, but is not limited to the above-described process method, so that a thin first top silicon layer remains on the surface of the doped monocrystalline silicon layer 200, and this thin first top silicon layer and the doped monocrystalline silicon layer 200 form a thin film silicon layer used as a device layer.

In fig. 11, the entire first top silicon layer is removed, for example, the first top silicon layer may be removed by continuing the cmp process on the basis of fig. 10, exposing the doped monocrystalline silicon layer 200; the first top silicon layer may also be removed by a dry or wet etch process to expose the doped monocrystalline silicon layer 200, at which time the remaining doped monocrystalline silicon layer 200 forms a thin film silicon layer that serves as a device layer.

On the formed new substrate, the average doping concentration of the thin film silicon layer can be calculated by measuring the square resistance of the thin film silicon layer or other methods, if the doping concentration is lower than the preset doping concentration, the doping concentration can be increased by methods such as thermal diffusion, ion implantation, high-temperature annealing and the like, and if the doping concentration is higher than the preset doping concentration, the effective doping ion number can be changed by methods such as high-temperature annealing and the like so as to reduce the doping concentration. Note that the specific process parameters (e.g., rate of rise, time of heating, rate of fall, number of cycles, etc.) of the high temperature annealing process used in increasing the doping concentration and decreasing the doping concentration are set differently, and that the specific process parameters of the annealing process are set differently for different preset doping concentrations.

In addition, the doping concentration of the heavily doped monocrystalline silicon layer 200 formed on the substrate 101 by epitaxial growth may vary with the growth thickness, so that the doping concentration of the doped monocrystalline silicon layer 200 may be adjusted and controlled according to the requirements of specific devices on the doping concentration.

In some embodiments, the doped monocrystalline silicon layer 200 has at least two sub-doped monocrystalline silicon layers stacked in a growth thickness direction, different sub-doped monocrystalline silicon layers having different doping concentrations. As illustrated in fig. 12, the doped monocrystalline silicon layer 200 includes three sub-doped monocrystalline silicon layers stacked in a growth thickness direction, and the three sub-doped monocrystalline silicon layers may be represented by a first sub-doped monocrystalline silicon layer 201, a second sub-doped monocrystalline silicon layer 202, and a third sub-doped monocrystalline silicon layer 203, respectively, wherein a thermal oxide layer 301 is grown on a surface of the first sub-doped monocrystalline silicon layer 201, and it is understood that doping concentrations of the first sub-doped monocrystalline silicon layer 201, the second sub-doped monocrystalline silicon layer 202, and the third sub-doped monocrystalline silicon layer 203 are different.

In some embodiments, the doping concentrations of the sub-doped monocrystalline silicon layers are sequentially arranged from large to small along the growth thickness direction. For example, the doping concentration may be arranged from the first sub-doped monocrystalline silicon layer 201 to the third sub-doped monocrystalline silicon layer 203 sequentially from large to small.

Alternatively, the doping concentrations may be arranged from the third sub-doped monocrystalline silicon layer 203 to the first sub-doped monocrystalline silicon layer 201 sequentially from large to small, and the doping concentrations are specifically set adaptively according to the requirement of the doping concentration, which is not particularly limited herein.

It can be appreciated that in the above-mentioned scheme, by making the doping concentration of each sub-doped monocrystalline silicon layer change in a gradient manner, the thickness and the doping concentration of each sub-doped monocrystalline silicon layer can be controlled, so that the doping concentration of the doped monocrystalline silicon layer 200 can be flexibly and accurately controlled, so that the doping concentration of the doped monocrystalline silicon layer 200 can reach the target doping concentration, for example, the target doping concentration can be more than 1×10 ¹⁸cm^-3, and the preferred range can be 1×10 ¹⁹ to 10 ²¹cm^-3, but not limited to the range, and can also be a higher doping concentration range, so that the semiconductor structure can realize zero temperature drift characteristics, that is, the temperature coefficient can be close to zero, the temperature performance is more stable, and the performance of the semiconductor structure can be improved, and the yield of the semiconductor structure can be improved.

In other embodiments, the doping concentration of the doped monocrystalline silicon layer 200 may be continuously varied with the growth thickness, as shown in fig. 13, it may be appreciated that by continuously varying the doping concentration of the doped monocrystalline silicon layer 200 with the growth thickness, so that the doping concentration of the doped monocrystalline silicon layer 200 can reach the target doping concentration, the semiconductor structure can achieve zero temperature drift characteristics, i.e., the temperature coefficient can be close to zero, the temperature performance is more stable, and thus the performance of the semiconductor structure can be improved, thereby improving the yield of the semiconductor structure.

Step S105: a piezoelectric resonator layer is formed on the surface of the doped monocrystalline silicon layer, and an upper silicon cap is bonded to the piezoelectric resonator layer.

It will be appreciated that after the substrate 101 is flip-chip bonded to the first bottom silicon layer 102, a first top silicon layer may be remained on the surface of the doped monocrystalline silicon layer 200, or the first top silicon layer may be completely removed, including the doped monocrystalline silicon layer 200, and in the embodiment of the present application, taking the removal of all the first top silicon layer as an example, as shown in fig. 14, a layer of the piezoelectric resonator 500 may be formed on the surface of the doped monocrystalline silicon layer 200 by physical vapor deposition, chemical vapor deposition, epitaxial growth, or other processes.

In some embodiments, the bottom electrode 503, the piezoelectric layer 502, and the top electrode 501 may be sequentially deposited on the surface of the doped monocrystalline silicon layer 200, that is, the bottom electrode 503, the piezoelectric layer 502, and the top electrode 501 are stacked along the thickness direction of the doped monocrystalline silicon layer 200, and the bottom electrode 503 is located on the doped monocrystalline silicon layer 200, so that the bottom electrode 503, the piezoelectric layer 502, and the top electrode 501 together form the piezoelectric resonator 500 layer, and then etched to form the final resonator structure.

The material of the bottom electrode 503 may be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a composite or alloy thereof; the material of the piezoelectric layer 502 may be aluminum nitride (unlike single crystal aluminum nitride mentioned later, here, aluminum nitride formed by a physical vapor deposition or the like is polycrystalline aluminum nitride), zinc oxide, PZT or the like and a rare earth element doped material containing the above materials in a certain atomic ratio; the material of the top electrode 501 may be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a composite of the above metals or an alloy thereof.

In other embodiments (not shown in the figures), the bottom electrode 503 may be omitted, i.e., the piezoelectric layer 502 and the top electrode 501 are formed directly on the surface of the doped monocrystalline silicon layer 200; in this case, the piezoelectric layer may be a single crystal AlN material or a single crystal-doped AlN material (the doping element may be the rare earth element described above) formed by epitaxial growth.

After the surface deposition of the doped monocrystalline silicon layer 200 to form the piezoelectric resonator, the previously prepared upper silicon cap 700 is bonded to the piezoelectric resonator 500 layer to achieve encapsulation, as shown in fig. 15a and 15 b.

In some embodiments, as shown in fig. 15a and 15b, when the upper silicon cap 700 and the piezoelectric resonator 500 layer are bonded and packaged, a first bonding layer 600 is disposed between the upper silicon cap 700 and the piezoelectric resonator 500 layer, and the bonding and packaging between the upper silicon cap 700 and the piezoelectric resonator 500 layer are achieved through the first bonding layer 600 and electrical conduction is achieved.

The material of the first bonding layer 600 may be gold, aluminum, germanium, copper, tin, titanium, chromium, or a composite layer of the above metals or an alloy thereof. The first bonding layer may be located above the piezoelectric layer 502 and connected to the piezoelectric layer, or may be located above the top electrode 501 and connected to the top electrode, or may be etched away from the piezoelectric layer 502 at a corresponding position and located on the surface of the doped monocrystalline silicon layer 200 or the surface of the bottom electrode 503.

In some embodiments, as shown in fig. 15b, a first dielectric layer 801 is further formed between the doped monocrystalline silicon layer 200 and the bottom electrode 503 of the piezoelectric resonator 500 layer, so as to achieve electrical isolation between the bottom electrode 503 and the doped monocrystalline silicon layer 200 through the first dielectric layer 801; in addition, a second dielectric layer 802 is formed on the surface of the top electrode 501, and passivation of the surface of the top electrode 501 can be prevented by the second dielectric layer 802.

The material of the first dielectric layer 801 and the second dielectric layer 802 may be an insulating material such as aluminum oxide (Al ₂O₃), aluminum nitride (AlN), silicon nitride (Si ₃N₄), or silicon dioxide (SiO ₂).

In some embodiments, the piezoelectric driven silicon-based resonator may be in the form of a cantilever beam, a simple beam, a tuning fork structure, or the like having a plurality of beam combinations, or may be in the form of other plate-like structures, and the vibration mode may be a lame (Lamb wave) mode, a Lamb wave (Lamb wave) mode, a flexural (bending) mode, or the like.

As shown in fig. 16 and 17, the structure of the piezoelectric driven silicon-based resonator is two different structures corresponding to tuning forks of the out-of-plane flexural mode and in-plane bending vibration modes (in-plane flexural mode).

Example two

In the method for manufacturing a semiconductor structure according to the embodiment of the present application, only the substrate structure is provided different from the substrate structure in the first embodiment, and in the embodiment of the present application, the substrate 101 is an SOI substrate.

Specifically, between the preparation steps S101, an SOI substrate is provided, where the SOI substrate includes a second bottom silicon layer 1011, an oxygen-buried layer 400, and a second top silicon layer 103 that are sequentially stacked, and the materials of the second top silicon layer 103 and the second bottom silicon layer 1011 are monocrystalline silicon, and the material of the oxygen-buried layer 400 may be SiO ₂.

Specifically, after providing the SOI substrate, a doped monocrystalline silicon layer 200 is formed on the surface of the second top silicon layer 103 by epitaxial growth, as shown in fig. 17, where the doping elements and doping types of the doped monocrystalline silicon layer 200 are the same as those in the first embodiment, and will not be described herein.

In some embodiments, as shown in fig. 18 and 19, after the doped monocrystalline silicon layer 200 is grown on the surface of the second top silicon layer 103 by means of epitaxial growth, a thermal oxide layer is grown on the surface of the doped monocrystalline silicon layer 200.

After a thermal oxide layer is grown on the surface of the doped monocrystalline silicon layer 200, the SOI substrate after the thermal oxide layer is formed on the surface of the doped monocrystalline silicon layer 200 is flipped and bonded with the first bottom silicon layer 102 with the cavity formed thereon, so that the cavity with a closed opening is formed after the first bottom silicon layer 102 is bonded with the SOI substrate. Note that instead of growing a thermal oxide layer, the two substrates prepared may be bonded directly by silicon-silicon bonding, similar to fig. 6; or after patterning a silicon dioxide layer on the surface of the doped monocrystalline silicon layer 200, a silicon-silicon bonding process is still used outside the cavity, similar to the case shown in fig. 7 b.

In fig. 20, the SOI substrate is flipped over and bonded to a first bottom silicon layer 102 on which no thermal oxide layer is grown on the surface.

In fig. 21, the SOI substrate is flipped and bonded to a first base silicon layer 102 on the surface of which a thermal oxide layer is grown.

In fig. 22, a thermal oxide layer is not grown on the surface of the second top silicon layer 103, but is grown on the surface of the first bottom silicon layer 102, and thus the SOI substrate is flip-chip bonded to the first bottom silicon layer 102 on which the thermal oxide layer is grown.

In some embodiments, removing at least a portion of the substrate 101, specifically includes: the second bottom silicon layer 1011 and the buried oxide layer 400 are sequentially removed.

In other embodiments, removing at least a portion of the substrate 101, specifically includes: the second bottom silicon layer 1011, the buried oxide layer 400 and the second top silicon layer 103 are sequentially removed.

In some embodiments, the removing the second bottom silicon layer 1011, the buried oxide layer 400, and the second top silicon layer 103 in the SOI substrate sequentially specifically includes: the second bottom silicon layer 1011 is removed by means of chemical mechanical polishing and wet etching.

That is, the second base silicon layer 1011 may be entirely removed by means of chemical mechanical polishing and wet etching, and the buried oxide layer 400 is exposed, as shown in fig. 23.

It will be appreciated that when the second bottom silicon layer 1011 is removed by chemical mechanical polishing and wet etching, the buried oxide layer 400 acts as an etch stop layer, such that etching is stopped when the buried oxide layer 400 is etched, thereby avoiding etching damage to the second top silicon layer 103 under the buried oxide layer 400, and thus, by providing the buried oxide layer 400 between the second bottom silicon layer 1011 and the second top silicon layer 103, the accuracy of the thickness of the substrate 101 can be better controlled.

In some embodiments, after removing the second bottom silicon layer 1011, the buried oxide layer 400 may be removed by a hydrofluoric acid (HF) solution, as shown in fig. 24, to expose the second top oxide layer.

In some embodiments, after removing the buried oxide layer 400, part or all of the second top silicon layer 103 may also be removed by a Chemical Mechanical Polishing (CMP) process; for example, in fig. 25, the entire second top silicon layer 103 is removed by chemical mechanical polishing to expose the doped monocrystalline silicon layer 200, after which structures such as the piezoelectric resonator 500 layer are further processed on the doped monocrystalline silicon layer 200.

The second top silicon layer 103 is removed by chemical mechanical polishing, so that the accuracy of the roughness of the surface of the doped monocrystalline silicon layer 200 can be ensured to be high.

In the above-described scheme, by setting the structure of the substrate 101 as an SOI substrate, the accuracy of the thickness of the semiconductor structure can be better controlled.

In addition, other manufacturing processes of the semiconductor structure are the same as those of the first embodiment, and will not be described here again.

Example III

As shown in fig. 15a and 15b, an embodiment of the present application provides a semiconductor structure, including: the first bottom silicon layer 102 and the thin film silicon layer are formed on the surface of the first bottom silicon layer 102 through bonding, the thin film silicon layer at least comprises a doped monocrystalline silicon layer 200 formed in a part through an epitaxial growth mode, the doped monocrystalline silicon layer 200 is located at a position, close to the first bottom silicon layer 102, in the thin film silicon layer, and the doped monocrystalline silicon layer 200 is a heavily doped layer.

In some embodiments, the semiconductor structure further includes a piezoelectric resonator 500 layer and an upper silicon cap 700, wherein the doped monocrystalline silicon layer 200, the piezoelectric resonator 500 layer and the upper silicon cap 700 layer are sequentially stacked on the first bottom silicon layer 102 in a thickness direction of the first bottom silicon layer 102, and the doped monocrystalline silicon layer 200 is disposed on a side close to the first bottom silicon layer 102.

In some embodiments, the material of the first bottom silicon layer 102 may be monocrystalline silicon, and a side of the first bottom silicon layer 102 facing the doped monocrystalline silicon layer 200 is provided with a cavity.

The piezoelectric resonator 500 is formed on the surface of the doped monocrystalline silicon layer 200, and the upper silicon cap 700 is bonded to the piezoelectric resonator 500to form a semiconductor structure such as a piezoelectrically driven silicon-based resonator.

In some embodiments, the doped monocrystalline silicon layer 200 is an N-type heavily doped monocrystalline silicon layer 200 or a P-type heavily doped monocrystalline silicon layer 200, wherein the doped monocrystalline silicon layer 200 is doped with silicon while being grown by, for example, epitaxy, and the element of the doped ions of the doped monocrystalline silicon layer 200 may be B, as or P or the like.

In order to improve the performance of the piezoelectric resonator 500, in the embodiment of the present application, the doping concentration of the doped monocrystalline silicon layer 200 may be changed along with the growth thickness, so that the doping concentration of the doped monocrystalline silicon layer 200 may be flexibly and accurately controlled, so that the doping concentration of the doped monocrystalline silicon layer 200 may reach a target doping concentration, for example, the range of the target doping concentration may be greater than 1×10 ¹⁸cm^-3, and the preferred range may be 1×10 ¹⁹ to 10 ²¹cm^-3, but not limited to this range, or may be a higher doping concentration range, so that the semiconductor structure may achieve zero temperature drift characteristics, that is, the temperature coefficient may be close to zero, and the temperature performance may be more stable, so that the performance of the semiconductor structure may be improved, thereby improving the yield of the semiconductor structure.

In some embodiments, the doped monocrystalline silicon layer 200 has at least two sub-doped monocrystalline silicon layers stacked in a growth thickness direction, and different sub-doped monocrystalline silicon layers have different doping concentrations, as shown in fig. 12, the doped monocrystalline silicon layer 200 includes a first sub-doped monocrystalline silicon layer 201, a second sub-doped monocrystalline silicon layer 202, and a third sub-doped monocrystalline silicon layer 203, wherein a surface of the first sub-doped monocrystalline silicon layer 201 is grown on a thermal oxide layer, and it is understood that the doping concentrations of the first sub-doped monocrystalline silicon layer 201, the second sub-doped monocrystalline silicon layer 202, and the third sub-doped monocrystalline silicon layer 203 are different.

In the above scheme, the doping concentration of each sub-doped monocrystalline silicon layer is changed in a gradient manner, so that the thickness and the doping concentration of each sub-doped monocrystalline silicon layer can be regulated and controlled, the doping concentration of the doped monocrystalline silicon layer 200 can be flexibly and accurately controlled, the semiconductor structure can realize zero temperature drift characteristics, namely, the temperature coefficient can be close to zero, the temperature performance is more stable, the performance of the semiconductor structure can be improved, and the yield of the semiconductor structure is further improved.

In some embodiments, the doped monocrystalline silicon layer 200 and the first bottom silicon layer 102 may be formed by bonding, and in order to improve bonding reliability between the doped monocrystalline silicon layer 200 and the first bottom silicon layer 102, please continue to refer to fig. 14, a thermal oxide layer 301 is further included, that is, the thermal oxide layer 301 is disposed between the first bottom silicon layer 102 and the doped monocrystalline silicon layer 200, so that the thermal oxide layer 301 may be disposed as an adhesive layer between the first bottom silicon layer 102 and the doped monocrystalline silicon layer 200, so as to improve adhesion between the first bottom silicon layer 102 and the doped monocrystalline silicon layer 200.

In some embodiments, the thermal oxide layer may cover a side wall of the cavity opposite the doped monocrystalline silicon layer 200, as shown in fig. 9.

In other embodiments, the thermal oxide layer covers a side surface of the doped monocrystalline silicon layer 200 corresponding to the cavity, as shown in fig. 7 a.

In still other embodiments, the thermal oxide layer covers the walls of the cavity and a side surface of the doped monocrystalline silicon layer 200 corresponding to the cavity, as shown in fig. 8.

In some embodiments, the piezoelectric resonator 500 layer includes a bottom electrode 503, a piezoelectric layer 502, and a top electrode 501 stacked in this order on the surface of the doped monocrystalline silicon layer 200.

In some embodiments, the material of the piezoelectric layer 502 may be any of aluminum nitride, polycrystalline aluminum nitride, and rare earth doped aluminum nitride.

Illustratively, the piezoelectric layer 502 is made of rare earth doped aluminum nitride; wherein the rare earth doped aluminum nitride comprises at least one of scandium (Sc), yttrium (Y), magnesium (Mg), titanium (Ti), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu).

In some embodiments, a dielectric layer may be further disposed between the bottom electrode 503 and the thin film silicon layer, where the dielectric layer may be any of silicon dioxide, silicon nitride, aluminum oxide, and aluminum nitride.

In some embodiments, the upper silicon cap 700 may be disposed on the top electrode 501 of the piezoelectric resonator 500 by means of bonding, and in order to improve bonding reliability between the upper silicon cap 700 and the top electrode 501, in the embodiment of the present application, a first bonding layer 600 is disposed between the upper silicon cap 700 and the top electrode 501, and bonding between the upper silicon cap 700 and the top electrode 501 is achieved through the first bonding layer 600, thereby improving bonding reliability thereof.

In some embodiments, as shown in fig. 15a and 15b, the upper silicon cap 700 includes a substrate 701 and a second bonding layer 702, the second bonding layer 702 being disposed on a side of the substrate 701 facing the first bonding layer 600; the substrate 701 is further provided with a conductive through hole 704 penetrating the substrate 701 and the second bonding layer 702, a side of the upper silicon cap 700 facing away from the second bonding layer 702 is provided with a metal pin 703 electrically connected with the conductive through hole 704, and a side of the substrate 701 facing the top electrode 501 is further provided with a getter layer 705, and the materials of the getter layer may be titanium (Ti) and titanium alloy, zirconium (Zr) and zirconium alloy, and the like. The material of the substrate 701 may be monocrystalline silicon or the like. In other embodiments (not shown), the surface of the second bonding layer 702 and the conductive layer of the conductive via 704 contacting the substrate 701 is further provided with a SiO2 layer generated by thermal oxygen or chemical vapor deposition as an insulating layer, so that the bonding layer 702 and the conductive layer of the conductive via 704 are not directly contacted with the substrate 701, thereby improving the isolation characteristics between the input, output and ground ports of the device

By providing the second bonding layer 702 on the side of the substrate 701 facing the first bonding layer 600, bonding between the upper silicon cap 700 and the top electrode 501 is achieved through the first bonding layer 600 and the second bonding layer 702, so that bonding reliability between the upper silicon cap 700 and the top electrode 501 can be further improved. The material of the second bonding layer 702 may be gold, aluminum, germanium, copper, tin, titanium, or a composite layer of the above metals or an alloy thereof, and specifically, a material matched with the material of the first bonding layer 600 may be selected, that is, the first bonding layer 600 and the second bonding layer 702 may be bonded by hot pressing, for example, the bonding materials matched with the first bonding layer 600 and the second bonding layer 702 may be: gold-gold bonding, aluminum-germanium bonding, copper-copper bonding, copper-gold-copper bonding, copper-tin-gold bonding, and the like.

In some embodiments, the upper silicon cap 700 is further provided with a through hole penetrating through the substrate 701 and the second bonding layer 702, a conductive layer is attached to a hole wall of the through hole, and the through hole and the conductive layer on the surface form a conductive through hole 704, where a material of the conductive layer in the conductive through hole 704 may be copper, gold, aluminum-silicon-copper alloy or a composite layer thereof.

The metal pins 703 are made of gold, aluminum, copper, titanium, iridium, osmium, chromium, or a composite of these metals or an alloy thereof.

It will be appreciated that the semiconductor structure formed in the above-described scheme may be electrically connected to other devices through the metal pins 703.

In some embodiments, as shown in fig. 15a and 15b, the upper silicon cap 700 has etched bump structures and an upper cavity structure for accommodating devices thereon, wherein the second bonding layer 702 is located on the bump structures and the getter layer 705 is located inside the cavity. In other embodiments, not shown, the upper silicon cap may also have no etched cavity structures and/or raised structures therein, such that the side of the silicon cap 700 facing the device is a flat surface, in which case the upper cavity structure housing the device is formed solely by the bonding layer.

The embodiment of the application also provides electronic equipment, which comprises the semiconductor structure provided in the embodiment.

The preparation method of the semiconductor structure provided by the embodiment of the application comprises the following steps: forming a heavily doped monocrystalline silicon layer on a substrate in an epitaxial growth mode; forming a cavity on the first bottom silicon layer; after the substrate is inverted, bonding the doped monocrystalline silicon layer with the first bottom silicon layer; removing at least part of the substrate to form a thin film silicon layer on the first bottom silicon layer; wherein the thin film silicon layer comprises a doped monocrystalline silicon layer having at least a partial thickness. In the scheme, the heavily doped monocrystalline silicon layer is formed on the substrate in an epitaxial growth mode, so that the doping concentration of the silicon layer of the semiconductor structure can be improved, the doping concentration is adjustable and controllable, and the performance consistency and the yield of the semiconductor structure can be improved.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a cavity on the first bottom silicon layer;

2. The method of manufacturing a semiconductor structure according to claim 1, wherein the step of forming the heavily doped monocrystalline silicon layer on the substrate by epitaxial growth comprises:

3. The method for manufacturing a semiconductor structure according to claim 2, wherein the doped monocrystalline silicon layer has at least two sub-doped monocrystalline silicon layers stacked in a growth thickness direction, different ones of the sub-doped monocrystalline silicon layers having different doping concentrations and/or different dopants.

4. The method of manufacturing a semiconductor structure according to claim 3, wherein a doping concentration of each of the sub-doped single crystal silicon layers is sequentially arranged from large to small or from small to large in a direction of the growth thickness.

5. The method of claim 2, wherein the doping concentration of the doped monocrystalline silicon layer varies continuously with growth thickness.

6. The method of any one of claims 1-5, wherein the doped monocrystalline silicon layer has a doping concentration greater than the substrate doping concentration, the doped monocrystalline silicon layer being an N-type heavily doped monocrystalline silicon layer or a P-type heavily doped monocrystalline silicon layer; wherein the doping concentration of the doped monocrystalline silicon layer is greater than or equal to 10 ¹⁹cm^-3.

7. The method of claim 6, wherein the doped monocrystalline silicon layer has a doping concentration greater than or equal to 10 ²⁰cm^-3.

8. The method of any of claims 1-5, wherein the inverting the substrate and bonding the first bottom silicon layer are preceded by:

9. The method of any of claims 1-5, wherein the substrate comprises a first top silicon layer, and the doped monocrystalline silicon layer is formed on a surface of the first top silicon layer.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein the removing at least a portion of the substrate specifically comprises: thinning the thickness of the first top silicon layer; or removing the first top silicon layer.

11. The method for fabricating a semiconductor structure according to any one of claims 1 to 5, wherein the forming a heavily doped monocrystalline silicon layer on the substrate by epitaxial growth comprises:

12. The method for manufacturing a semiconductor structure according to claim 11, wherein the removing at least a portion of the substrate specifically comprises:

13. The method of any of claims 1-5, wherein the removing at least a portion of the substrate, in particular, comprises:

14. The method of fabricating a semiconductor structure according to any one of claims 1 to 5, wherein after forming a heavily doped monocrystalline silicon layer on the substrate by epitaxial growth or after forming a thin film silicon layer on the first underlying silicon layer, further comprising:

15. The method for manufacturing a semiconductor structure according to claim 14, wherein if the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer is smaller than a preset doping concentration, doping the doped monocrystalline silicon layer or the thin film silicon layer by ion implantation or thermal diffusion, or high-temperature annealing the doped monocrystalline silicon layer or the thin film silicon layer to increase the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer; and if the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer is larger than the preset doping concentration, carrying out high-temperature annealing on the doped monocrystalline silicon layer or the thin film silicon layer so as to reduce the doping concentration of the doped monocrystalline silicon layer or the thin film silicon layer.

16. The method of any of claims 1-5, wherein after removing at least a portion of the substrate to form a thin film silicon layer on the first bottom silicon layer, further comprising:

17. The method of manufacturing a semiconductor structure according to claim 16, wherein after the forming of the piezoelectric resonator layer on the surface of the thin film silicon layer, further comprising:

An upper silicon cap is bonded to the piezoelectric resonator layer.

18. A semiconductor structure, comprising:

A first bottom silicon layer having a cavity;

The thin film silicon layer is formed on the surface of the first bottom silicon layer through bonding, and at least comprises a doped monocrystalline silicon layer which is formed in a part through an epitaxial growth mode, wherein the doped monocrystalline silicon layer is positioned at a position, close to the first bottom silicon layer, in the thin film silicon layer, and the doped monocrystalline silicon layer is a heavy doped layer.

19. The semiconductor structure of claim 18, wherein the doped monocrystalline silicon layer is an N-type heavily doped monocrystalline silicon layer or a P-type heavily doped monocrystalline silicon layer, and the doping concentration of the doped monocrystalline silicon layer is greater than or equal to 10 ¹⁹cm^-3.

20. The semiconductor structure of claim 19, wherein a doping concentration of the doped monocrystalline silicon layer varies with a growth thickness.

21. The semiconductor structure of claim 20, wherein the doped monocrystalline silicon layer has at least two sub-doped monocrystalline silicon layers stacked along a growth thickness direction, different ones of the sub-doped monocrystalline silicon layers having different doping concentrations and/or different dopants.

22. The semiconductor structure of claim 21, wherein a doping concentration of each of the sub-doped single crystal silicon layers is sequentially arranged from large to small or from small to large in a direction of the growth thickness.

23. The semiconductor structure of claim 20 wherein the doping concentration of the doped monocrystalline silicon layer varies continuously with growth thickness.

24. The semiconductor structure of claim 18, further comprising a thermal oxide layer disposed between the first bottom silicon layer and the doped monocrystalline silicon layer.

25. The semiconductor structure of claim 24, wherein the thermal oxide layer covers a side wall of the cavity opposite the doped monocrystalline silicon layer.

26. The semiconductor structure of claim 24, wherein the thermal oxide layer covers a side surface of the doped monocrystalline silicon layer corresponding to the cavity.

27. The semiconductor structure of claim 24, wherein the thermal oxide layer covers walls of the cavity and a side surface of the doped monocrystalline silicon layer corresponding to the cavity.

28. The semiconductor structure of claim 18, further comprising:

And a silicon cap bonded to the piezoelectric resonator layer.

29. The semiconductor structure of claim 28, wherein the piezoelectric resonator layer comprises a piezoelectric layer and a top electrode sequentially stacked on a surface of the thin film silicon layer.

30. The semiconductor structure of claim 29, wherein the piezoelectric resonator further comprises a bottom electrode disposed on a side of the piezoelectric layer facing away from the top electrode.

31. The semiconductor structure of claim 30, wherein a dielectric layer is disposed between the bottom electrode and the thin film silicon layer, the dielectric layer being at least one of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride.

32. The semiconductor structure of claim 29, wherein the piezoelectric layer comprises any one of single crystal aluminum nitride, polycrystalline aluminum nitride, rare earth doped aluminum nitride; wherein the rare earth doped aluminum nitride comprises at least one of scandium, yttrium, magnesium, titanium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, lutetium.

33. The semiconductor structure of claim 29, wherein a first bonding layer is disposed between the upper silicon cap and the piezoelectric layer.

34. The semiconductor structure of claim 33, wherein the upper silicon cap comprises a substrate and a second bonding layer disposed on a side of the substrate facing the first bonding layer;

35. The semiconductor structure of claim 34, wherein the first bonding layer and the second bonding layer are both metal layers.

36. The semiconductor structure of claim 35, wherein a silicon dioxide layer is disposed between the metal pins and the conductive vias and the substrate.

37. An electronic device comprising the semiconductor structure of any one of claims 18-36.