CN112447771B - GeSiOI substrate and preparation method thereof, and GeSiOI device and preparation method thereof - Google Patents
GeSiOI substrate and preparation method thereof, and GeSiOI device and preparation method thereof Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 176
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 43
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000011241 protective layer Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 230000007547 defect Effects 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 14
- 239000012212 insulator Substances 0.000 description 8
- 238000005498 polishing Methods 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
Abstract
The invention relates to a GeSiOI substrate and a preparation method thereof, and a GeSiOI device and a preparation method thereof. A GeSiOI substrate comprising, stacked in order from bottom to top: silicon substrate, buried oxide layer, protective layer, ge 1‑x Si x A layer; wherein x is more than or equal to 0.1 and less than or equal to 0.3, and Ge 1‑x Si x The thickness of the layer is less than or equal to 100nm. The preparation method comprises the following steps: sequentially depositing a germanium buffer layer and Ge on a silicon substrate 1‑x Si x A layer and a protective layer to obtain a first multi-layer material structure; depositing an oxygen burying layer on the silicon substrate to obtain a second multilayer material structure; bonding the two structures; etching sequentially to remove the silicon substrate and the germanium buffer layer, and then removing Ge 1‑x Si x Etching the layer until the thickness is less than or equal to 100nm. The invention improves the mobility of the GeSiOI substrate, obtains a doped GeSiOI device, reduces the source-drain resistance of the device and improves the on-state current of the device.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a GeSiOI substrate and a preparation method thereof, and a GeSiOI device and a preparation method thereof.
Background
Fully depleted SOI devices with flexible threshold voltage (V) compared to conventional bulk material devices T ) The advantages of adjustability, better electrostatic properties, compatibility with existing planar device processes, etc., are one of the main development directions of semiconductor devices with continuously shrinking feature sizes. Strained SOI or low-germanium SiGeOI as substrate material, due to low mobility limitWith the continuous reduction of the feature size, the requirements of high-performance devices cannot be fully met.
For this purpose, the present invention is proposed.
Disclosure of Invention
The main purpose of the invention is to provide a GeSiOI substrate, wherein the top layer of the substrate is high in Ge content and has the advantage of high mobility.
Another object of the present invention is to provide a method for preparing the GeSiOI substrate described above, which solves the problem of directly depositing Ge on a silicon substrate 1-x Si x And the defect is more when the layer is formed.
Another object of the present invention is to provide a doped GeSiOI device that further reduces the source-drain resistance of the device and increases the on-state current of the device by doping. In order to achieve the above object, the present invention provides the following technical solutions.
A GeSiOI substrate comprising, stacked in order from bottom to top:
a silicon substrate having a silicon-based layer,
an oxygen-buried layer is arranged on the substrate,
the protective layer is provided with a protective layer,
Ge 1-x Si x a layer;
wherein x is more than or equal to 0.1 and less than or equal to 0.3, and Ge 1-x Si x The thickness of the layer is less than or equal to 100nm.
Compared with the traditional germanium-silicon substrate on insulator, the germanium-silicon substrate on insulator has higher mobility, and can meet the requirements of high-performance devices, such as GeSiOI devices for manufacturing doped source-drain structures, and particularly fully-depleted devices.
The above GeSiOI substrate can be obtained by the following preparation method, which comprises the following steps:
sequentially depositing a germanium buffer layer and Ge on a first silicon substrate 1-x Si x A layer and a protective layer to obtain a first multi-layer material structure; wherein x is more than or equal to 0.1 and less than or equal to 0.3, and the germanium buffer layer is a pure Ge layer or the germanium content is less than Ge 1-x Si x Is a germanium-silicon layer;
depositing an oxygen burying layer on a second silicon substrate to obtain a second multilayer material structure;
bonding the first multi-layer material structure with the second multi-layer material structure, and bonding the protective layer of the first multi-layer material structure with the oxygen-buried layer of the second multi-layer material structure to obtain a bonding structure;
sequentially etching to remove the first silicon substrate and the germanium buffer layer of the bonding structure, and then removing the Ge 1-x Si x Etching the layer until the thickness is less than or equal to 100nm.
Compared with the traditional preparation process of the germanium-silicon substrate on the insulator, the preparation method provided by the invention has the following characteristics:
1. deposition of Ge on Ge buffer layer 1-x Si x A layer, which can avoid high germanium content Ge 1-x Si x Defect too many in growth, controlling defect in germanium buffer layer, reducing Ge 1-x Si x Defects inside the layer; on the other hand, due to the germanium buffer layer and Ge 1-x Si x The layers are of different materials, so that the etching can be stopped at Ge by selective etching 1-x Si x A layer surface; in addition, the germanium buffer layer can be relaxed to be Ge 1-x Si x The layer introduces stress, so that the mobility of the film carrier is improved;
2. the protective layer can reduce Ge 1-x Si x Interface defects with the buried oxide layer enhance adhesion with the buried oxide layer;
3. bonding Ge 1-x Si x The transfer of the layer to the insulator also retains the feature of few internal defects.
In conclusion, compared with the prior art, the invention achieves the following technical effects:
(1) The mobility of the GeSiOI substrate is improved;
(2) Reduction of Ge in GeSiOI substrate 1-x Si x Internal lattice defects of the layer;
(3) Solves the Ge 1-x Si x The etching selectivity of the layer and the adjacent layer is low;
(4) To Ge 1-x Si x The layer introduces stress, thereby improving carrier mobility;
(5) The doped GeSiOI device is obtained, the source-drain resistance of the device is reduced, and the on-state current of the device is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a schematic diagram of a GeSiOI substrate structure provided by the present invention;
FIGS. 2-4 are schematic views of structures formed at various steps in forming a donor wafer;
FIG. 5 is a schematic view of a structure for supporting a wafer;
FIG. 6 is a schematic diagram of the bonded wafers of FIGS. 4 and 5;
FIG. 7 is a structure after etching to remove the Si <100> substrate of the donor wafer of the structure shown in FIG. 6;
FIG. 8 is a structure after etching to remove the Ge buffer layer of the structure of FIG. 7;
FIG. 9 is a schematic diagram of an FD-GeSiOI device with a doped source-drain structure according to the present invention;
fig. 10 to 12 are schematic views of three other GeSiOI substrate structures according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
In order to improve the mobility of the GeSiOI substrate, the invention provides a substrate with the following structure.
A GeSiOI substrate comprising, stacked in order from bottom to top:
a silicon substrate having a silicon-based layer,
an oxygen-buried layer is arranged on the substrate,
the protective layer is provided with a protective layer,
Ge 1-x Si x a layer;
wherein x is more than or equal to 0.1 and less than or equal to 0.3, and Ge 1-x Si x The thickness of the layer is less than or equal to 100nm.
Compared with the traditional germanium-silicon-on-insulator substrate, the germanium content (the germanium atom content reaches 70% -90%), so that the substrate has higher mobility, and can meet the requirements of high-performance devices, such as GeSiOI devices for manufacturing doped source-drain structures, and particularly fully-depleted devices.
If the GeSiOI substrate is obtained by conventional layer-by-layer deposition, there are many problems, such as Ge 1-x Si x Large internal defects, high interface defects with the buried silicon oxide layer, and the like.
To this end, the present invention provides the following preferred preparation method comprising:
sequentially depositing a germanium buffer layer and Ge on a silicon substrate 1-x Si x A layer and a protective layer to obtain a first multi-layer material structure; wherein x is more than or equal to 0.1 and less than or equal to 0.3, and the germanium buffer layer is a pure Ge layer or the germanium content is less than Ge 1-x Si x Is a germanium-silicon layer;
depositing an oxygen burying layer on the silicon substrate to obtain a second multilayer material structure;
bonding the first multi-layer material structure with the second multi-layer material structure, and bonding the protective layer of the first multi-layer material structure with the oxygen-buried layer of the second multi-layer material structure to obtain a bonding structure;
sequentially etching to remove the silicon substrate and the germanium buffer layer of the bonding structure, and then removing the Ge 1-x Si x Etching the layer until the thickness is less than or equal to 100nm.
Compared with the traditional preparation process of the germanium-silicon substrate on the insulator, the preparation method provided by the invention has the following characteristics:
1. deposition of Ge on Ge buffer layer 1-x Si x Layer (c):
because the high-quality germanium-silicon layer is directly grown on the silicon, the defects in the layer are more, the epitaxial layer is poor in quality, and the defects can be limited in the range of the buffer layer by adopting the buffer layer, so that the high-quality epitaxial germanium-silicon layer required by growth is grown;
on the other hand, due to the germanium buffer layer and Ge 1-x Si x The layers are of different materials, so that the etching can be stopped at Ge by selective etching 1-x Si x A layer surface;
in addition, the germanium buffer layer can be relaxed to be Ge 1-x Si x The layer introduces stress, thereby improving carrier mobility;
2. the protective layer can reduce Ge 1-x Si x Interface defects with the buried oxide layer enhance adhesion with the buried oxide layer;
3. bonding Ge 1-x Si x The transfer of the layer to the insulator also retains the feature of few internal defects.
In some preferred embodiments, the protective layer comprises at least one of a silicon oxide layer, a silicon layer, or a high-k dielectric layer, preferably an aluminum oxide layer.
In some preferred embodiments, the protective layer is an alumina layer, which not only has good passivation but also enhances adhesion and facilitates bonding.
In some preferred embodiments, the protective layer is a silicon layer.
In some preferred embodiments, the protective layer is formed by stacking a silicon oxide layer and a silicon layer sequentially from bottom to top.
In some preferred embodiments, the protective layer is formed by stacking a high-k dielectric layer and a silicon layer sequentially from bottom to top.
The high-k dielectric as described herein generally refers to a dielectric material having a k greater than the dielectric constant of silicon oxide.
In the invention, the buried oxide layer mainly serves as insulation, and preferably some insulators with small interface defects are selected.
In some preferred embodiments, the buried oxide layer is silicon oxide.
In some preferred embodiments, the silicon substrate is a silicon <100> substrate.
In some preferred embodiments, the germanium buffer layer is a pure Ge layer, or a silicon germanium layer with the germanium content increasing from bottom to top; and the germanium buffer layer is a germanium-silicon layer with the content of germanium increasing from bottom to top, and the highest content of germanium is less than the Ge 1- x Si x Germanium content in the layer.
In some preferred embodiments, the thickness of the germanium buffer layer exceeds its critical thickness to form a more complete relaxation.
In some preferred embodiments, when the germanium buffer layer is a pure Ge layer, a more complete relaxation is formed by growing Ge first at a low temperature and then at a high temperature.
In some preferred embodiments, the germanium buffer layer, ge 1-x Si x The deposition method of the layer comprises the following steps: and (5) epitaxial growth. Epitaxial growth can make germanium buffer layer and Ge 1-x Si x The layer has the characteristics of regular and larger monocrystal, and has more excellent electrical property.
The deposition means of the remaining layers in the present invention are not limited, including but not limited to typical APCVD, UHVCVD, LPCVD, RTCVD, PECVD or oxide growth, etc. Taking the deposition of the buried oxide layer as silicon oxide as an example, thermal oxygen growth is preferably employed.
In the present invention, the first multi-layer Ge 1-x Si x The bonding means of the layer material structure to the second multilayer material structure is optional, e.g. pre-bonding at room temperature followed by high temperature bonding as one, or electrostatic bondingBonding, etc., is preferably low temperature bonding.
In the invention, the etching means of the silicon substrate is arbitrary, preferably polishing (polishing) back surface thinning, chemical Mechanical Polishing (CMP), wet etching, dry etching and the like, and can be combined by a plurality of means.
The etching means of the germanium buffer layer is arbitrary, and selective wet etching is preferable.
Ge 1-x Si x The etching means of (a) is arbitrary, and Chemical Mechanical Polishing (CMP), wet etching, atomic Layer Etching (ALE) (dry or wet), gas oxidation+wet etching, or the like is preferably used, and a combination of a plurality of means is also possible.
Any of the GeSiOI substrates described above may be used to fabricate memories, logic circuits, microprocessors, etc., and is particularly advantageous for fully depleted GeSiOI devices (FD-GeSiOI) with doped source-drain structures.
The invention also provides a preparation method of the preferable GeSiOI device, which comprises the following steps:
forming an active region of a device on the GeSiOI substrate;
forming a gate structure in the active region;
performing source-drain doping; the doping generally refers to a doping amount sufficient to achieve the adjustment of the intrinsic material band structure;
and forming a source drain structure.
In some preferred embodiments, the source-drain doping method is as follows: ion implantation in combination with activation annealing, or a two-step thermal diffusion process, or a selective epitaxy process.
In a preferred embodiment of the present invention, the GeSiOI substrate has a structure as shown in fig. 1, and comprises, in order from bottom to top:
a silicon substrate having a silicon-based layer,
a layer of silicon oxide is formed over the silicon oxide layer,
the layer of aluminum oxide is formed from a layer of aluminum oxide,
Ge 1-x Si x a layer;
wherein x is more than or equal to 0.1 and less than or equal to 0.3, and Ge 1-x Si x The thickness of the layer is less than or equal to 100nm.
The GeSiOI substrate of this example was prepared by the following procedure.
First, a donor wafer is formed:
providing a silicon <100> substrate, and epitaxially growing a germanium layer on the surface to obtain a morphology as shown in figure 2;
second step, epitaxial growth of Ge 1-x Si x A layer, x is more than or equal to 0.1 and less than or equal to 0.3, and the thickness can exceed 100nm, so that the morphology shown in figure 3 is obtained;
third step, deposit Al 2 O 3 The layers, resulting in the topography shown in fig. 4.
Next, a supporting wafer is formed:
providing a silicon <100> substrate, and depositing a silicon oxide layer on the surface to obtain the shape shown in figure 5;
bonding the donor wafer shown in FIG. 4 to the support wafer shown in FIG. 5, al 2 O 3 The layer bonds to the silicon oxide layer supporting the wafer, resulting in the topography shown in fig. 6.
And then removing the Si <100> substrate of the donor wafer by adopting a polishing (Grading) back thinning method, a Chemical Mechanical Polishing (CMP) method, a wet etching method, a dry etching method and the like, exposing the surface of the Ge buffer layer, and obtaining the morphology shown in figure 7.
Removing the Ge buffer layer by adopting a selective wet etching scheme to expose Ge 1-x Si x The layers, resulting in the topography shown in fig. 8.
Thinning Ge using a Chemical Mechanical Polishing (CMP)/wet etch scheme/Atomic Layer Etch (ALE) scheme (dry or wet)/gas oxidation + wet etch (or a combination of means) 1-x Si x (0.1.ltoreq.x.ltoreq.0.3) layer to 100nm and below, resulting in the structure shown in FIG. 1.
The FD-GeSiOI device with the doped source-drain structure is manufactured by using the GeSiOI substrate shown in fig. 1, and the flow is as follows:
forming an active region of the device on the GeSiOI substrate, and etching the GeSiOI substrate until Al is etched 2 O 3 Silicon oxide or even a substrate silicon layer;
forming a gate structure in the active region;
the ion implantation is combined with activation annealing, a two-step thermal diffusion method or a selective epitaxy method is adopted to carry out source-drain doping (such as N-type doping or P-type doping, etc., and the doping can be realized by means of in-situ doping or ion implantation, etc.).
The obtained device structure is shown in fig. 9, a source electrode 1, a drain electrode 2 and a grid stacking layer 3 are arranged on the germanium-silicon top layer of GeSiOI, a contact structure 4 is arranged above the source electrode 1 and the drain electrode 2, and the contact structure 4 can be realized through means of metal deposition, metal etching, annealing and the like.
The present invention also provides three other embodiments, the GeSiOI substrate structures provided in fig. 10, 11 and 12 are respectively similar to the structure of fig. 1, and the preparation method is that the GeSiOI substrate structure is formed by etching the redundant layers after bonding the donor wafer and the support wafer, and is specifically shown in table 1.
TABLE 1
| Final substrate | Donor wafer | Supporting wafer |
| Formation of the structure of FIG. 1 | Si/germanium buffer layer/Ge 1-x Si x /Al 2 O 3 | Si/SiO 2 |
| Formation of the structure of FIG. 10 | Si/germanium buffer layer/Ge 1-x Si x /Si | Si/SiO 2 |
| Formation of the structure of FIG. 11 | Si/germanium buffer layer/Ge 1-x Si x /Si/SiO 2 | Si/SiO 2 |
| Formation of the structure of FIG. 12 | Si/germanium buffer layer/Ge 1-x Si x Si/high k dielectric | Si/SiO 2 |
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (10)
1. A method of preparing a GeSiOI substrate for a fully depleted device, comprising:
sequentially depositing a germanium buffer layer and Ge on a first silicon substrate 1-x Si x A layer and a protective layer to obtain a first multi-layer material structure; wherein x is more than or equal to 0.1 and less than or equal to 0.3;
depositing an oxygen burying layer on a second silicon substrate to obtain a second multilayer material structure;
bonding the first multi-layer material structure with the second multi-layer material structure, and bonding the protective layer of the first multi-layer material structure with the oxygen-buried layer of the second multi-layer material structure to obtain a bonding structure;
sequentially etching to remove the first silicon substrate and the germanium buffer layer of the bonding structure, and then removing the Ge 1-x Si x Etching to a thickness of less than 100 nm;
the germanium buffer layer is a germanium-silicon layer with the content of germanium increasing from bottom to top, and the highest content of germanium is smaller than that of the Ge 1-x Si x Germanium content in the layer.
2. The method of claim 1, wherein the germanium buffer layer has a thickness exceeding a critical thickness thereof.
3. The method of claim 1, wherein the germanium buffer layer, ge 1-x Si x The deposition method of the layer comprises the following steps: and (5) epitaxial growth.
4. The method of claim 1, wherein the protective layer comprises at least one of a silicon oxide layer, a silicon layer, or a high-k dielectric layer.
5. The method of claim 1, wherein the protective layer is a high-k dielectric layer;
or, the protective layer is a silicon layer;
or the protective layer is formed by stacking silicon oxide layers and silicon layers in sequence from bottom to top;
or the protective layer is formed by stacking high-k dielectric layers and silicon layers sequentially from bottom to top.
6. The method of claim 1, wherein the protective layer is an alumina layer.
7. The method of claim 1, wherein the buried oxide layer is silicon oxide.
8. The method of manufacturing according to claim 1, wherein the silicon substrate is a silicon <100> substrate.
9. A method of fabricating a GeSiOI device, comprising:
forming an active region of a device on a GeSiOI substrate made by the method of any one of claims 1-8;
forming a gate structure in the active region;
performing source-drain doping;
and forming a source drain structure.
10. The method of claim 9, wherein the source-drain doping method comprises: ion implantation in combination with activation annealing, or a two-step thermal diffusion process, or a selective epitaxy process.
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