CN115763256A - Preparation method of semiconductor structure and semiconductor structure - Google Patents
Preparation method of semiconductor structure and semiconductor structure Download PDFInfo
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- CN115763256A CN115763256A CN202211462898.5A CN202211462898A CN115763256A CN 115763256 A CN115763256 A CN 115763256A CN 202211462898 A CN202211462898 A CN 202211462898A CN 115763256 A CN115763256 A CN 115763256A
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Abstract
The invention provides a preparation method of a semiconductor structure and the semiconductor structure, the preparation method of the semiconductor structure comprises the steps of growing a SiGe relaxation buffer layer and a fully relaxed SiGe strain relaxation layer on a second silicon substrate in sequence, bonding the SiGe strain relaxation layer on the second silicon substrate on a dielectric layer on a first silicon substrate, removing the first silicon substrate and the SiGe relaxation buffer layer, thinning the SiGe strain relaxation layer, and finally epitaxially growing a tensile strain silicon layer on the thinned SiGe strain relaxation layer to realize the high-mobility tensile strain silicon layer SOI structure, and simultaneously manufacturing a brand new nanosheet substrate platform with high mobility, less impurity contamination, low impurity contamination, a high-quality laminated structure and a channel structure. The subsequent preparation of structures such as but not limited to a tensile strained silicon channel in the tensile strained silicon layer according to application scenarios is facilitated, and a good substrate is provided for FD/GAAOI devices.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure and the semiconductor structure.
Background
The introduction of stress in transistors is a technique widely used in the semiconductor process industry, and the introduction of stress can cause tensile stress or compressive stress to the material. The introduction of stress changes the quality of carriers, improves the mobility of the carriers in the transistor, and can manufacture a transistor with lower power consumption and higher mobility compared with a transistor without a stress substrate. The introduction of a tensile strained channel is therefore the primary method of improving device mobility. However, it is difficult to grow a high quality tensile strained silicon channel on a dielectric layer in the prior art. In addition, in the prior art, the nanosheet integration based on the silicon substrate is limited by the quality of the bottom laminated material, so that a plurality of problems such as impurity contamination, lattice defects, oxide layer defects, difficulty in ensuring the uniformity of the top silicon and the like often occur.
Disclosure of Invention
The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and realizes a tensile strain silicon layer SOI structure with high mobility.
In a first aspect, the present invention provides a method for fabricating a semiconductor structure, the method comprising: growing a dielectric layer on a first silicon substrate; growing a Si (silicon) Ge (germanium) relaxed buffer layer on the second silicon substrate, and growing a fully relaxed SiGe strain relaxed layer on the SiGe relaxed buffer layer; bonding the SiGe strain relaxed layer on the second silicon substrate on the dielectric layer on the first silicon substrate; removing the first silicon substrate and the SiGe relaxed buffer layer, and thinning the SiGe relaxed strain layer; epitaxially growing a tensile strained silicon layer on the thinned SiGe strain relaxed layer.
In the above scheme, a method for manufacturing a semiconductor structure for growing a tensile strained si layer is provided, in which a SiGe relaxed buffer layer and a fully relaxed SiGe strain relaxed layer are sequentially grown on a second silicon substrate, the SiGe strain relaxed layer on the second silicon substrate is bonded to a dielectric layer on a first silicon substrate, the first silicon substrate and the SiGe relaxed buffer layer are removed, the SiGe strain relaxed layer is thinned, and finally, a tensile strained si layer is epitaxially grown on the thinned SiGe strain relaxed layer, thereby realizing a high-mobility tensile strained si layer SOI structure. Meanwhile, the SiGe strain relaxation layer is bonded on the dielectric layer of the first silicon substrate after being prepared on the second silicon substrate, so that impurity contamination, impurity contamination and the like cannot be caused to the first silicon substrate, and a brand-new nanosheet substrate platform with high mobility, less impurity contamination, low impurity contamination, a high-quality laminated structure and a channel structure is manufactured. Facilitating subsequent fabrication of structures such as, but not limited to, a tensile strained silicon channel in a tensile strained silicon layer depending on the application scenario, providing a good substrate for FD/GAA (gate-all-around) OI devices.
In one particular embodiment, the thinned SiGe strain relaxed layer comprises: and thinning the SiGe strain relaxation layer until the thickness of the residual SiGe strain relaxation layer is 5-100nm, wherein the quality of the residual SiGe strain relaxation layer can be improved by preparing the thicker SiGe strain relaxation layer and then thinning the SiGe strain relaxation layer, and a higher-quality tensile strain silicon layer is conveniently epitaxially grown.
In one embodiment, the SiGe relaxed buffer layer and the SiGe strain relaxed layer are both Si 1- a Ge a (ii) a The value of a is gradually increased from the bottom of the SiGe relaxed buffer layer to the top of the SiGe relaxed buffer layer and is increased to the maximum value in the SiGe relaxed layer, and a in the SiGe relaxed layer is a fixed value, so that the quality of the SiGe relaxed layer is improved, and a higher-quality tensile strained silicon layer is conveniently epitaxially grown.
In a specific embodiment, a is gradually increased from the value of 0 at the bottom of the SiGe relaxed buffer layer to the value of max of the SiGe strain relaxed layer; wherein, the value range of max is 0.2-0.45, which improves the quality of SiGe strain relaxation layer and facilitates the epitaxial growth of higher quality tensile strain silicon layer.
In a specific embodiment, the dielectric layer is made of SiOx, siNx or Al 2 O 3 The quality of the dielectric layer is improved by the single layer or the laminated layer combination.
In one embodiment, the method for fabricating a semiconductor structure further comprises: preparing a source and a drain of the transistor in the tensile strained Si layer and the SiGe strain relaxed layer; forming a tensile strained silicon channel connecting the source and the drain on the tensile strained silicon layer; and preparing a grid electrode of the transistor on the tensile strain silicon channel to form an FDSOI device, enhancing the mobility of the silicon channel in the FDSOI device and finally realizing the substrate preparation of the high-mobility FDSOI device.
In one embodiment, the method for fabricating a semiconductor structure further comprises: repeatedly and alternately growing a SiGe strain relaxation layer and a tensile strained silicon layer on the tensile strained silicon layer to form a laminated structure in which the SiGe strain relaxation layer and the tensile strained silicon layer are repeatedly laminated; the cycle number of the repeated alternate growth is n times, and n is any positive integer, so that the GAASOI device with high mobility can be prepared conveniently.
In one embodiment, the method for fabricating a semiconductor structure further comprises: preparing a source electrode and a drain electrode of the transistor in a laminated structure; forming a tensile strained silicon channel connecting the source and the drain on each tensile strained silicon layer in the stacked structure; the gate of the transistor is fabricated in a stacked structure to form a GAASOI device. And enhancing the mobility of a silicon channel in the GAASOI device, and finally realizing the substrate preparation of the high-mobility GAASOI device.
In a second aspect, the present invention is also a semiconductor structure, comprising: the SiGe strain relaxed layer is bonded to the first silicon substrate, and the tensile strained silicon layer is epitaxially grown on the SiGe strain relaxed layer. Wherein, the SiGe strain relaxation layer is bonded and connected on the dielectric layer by adopting the following mode: growing a relaxed SiGe buffer layer on the second silicon substrate, and growing a fully relaxed SiGe strain relaxed layer on the relaxed SiGe buffer layer; bonding the SiGe strain relaxed layer on the second silicon substrate on the dielectric layer on the first silicon substrate; and removing the first silicon substrate and the SiGe relaxed buffer layer, and thinning the SiGe strain relaxed layer so that a tensile strained silicon layer is epitaxially grown on the thinned SiGe strain relaxed layer.
In the above scheme, a semiconductor structure for growing a tensile strained silicon layer is provided, in which a SiGe relaxed buffer layer and a fully relaxed SiGe strain relaxed layer are sequentially grown on a second silicon substrate, the SiGe strain relaxed layer on the second silicon substrate is bonded to a dielectric layer on a first silicon substrate, the first silicon substrate and the SiGe relaxed buffer layer are removed, the SiGe strain relaxed layer is thinned, and finally, a tensile strained silicon layer is epitaxially grown on the thinned SiGe strain relaxed layer, thereby implementing a high-mobility tensile strained silicon layer SOI structure. Meanwhile, the SiGe strain relaxation layer is bonded on the dielectric layer of the first silicon substrate after being prepared on the second silicon substrate, so that impurity contamination, impurity contamination and the like cannot be caused to the first silicon substrate, and a brand-new nanosheet substrate platform with high mobility, less impurity contamination, low impurity contamination, a high-quality laminated structure and a channel structure is manufactured. Facilitating subsequent fabrication of structures such as, but not limited to, a tensile strained silicon channel in a tensile strained silicon layer depending on the application scenario, providing a good substrate for FD/GAA (gate-all-around) OI devices.
In a specific embodiment, siGe strain relaxation layers and tensile strain silicon layers are repeatedly and alternately grown on the tensile strain silicon layers to form a laminated structure formed by repeatedly laminating the SiGe strain relaxation layers and the tensile strain silicon layers; the cycle number of the repeated alternate growth is n times, and n is any positive integer, so that the GAASOI device with high mobility can be prepared conveniently.
Drawings
Fig. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;
fig. 2 to 9 are schematic cross-sectional views of various steps of fabricating a semiconductor structure according to an embodiment of the present invention.
Reference numerals:
11-first silicon substrate 12-dielectric layer 21-second silicon substrate
22-SiGe relaxed buffer 23-SiGe strain relaxed 30-strained Si layer
41-source 42-drain 43-tensile strained silicon channel 44-gate
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
For convenience of understanding the method for manufacturing a semiconductor structure provided in the embodiment of the present invention, an application scenario of the method for manufacturing a semiconductor structure provided in the embodiment of the present invention is first described below, where the method for manufacturing a semiconductor structure is applied to a process for manufacturing a tensile strained silicon layer, where the tensile strained silicon layer may be used as a layer structure for manufacturing a silicon channel in a transistor, or may be used as a layer structure requiring a tensile strained silicon layer in other scenarios. The method for fabricating the semiconductor structure is described in detail below with reference to the accompanying drawings.
Referring to fig. 1 to 6, a method for manufacturing a semiconductor structure according to an embodiment of the present invention includes:
step10: growing a dielectric layer 12 on a first silicon substrate 11;
step20: growing a relaxed SiGe buffer layer 22 on the second silicon substrate 21 and growing a fully relaxed SiGe strain relaxed layer 23 on the relaxed SiGe buffer layer 22;
step30: bonding the SiGe strain relaxed layer 23 on the second silicon substrate 21 on the dielectric layer 12 on the first silicon substrate 11;
step40: removing the first silicon substrate 11 and the SiGe relaxed buffer layer 22, and thinning the SiGe strain relaxed layer 23;
step50: a tensile strained silicon layer 30 is epitaxially grown on the thinned SiGe strain relaxed layer 23.
In the above scheme, a method for preparing a semiconductor structure for growing a tensile strained silicon layer 30 is provided, in which a SiGe relaxed buffer layer 22 and a fully relaxed SiGe strain relaxed layer 23 are sequentially grown on a second silicon substrate 21, the SiGe strain relaxed layer 23 on the second silicon substrate 21 is bonded to a dielectric layer 12 on a first silicon substrate 11, then the first silicon substrate 11 and the SiGe relaxed buffer layer 22 are removed, the SiGe strain relaxed layer 23 is thinned, and finally, a tensile strained silicon layer 30 is epitaxially grown on the thinned SiGe strain relaxed layer 23, thereby realizing a high-mobility tensile strained silicon layer 30SOI structure. Meanwhile, since the SiGe strain relaxation layer 23 is bonded on the dielectric layer 12 of the first silicon substrate 11 after being prepared on the second silicon substrate 21, impurity contamination, and the like are not caused to the first silicon substrate 11, thereby manufacturing a brand new nanosheet substrate platform having high mobility, less impurity contamination, low impurity contamination, a high-quality stacked structure, and a channel structure. Facilitating subsequent fabrication of structures such as, but not limited to, a tensile strained silicon channel 43 in the tensile strained silicon layer 30 depending on the application scenario, providing a good substrate for FD/GAA (gate-all-on) OI devices. The above steps will be described in detail with reference to the accompanying drawings.
First, referring to fig. 1 and 2, a dielectric layer 12 is grown on a first silicon substrate 11. The first silicon substrate 11 may specifically be a substrate structure such as, but not limited to, a wafer substrate. The pattern top view of the first silicon substrate 11 may be rectangular, square, diamond, circular, etc. but is not limited to one. The first silicon substrate 11 may be a rectangular parallelepiped, a cylinder, a circular truncated cone, a cone, or the like as a whole. Electrical structures such as word lines and bit lines may be formed on the first silicon substrate 11. After forming the electrical structures for word lines, bit lines, etc., a planar surface is formed on the first silicon substrate 11 by depositing a dielectric layer 12. In determining the dielectric layer 12, the material of the dielectric layer 12 may be SiOx, siNx, or Al 2 O 3 The single layer or the laminated combination of (1), wherein the laminated layer can be SiOx, siNx or Al 2 O 3 The laminated layer composed of any two materials in the above can also be SiOx, siNx and Al 2 O 3 The stack of these three materials improves the quality of the dielectric layer 12. Of course, the dielectric layer 12 may be other types of materials.
Next, as shown in fig. 1 and 3, a SiGe relaxed buffer layer 22 is grown on the second silicon substrate 21, and a fully relaxed SiGe strain relaxed layer 23 is grown on the SiGe relaxed buffer layer 22.
Specifically, when the SiGe relaxed buffer layer 22 and the SiGe strain relaxed layer 23 are grown in sequence on the second silicon substrate 21, the SiGe relaxed buffer layer 22 and the SiGe strain relaxed layer 23 are both made of Si 1-a Ge a . Wherein the value of a represents the content ratio of silicon to germanium. The larger a is, the higher the content of germanium is; a smaller indicates a lower content of germanium. Wherein, when the relaxed SiGe buffer layer 22 is grown on the second silicon substrate 21, the value of a may gradually increase from the bottom of the relaxed SiGe buffer layer 22 to the top of the relaxed SiGe buffer layer 22. Then, when the SiGe strain relaxed layer 23 is grown on the SiGe strain relaxed buffer layer 22, the value of a is maximized in the SiGe strain relaxed layer 23, and a in the SiGe strain relaxed layer 23 is a fixed value. By employing the above growth method, the quality of the SiGe strain relaxed layer 23 can be improved, facilitating epitaxial growth of a higher quality strained si layer 30.
When the value range of a is specifically determined, a gradually increases from the value 0 at the bottom of the SiGe relaxed buffer layer 22 to the value max of the SiGe strain relaxed layer 23. I.e. the bottom of the SiGe relaxed buffer layer 22 is initially deposited with only silicon, gradually germanium is added during the gradual upward deposition and the germanium content is gradually increased, and a is at most max when the SiGe strain relaxed layer 23 is deposited. When the value range of max is determined, max can be any value between 0.2 and 0.45, such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45 and the like, so that the quality of the SiGe strain relaxation layer 23 is improved, and the higher-quality tensile strained silicon layer 30 is conveniently grown in an epitaxial mode.
Next, referring to fig. 1 and 4, the SiGe strain relaxed layer 23 on the second silicon substrate 21 is bonded on the dielectric layer 12 on the first silicon substrate 11. I.e., the second silicon substrate 21 is flipped over and the SiGe strain relaxed layer 23 on the second silicon substrate 21 is bonded to the dielectric layer 12 on the first silicon substrate 11. The specific bonding may be any bonding that is capable of bonding the SiGe strain relaxed layer 23 to the dielectric layer 12.
Next, referring to fig. 1 and 5, the first silicon substrate 11 and the SiGe relaxed buffer layer 22 are removed, and the SiGe strain relaxed layer 23 is thinned. In particular, the first silicon substrate 11 and the relaxed buffer layer 22 of SiGe may be removed by any means known in the art. For example, chemical mechanical polishing, dry etching or wet etching may be used. The SiGe strain relaxed layer 23 may be thinned specifically in any manner that enables a reduction of the layer structure. In the specific thinning, the SiGe strain relaxed layer 23 may be thinned until the thickness of the remaining SiGe strain relaxed layer 23 is any value between 5 and 100nm, such as 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc. By preparing the thicker SiGe strain relaxed layer 23 first and then thinning the SiGe strain relaxed layer 23, the quality of the remaining SiGe strain relaxed layer 23 can be improved, facilitating epitaxial growth of a higher quality strained si layer 30.
Next, referring to FIGS. 1 and 6, a tensile strained silicon layer 30 is epitaxially grown on the thinned SiGe strain relaxed layer 23. The epitaxially grown tensile strained si layer 30 on the SiGe strain relaxed layer 23 enables the epitaxially grown si layer to be embodied as the tensile strained si layer 30, thereby realizing a high mobility tensile strained si layer 30SOI structure. Meanwhile, since the SiGe strain relaxed layer 23 is bonded on the dielectric layer 12 of the first silicon substrate 11 after being prepared on the second silicon substrate 21, impurity contamination, and the like are not caused to the first silicon substrate 11, thereby manufacturing a brand new nanosheet substrate platform having high mobility, less impurity contamination, low impurity contamination, a high-quality stacked structure, and a trench structure. Facilitating subsequent fabrication of structures such as, but not limited to, a tensile strained silicon channel 43 in the tensile strained silicon layer 30 depending on the application scenario, providing a good substrate for FD/GAA (gate-all-on) OI devices.
In addition, referring to fig. 7, when a structure using the tensile strained silicon layer 30 is prepared on the first silicon substrate 11, a transistor may be prepared on the first silicon substrate 11, and a tensile strained channel in the transistor may be prepared by using the tensile strained silicon layer 30. In the specific manufacturing process, referring to fig. 7, the source 41 and the drain 42 of the transistor may be manufactured in the strained si layer 30 and the SiGe strain relaxed layer 23, and specifically, a selective etching process may be adopted to etch away a part of the material in the SiGe strain relaxed layer 23 in the stack layer to form a space for manufacturing the source 41 and the drain 42, and the source 41 and the drain 42 may be manufactured by filling or the like. A tensile strained silicon channel 43 connecting the source 41 and drain 42 is then formed on the tensile strained silicon layer 30. Then, as shown in fig. 7, a gate 44 of the transistor is fabricated on the tensile strained silicon channel 43 to form an FDSOI device, which enhances the mobility of the silicon channel in the FDSOI device, and finally realizes the substrate fabrication of the high-mobility FDSOI device.
In addition, as shown in fig. 8, the method for manufacturing a semiconductor structure may further include: repeatedly and alternately growing the SiGe strain relaxed layer 23 and the tensile strained silicon layer 30 on the tensile strained silicon layer 30 to form a stacked structure in which the SiGe strain relaxed layer 23 and the tensile strained silicon layer 30 are repeatedly stacked. The cycle number of the repeated alternate growth is n times, n is any positive integer, and specifically, n is any positive integer larger than 1, so that the GAASOI device with high mobility can be conveniently prepared subsequently.
Specifically, in the fabrication of the gaasii device, the source 41 and the drain 42 of the transistor may be fabricated in a stacked structure, as shown in fig. 8, a selective etching process may be used to etch away a portion of the material in each SiGe strain relaxed layer 23 in the stacked structure to form a space for fabricating the source 41 and the drain 42, and the source 41 and the drain 42 may be fabricated by filling or the like. Thereafter, on each of the tensile strained silicon layers 30 in the stacked structure, a tensile strained silicon channel 43 (not shown in the figure) connecting the source 41 and the drain 42 is formed. The gate 44 of the transistor is then fabricated in a stacked configuration to form a GAASOI device. And the mobility of a silicon channel in the GAASOI device is enhanced, and finally, the substrate preparation of the high-mobility GAASOI device is realized.
In the various embodiments shown above, a semiconductor structure for growing a tensile strained silicon layer 30 is proposed, in which after a SiGe relaxed buffer layer 22 and a fully relaxed SiGe strain relaxed layer 23 are grown in sequence on a second silicon substrate 21, the SiGe strain relaxed layer 23 on the second silicon substrate 21 is bonded to a dielectric layer 12 on a first silicon substrate 11, then the first silicon substrate 11 and the SiGe relaxed buffer layer 22 are removed, the SiGe strain relaxed layer 23 is thinned, and finally, the tensile strained silicon layer 30 is epitaxially grown on the thinned SiGe strain relaxed layer 23, thereby realizing a high mobility tensile strained silicon layer 30SOI structure. Meanwhile, since the SiGe strain relaxed layer 23 is bonded on the dielectric layer 12 of the first silicon substrate 11 after being prepared on the second silicon substrate 21, impurity contamination, and the like are not caused to the first silicon substrate 11, thereby manufacturing a brand new nanosheet substrate platform having high mobility, less impurity contamination, low impurity contamination, a high-quality stacked structure, and a trench structure. Facilitating subsequent fabrication of structures such as, but not limited to, a tensile strained silicon channel 43 in the tensile strained silicon layer 30 depending on the application scenario, providing a good substrate for FD/GAA (gate-all-on) OI devices.
In addition, referring to fig. 2 to 6, a semiconductor structure according to an embodiment of the present invention includes: a first silicon substrate 11, a dielectric layer 12 grown on the first silicon substrate 11, a SiGe strain relaxed layer 23 bonded to the dielectric layer 12, a tensile strained silicon layer 30 epitaxially grown on the SiGe strain relaxed layer 23. Wherein, the SiGe strain relaxation layer 23 is bonded on the dielectric layer 12 by the following method: growing a relaxed SiGe buffer layer 22 on the second silicon substrate 21 and growing a fully relaxed SiGe strain relaxed layer 23 on the relaxed SiGe buffer layer 22; bonding the SiGe strain relaxed layer 23 on the second silicon substrate 21 on the dielectric layer 12 on the first silicon substrate 11; after removing the first silicon substrate 11 and the SiGe relaxed buffer layer 22 and thinning the SiGe strain relaxed layer 23, a tensile strained silicon layer 30 is epitaxially grown on the thinned SiGe strain relaxed layer 23.
In the above scheme, a semiconductor structure for growing a tensile strained silicon layer 30 is provided, in which after a SiGe relaxed buffer layer 22 and a fully relaxed SiGe strain relaxed layer 23 are sequentially grown on a second silicon substrate 21, the SiGe strain relaxed layer 23 on the second silicon substrate 21 is bonded to a dielectric layer 12 on a first silicon substrate 11, then the first silicon substrate 11 and the SiGe relaxed buffer layer 22 are removed, the SiGe strain relaxed layer 23 is thinned, and finally, the tensile strained silicon layer 30 is epitaxially grown on the thinned SiGe strain relaxed layer 23, thereby realizing a high-mobility SOI structure of the tensile strained silicon layer 30. Meanwhile, since the SiGe strain relaxation layer 23 is bonded on the dielectric layer 12 of the first silicon substrate 11 after being prepared on the second silicon substrate 21, impurity contamination, and the like are not caused to the first silicon substrate 11, thereby manufacturing a brand new nanosheet substrate platform having high mobility, less impurity contamination, low impurity contamination, a high-quality stacked structure, and a channel structure. Facilitating subsequent fabrication of structures such as, but not limited to, a tensile strained silicon channel 43 in the tensile strained silicon layer 30 depending on the application scenario, providing a good substrate for FD/GAA (gate-all-on) OI devices.
In addition, referring to fig. 7, a transistor may be fabricated on the first silicon substrate 11, with a tensile strained silicon layer 30 being used to fabricate a tensile strained channel in the transistor. In the specific manufacturing process, referring to fig. 7, the source 41 and the drain 42 of the transistor may be manufactured in the strained si layer 30 and the SiGe strain relaxed layer 23, and specifically, a selective etching process may be adopted to etch away a part of the material in the SiGe strain relaxed layer 23 in the stack layer to form a space for manufacturing the source 41 and the drain 42, and the source 41 and the drain 42 may be manufactured by filling or the like. A tensile strained silicon channel 43 connecting the source 41 and drain 42 is then formed on the tensile strained silicon layer 30. Then, as shown in fig. 7, a gate 44 of the transistor is fabricated on the tensile strained silicon channel 43 to form an FDSOI device, which enhances the mobility of the silicon channel in the FDSOI device, and finally realizes the substrate fabrication of the high-mobility FDSOI device.
Referring to fig. 8, siGe strain relaxed layers 23 and tensile strained silicon layers 30 may be repeatedly and alternately grown on the tensile strained silicon layer 30 to form a stacked structure in which SiGe strain relaxed layers 23 and tensile strained silicon layers 30 are repeatedly stacked; the cycle number of the repeated alternate growth is n times, and n is any positive integer, so that the GAASOI device with high mobility can be prepared conveniently.
Specifically, when a GAASOI device is fabricated, the source 41 and the drain 42 of the transistor may be fabricated in a stacked structure, as shown in fig. 8, a selective etching process may be used to etch away a portion of the material in each SiGe strain relaxed layer 23 in the stack to form spaces for fabricating the source 41 and the drain 42, and the source 41 and the drain 42 may be fabricated by filling or the like. Thereafter, on each of the tensile strained silicon layers 30 in the stacked structure, a tensile strained silicon channel 43 (not shown in the figure) connecting the source 41 and the drain 42 is formed. The gate 44 of the transistor is then fabricated in a stacked configuration to form a GAASOI device. And the mobility of a silicon channel in the GAASOI device is enhanced, and finally, the substrate preparation of the high-mobility GAASOI device is realized.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
growing a dielectric layer on a first silicon substrate;
growing a relaxed SiGe buffer layer on a second silicon substrate and growing a fully relaxed SiGe strain relaxed layer on said relaxed SiGe buffer layer;
bonding said SiGe strain relaxed layer on said second silicon substrate to said dielectric layer on said first silicon substrate;
removing the first silicon substrate and the SiGe relaxed buffer layer, and thinning the SiGe relaxed strain layer;
and epitaxially growing a tensile strained silicon layer on the thinned SiGe strain relaxation layer.
2. The method of manufacturing according to claim 1, wherein said thinning said SiGe strain relaxed layer comprises:
and thinning the SiGe strain relaxation layer until the thickness of the residual SiGe strain relaxation layer is 5-100nm.
3. The method of claim 1 wherein said relaxed SiGe buffer layer and said relaxed SiGe layer are both Si 1-a Ge a ；
The value of a is gradually increased from the bottom of the SiGe relaxed buffer layer to the top of the SiGe relaxed buffer layer and is increased to the maximum in the SiGe strain relaxed layer, and a in the SiGe strain relaxed layer is a fixed value.
4. The method according to claim 3, wherein a gradually increases from a value of 0 at the bottom of the relaxed SiGe buffer layer to a value of max at the relaxed SiGe layer; wherein max ranges from 0.2 to 0.45.
5. The method of claim 1, wherein the dielectric layer is made of SiOx, siNx, or Al 2 O 3 A single layer or a stacked layer combination of (a).
6. The method of claim 1, further comprising:
preparing a source and a drain of a transistor in said tensile strained Si layer and said SiGe strain relaxed layer;
forming a tensile strained silicon channel connecting the source and drain on the tensile strained silicon layer;
fabricating a gate of the transistor on the tensile strained silicon channel to form an FDSOI device.
7. The method of claim 1, further comprising:
repeatedly and alternately growing a SiGe strain relaxation layer and a tensile strained silicon layer on the tensile strained silicon layer to form a stacked structure in which the SiGe strain relaxation layer and the tensile strained silicon layer are repeatedly stacked;
wherein the cycle number of the repeated alternate growth is n times, and n is any positive integer.
8. The method of claim 7, further comprising:
preparing a source electrode and a drain electrode of a transistor in the laminated structure;
forming a tensile strained silicon channel connecting the source and the drain on each tensile strained silicon layer in the stacked structure;
fabricating a gate of the transistor in the stacked structure to form a GAASOI device.
9. A semiconductor structure, comprising:
a first silicon substrate;
a dielectric layer grown on the first silicon substrate;
bonding a SiGe strain relaxed layer attached to said dielectric layer;
a tensile strained silicon layer epitaxially grown on said SiGe strain relaxed layer;
wherein the SiGe strain relaxation layer is bonded on the dielectric layer by adopting the following mode:
growing a relaxed SiGe buffer layer on a second silicon substrate and growing a fully relaxed SiGe strain relaxed layer on said relaxed SiGe buffer layer;
bonding said SiGe strain relaxed layer on said second silicon substrate on said dielectric layer on said first silicon substrate;
and removing the first silicon substrate and the SiGe relaxed buffer layer, and thinning the SiGe strain relaxed layer so as to enable the tensile strain silicon layer to be epitaxially grown on the thinned SiGe strain relaxed layer.
10. The semiconductor structure of claim 9 wherein said tensile strained silicon layer is further repeatedly and alternately grown with a SiGe strain relaxed layer and a tensile strained silicon layer to form a stacked structure of repeated stacking of SiGe strain relaxed layers and tensile strained silicon layers;
wherein the cycle number of the repeated alternate growth is n times, and n is any positive integer.
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| CN116583109A (en) * | 2023-06-27 | 2023-08-11 | 北京超弦存储器研究院 | 3D memory, preparation method thereof and electronic equipment |
| CN116583109B (en) * | 2023-06-27 | 2024-02-02 | 北京超弦存储器研究院 | 3D memory, preparation method thereof and electronic equipment |
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