JP2002076334A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high speed field effect transistor with low power consumption by using the combination of Si and Ge having the same family element as Si. SOLUTION: The roughness of an interface between the distortion applying layer of SiGe and the distortion semiconductor layer of Si deposited thereon, or an interface between the distortion semiconductor layer of Si and the gate insulating layer on it are reduced to an appropriate value, and MOSFET is formed on the distortion semiconductor layer of Si.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device including an insulated gate transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device using a Si-MOS type field effect transistor (Si-MOSFET), power consumption is reduced by reducing device dimensions, operating voltage, etc. according to a so-called scaling rule. Reduction and speeding up. However, recently, when the gate length has been reduced to about 0.1 μm, many problems such as a problem of a short channel effect and a decrease in an operation margin due to the proximity of a drain voltage and a threshold voltage have occurred. .

[0003] Looking at mobility as an index of speeding-up, the various improvements described above have the ironic result of further reducing the mobility of Si in an actual device. Thus, it has become extremely difficult to improve the performance of the conventional Si-MOSFET.

In order to further improve the performance, it is necessary to increase the speed by improving the semiconductor material itself. The use of a so-called compound semiconductor, which is essentially high-speed, is one solution, but it is extremely difficult in terms of integration with the manufacturing technology of Si integrated circuit devices, and the production cost is enormous, so it is practical. Not a good solution.

[0005] Therefore, Si and its congener element G
It is more realistic to provide a semiconductor device having a high-speed field-effect transistor with low power consumption by using a combination such as e.

Specifically, a strain is applied to a channel forming layer in which a channel of a field-effect transistor is formed by a strain applying semiconductor layer so that the mobility of carriers in the channel is made larger than that of the material of the unstrained channel forming layer. This can be achieved by: That is, when the material of the channel forming layer is Si,
By applying strain, the lattice constant in the plane of the Si channel forming layer is made larger than that of unstrained Si.

The fact that when a strain is applied to Si or Ge, the mobility of carriers is increased as compared with Si or Ge which is not subjected to strain is described in M. K .; V. Fischettia
ndS. E. FIG. Laux: J. Appl. Phys. 80
(1996), 2234.

[0008]

As a method of giving a strain to a Si layer, a sufficiently thick Si (1-x) Ge is formed on a Si substrate.
There is a method of growing a SiGe mixed crystal film of (x) and further growing a Si thin film thereon.

When a Si (1-x) Ge (x) mixed crystal film having a sufficient thickness is grown, a transition occurs in the film and the Si (1-x)
The lattice constant in the growth plane of the Ge (x) mixed crystal film is increased, and the bulk S
It is about the same as i (1-x) Ge (x). That is, the Si substrate and the Si
Lattice mismatch with the (1-x) Ge (x) film is reduced. When a Si film is grown on the lattice-relaxed Si (1-x) Ge (x) film thus grown, the Si film is subjected to in-plane biaxial tensile strain.

However, in order to reduce lattice mismatch, Si (1
The transition of the -x) Ge (x) mixed crystal film also results in a marked deterioration in the flatness of the film surface. Even if a MOSFET is manufactured by growing a strained Si layer on the surface having deteriorated flatness as described above, the effect of increasing the mobility due to the strain is canceled out due to an increase in carrier scattering, and a high-performance element is manufactured. It also has an adverse effect on fine lithography, which is essential for lithography.

A first object of the present invention is to provide a semiconductor device including a strained Si layer necessary for performing a fine lithography process while keeping device performance from deteriorating.

Second, a problem to be solved in manufacturing a semiconductor device including a strained Si layer is to reduce the thermal load applied to the strained Si layer during manufacturing as much as possible. In a manufacturing process of a complementary field effect transistor circuit device which is a mainstream of a semiconductor device, a large heat load is applied in a well forming process and an element isolation process. The heat load which does not cause any problem in the conventionally used single-crystal Si substrate can be applied to the semiconductor substrate including the strained Si layer and the SiGe strain applying layer.
Problems such as diffusion of Ge from the Ge strain applying layer and strain relaxation of the strained Si layer may occur. Therefore, reducing the effect of the heat load is a second problem to be solved by the present invention.

In order to obtain good characteristics with a short channel field effect transistor, it is necessary to precisely control an impurity profile in a channel region depth direction.
It is necessary to increase the impurity concentration of the channel part in order to suppress the punch-through current generated with the shortening of the channel.
This lowers the effective mobility of the channel at the same time, which is an obstacle to improving the characteristics. Therefore, it is important to control the three-dimensional impurity profile such that the impurity concentration near the gate insulating film interface where the channel is formed is low, and the impurity concentration deeper than that is high.

A method of implanting Group III elements and Group V elements at different depths by an ion implantation method can be considered. In a conventionally used single-crystal Si substrate, the impurity profile can be relatively easily controlled by this method. However, in the semiconductor substrate including the strained Si layer and the SiGe strain applying layer, SiG
Abnormal diffusion of the dopant in the e-strain applying layer makes it difficult to control the impurity profile. To avoid this problem is a third problem to be solved by the present invention.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems 1 to 3, and has an object to provide an insulated gate transistor capable of operating at high speed in which the problem of the short channel effect is improved and a semiconductor integrated circuit device using the same. To provide.

Another object of the present invention is to provide a manufacturing method suitable for mass-producing such semiconductor devices with good reproducibility.

[0017]

According to the present invention, there is provided the above-described Si substrate.
This is made by paying attention to the influence of the flatness of the (1-x) Ge (x) mixed crystal film surface on the device characteristics.

In order to solve the first problem, the present inventors have repeatedly conducted trial production studies on the correlation between the roughness of each interface between the layers and the device characteristics. Is equivalent to the two-dimensional power spectral density of the roughness).

In particular, the influence of the roughness of the flatness of the interface between the strained Si layer on SiGe and the gate insulating film is great,
It has been found that it is necessary to flatten the interface, that is, the roughness power distribution characteristic of the flatness of the Si layer so as to be equal to or smaller than a predetermined value. When the thickness of the strained Si layer is as thin as 50 nanometers (nm) or less, the roughness of the interface between the SiGe strain applying layer and the strained Si layer also has a significant effect. Was.

When the distribution of the roughness power with respect to the wavelength (corresponding to the period of the irregularities on the surface) is observed, the distribution has a peak at a certain wavelength and a distribution that gradually decreases around the peak. Further, the wavelength showing the maximum roughness power depends on the preparation conditions of the sample and the conditions of the surface polishing. Specifically, at least the flatness of the interface between the Si layer and the gate insulating film has a wavelength component. 0.1 nanometers (nm) to 1
Good device characteristics can be obtained by setting the roughness power in the range of 0 micrometer (μm) to 0.1 square nanometer (square nm) or less, preferably 0.02 square nanometer (square nm) or less. Was found to be. Furthermore, if the flatness of both the interface between the Si layer and the gate insulating film and the interface between the SiGe strain applying layer and the Si layer are within the above ranges, further excellent device characteristics can be obtained. I also found that.

A stacked structure of the Si substrate, the Si (1-x) Ge (x) mixed crystal film (x is a positive value smaller than 1), and the Si strained semiconductor layer satisfying the above conditions. In the manufacture of a semiconductor device having Si, the SiGe strain applying layer is made of Si
It has been found that it is desirable to planarize the surface by chemical mechanical polishing (CMP) after growth on a substrate.

In order to solve the second problem, the present inventors have found that it is best to construct a manufacturing process so that a process for applying a thermal load is performed before forming the strained Si layer. I found it. The specific method is as follows.

First, Si (1-x) G is formed on the Si substrate.
A semiconductor substrate on which an e (x) strain applying layer and a Si strained semiconductor layer are deposited in this order is manufactured. The Si (1-x) Ge (x) strain applying layer and the Si strained semiconductor layer are formed by ultra-high vacuum evacuation chemical vapor deposition (UHVCV).
It is desirable to grow using a method such as D). In addition, the Si strained semiconductor layer may be omitted in this case,
It is desirable to attach a Si layer having excellent chemical stability on the top surface. Ge of SiGe strain applying layer
X, which means the amount, can be any value within the range of 0 to 1, but is preferably about 0.3 to 0.4 in terms of the amount of distortion. This x does not necessarily have to be constant in the film thickness direction. Increasing x as the SiGe strain applying layer grows is also desirable because it has the effect of reducing the threading dislocation density of the strain applying layer.

Further, the semiconductor substrate is not limited to this combination. For example, the semiconductor substrate may be formed between a Si substrate and a SiGe layer.
A strain applying substrate having a so-called SOI structure in which an insulator layer such as 2 is inserted may be used.

Next, a well forming step is performed. The region of the Si layer where the N-type transistor is to be formed is doped with a Group III element by ion implantation or the like to make the conductivity type P-type.
A region for forming the type transistor is doped with a group V element to make the conductivity type N-type. Either step may be omitted depending on the conductivity type and resistivity of the Si layer to be deposited.

Next, an element isolation step is performed on the semiconductor substrate. A method such as local thermal oxidation (LOCOS) or trench isolation can be applied. By optimizing the height difference and the shape of the step between the insulator portion formed in the device isolation step and the active region of the device, the crystal nuclei at the end faces can be formed when the Si layer is selectively epitaxially grown in a later step. The quality of the epitaxially grown layer can be prevented from being deteriorated due to abnormal formation or facet growth, and the characteristics of the transistor and the element isolation characteristics can be kept good.

Next, Si is epitaxially grown on the semiconductor substrate after the well forming step and the element separating step. For this Si growth, it is desirable to use a UHVCVD method or the like that can selectively grow only in the active region other than the element isolation region.

Since Ge may be diffused in the first Si strained semiconductor layer of the semiconductor substrate having undergone the above-described well formation step due to the thermal load in the above-described step, before the second Si layer is formed by epitaxial growth of Si. , 1st S
It is desirable to remove part or most (and in some cases, all) of the i-layer by etching. Also, the second Si
It is preferable to grow the SiGe layer before growing the layer, because the surface contamination layer can be covered.

By using the manufacturing method which solves the second problem, the third problem can be solved. That is, in the well formation step, impurities are added by ion implantation and heat treatment so that the impurity concentration on the surface of the first Si layer becomes 10 17 / cubic centimeter or more. It is desirable to form the second Si layer by performing a process that requires a lower impurity concentration and requires precise control of the impurity profile.

Alternatively, Si for forming the second Si layer
In the early stage of the epitaxial growth process, the impurity is added so that the impurity concentration becomes 10 17 / cubic centimeter or more, and then the impurity is added so that the impurity concentration becomes 10 17 / cubic centimeter or less. good. Since the epitaxial growth is made only of Si and the impurity element, precise control of the impurity concentration becomes possible as compared with the case where both Si and Ge are included. The step of adding impurities so that the impurity concentration becomes 10 17 / cubic centimeter or more at the beginning of the Si epitaxial growth process may be omitted in some cases, and the impurity concentration is immediately increased to 10 17 / cubic centimeter.
A step of adding impurities may be performed so as to be cubic centimeter or less.

In any case, the impurity concentration at the surface of the uppermost Si layer on which the insulated gate transistor is formed is 10
It is desirable that the height be equal to or less than the 17th power / cubic centimeter.

In order not to relax the strain given by the Si (1-x) Ge (x) strain applying layer, the Si strained semiconductor layer (first Si layer) and the epitaxial Si layer (second The thickness of each layer is in the range of 1 to 100 nanometers (nm), and the sum of the thicknesses of both layers is 1
It is desirable to set the range to １００100 nanometers (nm).

According to the present invention, the SiGe region having a flat surface formed on the surface of the substrate,
Si deposited on the region and having a thickness of 100 nm or less and an impurity concentration of 10 17 / cm 3 or less on the surface thereof
A gate electrode provided on the upper surface of the Si layer with an insulating film interposed therebetween.
A semiconductor device in which a channel having a carrier mobility of 800 square centimeters / Vs or more is formed on the surface of the layer can be realized.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 First, a distortion S required to solve the first object of the present invention is described.
The correlation between the roughness of the interface between the i-layer and the gate insulating film and the roughness between the interface between the SiGe strain applying layer and the strained Si layer and device characteristics will be described with reference to actual examples.

First, a method for manufacturing a test device will be described. First, a Si (1-x) Ge (x) strain applying layer is grown on a Si substrate by ultra-high vacuum exhaust chemical vapor deposition (UHVCVD). The surface roughened by the growth of the strain applying layer is flattened by a chemical mechanical polishing (CMP) technique.

Further, in order to prepare various samples, the surfaces of some of the obtained samples are roughened again by a chemical treatment or the like, and the surface roughness of the strain applying layer is controlled to a desired value. next,
On the SiGe strain applying layers having different surface roughness, a Si strained semiconductor layer is grown by UHVCVD. The surface is again flattened by CMP, and a part of the sample is roughened again by chemical treatment, and the surface roughness of the Si strained semiconductor layer is controlled to a desired value.

The thickness of the SiGe strain applying layer is 3 micrometers, the thickness of the Si strain semiconductor layer is 25 nanometers, and the Ge content x of the SiGe strain applying layer is 0 to 0.1 from the first thickness of 2 micrometers. 3 and continuously increased in the film thickness direction, and was constant at 0.3 for the remaining thickness of 1 micrometer.

Next, a gate SiO2 film is formed on these samples by gate thermal oxidation, a polysilicon film is formed by CVD, a gate region is formed by dry etching, impurity ions are implanted into source / drain regions, an interlayer insulating film is formed, and a contact hole is formed. Various MOSFETs for testing were fabricated by sequentially passing through various processes of formation and wiring formation.

In order to evaluate the roughness of the interface between the SiGe strain applying layer and the Si strain semiconductor layer, the surface roughness of the sample immediately before the formation of the Si strain semiconductor layer was observed with an atomic force microscope (AFM), and ASTM E
42.14 The power spectrum was calculated according to the recommendations of the STM / AFM subcommittee. This is Power Spectral Dens
The power P (unit: square nm) is obtained by squaring the FFT (fast Fourier transform) of an image with respect to the image.

In order to evaluate the roughness of the interface between the Si strained semiconductor layer and the gate insulating layer, the gate insulating film was removed by chemical etching after performing gate thermal oxidation, and AF
The measurement was performed by measuring the surface roughness using M.

FIG. 1 is a characteristic diagram (also referred to as a power spectrum) obtained by measuring the power of the roughness with respect to the wavelength distribution corresponding to the surface irregularities at the interface between the SiGe strain applying layer and the Si strain semiconductor layer.
Is shown. As shown by reference numerals 11 to 14 in the figure, the roughness was controlled to four types. FIG. 2 shows a power spectrum of the roughness at the interface between the Si strained semiconductor layer and the gate insulating layer. In this case, the roughness was similarly controlled to four types indicated by reference numerals 21 to 24. Table 1 shows combinations of the roughness values for the 16 types of samples shown in this embodiment.

[0042]

[Table 1]

In the above table, roughness 1 indicates the roughness at the interface between the SiGe strain applying layer and the Si strained semiconductor layer, and roughness 2 indicates the roughness at the interface between the Si strained semiconductor layer and the gate insulating layer (SiO 2 film). Numerals 11 to 14 and 21 to 24 represent the numbers of the characteristic curves given in FIGS. 1 and 2, respectively.

FIG. 3 shows the electrical characteristics of the samples having different interface roughness. The vertical axis in FIG. 3 shows the effective mobility at room temperature (27 ° C.) calculated from the drain current characteristics of the MOSFET, and the horizontal axis shows the electric field intensity generated with the application of the gate voltage. The smaller the carrier scattering at the interface, the higher the effective mobility.

As can be seen from FIG. 3, the mobility of a sample having a large roughness at both interfaces, such as Samples A to D, is the lowest and that of Sample M-D.
The mobility of the sample having both small roughnesses, such as P, is highest. The mobility of the sample EL in which either the interface between the strain applying layer and the strained semiconductor layer or the interface between the strained semiconductor layer and the insulating film is rough also decreases, but the characteristics are improved as compared with the case where both are rough.

That is, it can be seen that both interfaces lower the channel mobility of the MOSFET due to scattering.
In the drawings of this embodiment, only the case where the thickness of the Si strained semiconductor layer is 25 nanometers (nm) is shown.
When the thickness exceeds nanometers (nm), it has been found that the influence of the roughness of the interface between the SiGe strain applying layer and the Si strain semiconductor layer on the mobility is considerably reduced. Further, the roughness required to reduce the influence on the mobility is determined at any one of the interface between the SiGe strain applying layer and the Si strained semiconductor layer and the interface between the Si strained semiconductor layer and the gate insulator (SiO 2 film).
Roughness power of less than 0.1 square nanometer, preferably 0.02 nm over a wavelength range of 0.1 nm to 10 μm
Less than square nanometers.

That is, by setting any one of the interface between the gate insulating film and the Si layer and the interface between the SiGe layer and the Si layer to a flatness having a roughness power within the above range, the sample E in FIG. As shown by the -L characteristic curve, a MOSFET having a channel region mobility of 400 square centimeters / Vs or more in a practical range where the electric field strength to the gate insulating film is 3 × 10 5 to 5 × 10 6 V / cm. Obtained with good reproducibility.

Further, by setting the interface between the SiGe layer and the Si layer to have a flatness having a roughness power within the above range in advance, a thin S layer of 100 nm or less deposited thereon is formed.
It was also found that the flatness of the i-layer, that is, the flatness of the interface between the gate insulating film and the Si layer was set to a roughness power within the above range.

Further, by setting the flatness of both the interfaces within the above range, the electric field strength to the gate insulating film is 3 × 10 3 as shown by the sample MP characteristic curve in FIG.
An extremely excellent MOSFET having a channel mobility of 800 square centimeters / Vs or more in a practical range of 5 to 5 × 10 6 V / cm can be obtained with good reproducibility.

FIG. 4 shows the numerical range of the roughness power.
If the sample has roughness in the hatched region and below (the lower side) in FIG. 4, the decrease in mobility due to scattering becomes so small as to be negligible. The reason that the roughness wavelength range is less than 10 micrometers or more than 0.1 nanometer is that the former has a larger period of undulation even on the surface but is larger than the size of the device, so the characteristics are hardly affected. The latter is because the latter does not affect the scattering of electron waves because even if irregularities having a shorter period are present on the surface, they become considerably smaller than the electron wave function. Second Embodiment Next, an example of a semiconductor device manufacturing process performed to solve the second and third problems will be described below. Sectional views of the semiconductor device in each step are shown in FIGS. 5 (1), (2), (3) and FIG.
(4) and (5).

First, Si (1-x) G is formed on a Si substrate 51.
An e (x) strain applying layer 52 is grown by UHVCVD.
The surface roughened by the growth of the SiGe strain applying layer 52 is planarized by CMP.

Next, the first S is formed on the SiGe strain applying layer 52.
An i-layer (strained semiconductor layer) 53 is grown by UHVCVD. The thickness of the strain applying layer 52 of SiGe is 3 micrometers, the thickness of the strained semiconductor layer 53 of Si is 25 nanometers, and the Ge content x of the strain applying layer 52 is from 0 in the first thickness of 2 micrometers. The thickness was continuously increased to 0.3 in the film thickness direction, and was constant at 0.3 for the remaining thickness of 1 micrometer. Through the above steps, a strained semiconductor substrate is prepared as shown in FIG.

Next, a well forming step is performed on the semiconductor substrate. A region other than the region where the P-type transistor is to be formed is covered with a resist by photolithography, and phosphorus is ion-implanted to make the conductivity type N-type. Similarly, a region other than the region where the N-type transistor is to be formed is covered with a resist, and boron is ion-implanted to make the conductivity type P-type. In these steps, in order to solve the third problem, the impurity concentration on the surface is increased to 10 17 cubic centimeters or more to suppress the occurrence of punch-through in the short channel element.

Next, an element isolation region 54 is formed on the semiconductor substrate.
To form In order to control a step between the element isolation region 54 and the active region 55, a thermal oxide film (SiO 2 film) 56 is formed on the surface of the Si strained semiconductor layer 53, and an amorphous Si thin film 57 is deposited thereon, and photolithography is performed. After covering the surface other than the surface of the element isolation region 54 with a resist, a groove 50 (trench) is dug by reactive ion etching. FIG. 5B shows a state in which the resist is further removed.

Next, the SiO2 was formed by TEOS-CVD.
A film 58 is buried in the trench, and the surfaces thereof are planarized by CMP. This state is shown in FIG.

Further, the amorphous Si thin film 57 is removed by reactive ion etching, the thermal oxide film 56 is removed, and the exposed surface of the first Si layer (strained semiconductor layer) 53 is etched or cleaned. To form a second Si layer 59 by epitaxial growth. At this time, in order to solve the third problem, the impurity concentration of at least the surface region of the second Si layer 59 is increased to 10 17 /
Control to be less than cubic centimeter. This state is shown in FIG.

Next, ion implantation for adjusting the threshold voltage and suppressing punch-through is performed as appropriate independently of the P-type transistor region and the N-type transistor region.

Thereafter, by a normal CMOS transistor manufacturing process, a gate thermal oxide film (SiO 2 film) 65 is formed, a gate electrode 60 is formed by CVD and dry etching of a polysilicon film, and source / drain regions 61 are formed by impurity ion implantation. Formation, formation of an interlayer insulating film 62,
By forming a contact hole and forming a source / drain / gate electrode wiring 63, a semiconductor device according to the present invention is completed. A cross-sectional view of the completed state is shown in FIG.

In the transistor completed through the above process, the strain is applied to the Si channel formation region 53 thereon by the strain applying layer 52 of SiGe, and the roughness of their interface, that is, the flatness is obtained by appropriate CMP. That is, the degree is appropriately controlled, that is, the interface between the SiGe strain applying layer and the Si strain semiconductor layer, the Si strain semiconductor layer and the gate insulator (Si
At least one of the interfaces with the O2 film) has a roughness power of 0.1 square nanometers or less, preferably 0.02 square nanometers or less over a wavelength range of 0.1 nm to 10 μm. After the element isolation step, a Si epitaxial growth layer 59 (this layer functions as an active region or a channel formation region of a transistor since a gate electrode is formed on the upper surface thereof) is formed by controlling the impurity concentration. By suppressing the effect and the decrease in mobility due to impurities, it is possible to realize a current driving capability and a high operation speed which are twice or more as high as those of a device using a normal Si substrate subjected to the same process.

By manufacturing a semiconductor integrated circuit by applying the present invention, it is possible to achieve high speed, high integration, and high performance, and therefore, its industrial value is extremely high.

As described in the above embodiments, when a Si wafer is used as a substrate, a normal IC or LSI manufacturing process is appropriately combined with the manufacturing process of the present invention to obtain a normal IC or LSI. And a higher-performance LSI integrated with the LSI.

As can be understood from the above, according to the present invention, the carrier mobility of the channel portion of the P-channel MOSFET or the N-channel MOSFET is 400 square cm / cm 2. Vs or more, and moreover 800 cm / Vs or more, can be manufactured with good reproducibility, so that a CMOS type semiconductor integrated circuit device that requires particularly high speed operation with low power consumption can be realized. .

In this case, the mobility of both the P-channel type and the N-channel type MOSFETs can be adjusted to the above-mentioned predetermined value. Therefore, it is easy to design a circuit of a CMOS LSI performing a high-performance and complicated function. A CMOS LSI with uniform carrier mobility characteristics can be realized.

[0064]

According to the present invention, the complementary field effect transistor of high speed and low power consumption, which suppresses the scattering caused by the roughening of the interface due to the introduction of the strained semiconductor of Si, and has excellent characteristics constituted by the transistor. A semiconductor integrated circuit device can be realized.

[Brief description of the drawings]

FIG. 1 is a power spectrum characteristic diagram of roughness at an interface between a SiGe strain applying layer and a Si strain semiconductor layer according to the present invention.

FIG. 2 is a power spectrum characteristic diagram of roughness at an interface between a Si strained semiconductor layer and a gate insulating layer according to the present invention.

FIG. 3 is a characteristic diagram showing mobility characteristics of various samples having different interface roughness in Example 1 of the present invention.

FIG. 4 is a graph showing the regions of the roughness of the interface between the SiGe strain applying layer and the Si strain semiconductor layer and the interface between the Si strain semiconductor layer and the gate insulating layer, which are necessary for obtaining good mobility characteristics in Example 1 of the present invention. FIG. 4 is a characteristic diagram for explaining.

FIG. 5 is a cross-sectional view showing a step of manufacturing the field-effect transistor shown in Embodiment 2 of the present invention.

FIG. 6 is a cross-sectional view showing a step of manufacturing the field-effect transistor shown in Embodiment 2 of the present invention.

[Explanation of symbols]

Reference numeral 50: trench, 51: Si substrate, 52: SiGe strain applying layer, 53: first Si layer (strained semiconductor layer), 54: element isolation region, 55: active region, 56: thermal oxide film, 57: amorphous Si Thin film, 58: SiO2 trench filling film, 59
... Second Si layer (Si epitaxial growth layer), 61 ... Source / drain semiconductor region, 60 ... Gate electrode, 65 ...
Gate insulating film.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shinya Yamaguchi 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. F-term in the Central Research Laboratory of the Works (reference) NN02 NN62 NN65

Claims (5)

[Claims] An SiGe region formed on a surface portion of a substrate, a Si layer having a thickness of 100 nm or less formed on the SiGe region, and a gate electrode provided on a surface of the Si layer via an insulating film. Wherein the interface between the Si layer and the insulating film is planarized with a roughness power distribution characteristic of 0.1 square nanometers or less over at least a region under the gate electrode. 2. An interface between the Si layer and the insulating film is flattened with a roughness power distribution characteristic of 0.02 square nanometers or less over at least a region under the gate electrode. The semiconductor device according to claim 1. 3. The surface of a SiGe region provided on a surface of a substrate is flattened by chemical mechanical polishing, and a Si layer is deposited on the flattened SiGe region. A method for manufacturing a semiconductor device, comprising forming a transistor. 4. A circuit element comprising: depositing a first Si layer having a thickness of 100 nm or less on a SiGe region provided on a substrate surface, and partially depositing an insulator on the deposited first Si layer and the SiGe region. An isolation region is formed, and then a second layer having a thickness of 100 nm or less is formed on the first Si layer.
A method for manufacturing a semiconductor integrated circuit device, comprising: depositing a Si layer and forming an insulated gate transistor on the second Si layer. 5. An SiGe region formed on a surface of a substrate, having a thickness of 100 nm or less deposited on the SiGe region and having an impurity concentration of 10 17 / cm 3 on the surface.
The following Si layer and a gate electrode provided above the surface of the Si layer with an insulating film interposed therebetween, and the surface of the Si layer below the gate electrode has a surface area of 800 cm 2 / Vs
A semiconductor device in which a channel having the above carrier mobility is formed.