CN107546177B - Direct band gap Ge channel CMOS integrated device and preparation method thereof - Google Patents

Abstract

The present invention relates to a kind of direct band gap Ge channel CMOS integrated devices and preparation method thereof.The preparation method includes: to choose Si substrate；One Ge layers of growth regulation；Two Ge layers of growth regulation；Form shallow trench isolation；It injects B ion and forms NMOS active area；Gate dielectric layer and grid layer are grown, etching forms PMOS grid and NMOS gate；Form grid protection layer；It etches the 2nd Ge layers, form Ge step at the PMOS grid and NMOS gate position；Grow Si_0.5Ge_0.5Layer；Grid protection layer is removed, forms PMOS source drain electrode and NMOS source-drain electrode using ion implantation technology；It deposits metal and forms contact zone, ultimately form cmos device.The Ge modification mode that the present invention realizes i.e. direct band gap Ge is prepared as the cmos device of channel, increases the carrier mobility of cmos device, while being also equipped with the advantage of monolithic optoelectronic integration.

Description

Direct band gap Ge channel CMOS integrated device and preparation method thereof

Technical field

The present invention relates to technical field of integrated circuits, in particular to a kind of direct band gap Ge channel CMOS integrated device and its Preparation method.

Background technique

Traditional silicon base CMOS (Complementary Metal-Oxide-Semiconductor Transistor) skill Art with the advantages that its low-power consumption, low noise, high input impedance, high integration, good reliability in integrated circuit fields in occupation of master It leads status and constantly advances according to Moore's Law.However, with the development of semiconductor micro-nano processing technology, as device spy Sign size steps into nanometer scale, and the size for further reducing transistor is faced with more and more problem and challenge, such as dissipates Heat is serious, it is big that power consumption is electrically interconnected, and parasitic RC leads to transmission speed decline and the decline of MOSFET element mobility, all limits The further development of integrated circuit.In order to solve these problems, a new development trend is exactly by micro- electricity of existing maturation Son and photoelectron technology combine, give full play to the advanced and mature technology of microelectronic, High Density Integration, it is cheap with And transmission rate, high anti-interference ability and the advantage of low-power consumption that photon is high, realize that silicon based opto-electronics are integrated.Meanwhile in order into one Step improves the carrier mobility of cmos device and then improves the driving current of device, the research of novel mobility channel material As the new way for continuing raising MOSFET performance.

In numerous novel semiconductor materials, Ge receives the extensive concern of each research institution with its exclusive advantage.Its It is all IV race element and crystal structure having the same that advantage, which includes: with Si,；Hole mobility with 4 times of Si (1900cm²/ Vs) and higher electron mobility (3900cm²/Vs)；It is easier to relative to compound semiconductor materials in Si It is integrated on substrate.Ge channel mosfet also receives the extensive concern of industry with its high hole mobility.In addition, in recent years, with The continuous diminution of device size, the continuous reduction of operating voltage and high-k gate dielectric technology it is gradually mature, be Ge channel The application of MOSFET provides good condition.

In this context, Ge MOSFET, which has become, promotes CMOS performance, continues the important technical of Moore's Law.And Significantly, since successful application of the strain gauge technique in Si MOSFET, strain gauge technique is combined and introduces Ge MOSFET It is also the research emphasis of Ge CMOS technology.The study found that can effectively promote Ge half by applying certain effect to Ge material The carrier mobility of conductor.Particularly, if further increasing applied stress intensity, Ge can be changed by indirect band-gap semiconductor For direct band-gap semicondictor, carrier mobility will be further enhanced.Using direct band gap Ge as the cmos device of channel, Its carrier mobility and driving current can not only be improved, and completely compatible with current microelectronics prevailing technology, be high speed device Part and circuit provide another new technology evolutionary path.

However, the critical issue faced at present is that the Ge material for how preparing large strain realizes Ge material band gap type Transformation, and how to design, realize the direct band gap Ge cmos device of high carrier mobility.

Summary of the invention

Therefore, a kind of direct band gap Ge channel is proposed to solve technological deficiency and deficiency, the present invention of the existing technology CMOS integrated device and preparation method thereof.

Specifically, a kind of preparation side for direct band gap Ge channel CMOS integrated device that one embodiment of the invention proposes Method, comprising:

S101, n-type doping monocrystalline silicon (001) substrate is chosen；

S102, at 275 DEG C~325 DEG C on the single crystal Si substrate epitaxial growth with a thickness of the first Ge layers of 50nm, To avoid crystal quality loss；

S103, at 500 DEG C~600 DEG C, growth thickness is the 2nd Ge layers of 900~950nm on the first Ge layer；

S104, at 750 DEG C~850 DEG C, in H₂It anneals 10~15 minutes in atmosphere；

S105, in 75 DEG C of H₂O₂In solution, immersing the time is 10 minutes, forms GeO in the 2nd Ge layer surface₂It is blunt Change layer；

S106, using CVD process layer with a thickness of the Si of 150~200nm₃N₄Layer；

S107, photoetching shallow trench isolation region, using dry etch process, in the Si₃N₄Layer, the GeO₂It is passivation layer, described 2nd etches the shallow slot that depth is 300~500nm in Ge layers；

S108, using CVD technique at 750 DEG C~850 DEG C, deposit SiO in the shallow slot₂Material, by the shallow slot It fills up；

S109, the Si is removed using CMP process₃N₄The SiO of layer surface₂Material, and hot phosphorus is utilized under the conditions of 180 DEG C Sour wet processing etches the Si₃N₄Layer；

S110, using ion implantation technology in the GeO₂B ion is injected in passivation layer surface specific region, forms p type island region Domain is to form NMOS active area；

S111, at 250 DEG C~300 DEG C, use atom layer deposition process deposition thickness for the HfO of 2~3nm₂Material is made For gate dielectric layer；

S112, using CVD technique, growth thickness is 110nm TaN material as grid layer at 750 DEG C~850 DEG C；

S113, the TaN material, the HfO that specified region is etched using selective etch technique₂Material and described GeO₂Passivation layer formation NMOS gate and PMOS grid；

It S114, in the described 2nd Ge layers and the NMOS gate and the PMOS gate surface deposition thickness is 10~20nm SiO₂Material；

S115, using CVD technique in the SiO₂Material surface deposition thickness is the Si of 20~30nm₃N₄Material；

S116, the NMOS gate and the PMOS top portions of gates and side wall place are removed using selective etch technique etching SiO in addition₂Material and Si₃N₄Material forms grid protection layer on the NMOS gate surface and the PMOS gate surface；

S117, retain the NMOS gate using photoetching process exposure photo-etching glue in entire substrate surface smearing photoresist The photoresist on surface and the PMOS gate surface；

S118, the described 2nd Ge layers that the entire substrate surface is etched using sense coupling technique, Form Ge step；

S119, removal photomask surface glue；

S120, at 500 DEG C~600 DEG C, using silane, germane as gas source, using chemical vapor deposition process in the Ge Step surrounding growth with a thickness of 20nm Si_0.5Ge_0.5Material；

S121, the SiO is removed using wet-etching technology₂Material and the Si₃N₄The gate protection that material is formed Layer；

S122, photoresist is smeared on surface, carries out B ion implanting using self-registered technology and forms PMOS source drain electrode, removal Photoresist；

S123, photoresist is smeared on surface, carries out P ion using self-registered technology and inject to form NMOS source-drain electrode, removes Photoresist；

S124, using CVD process deposits with a thickness of the BPSG of 20~30nm to form dielectric layer；

S125, contact hole and the contact of NMOS source and drain are missed using the formation of dielectric layer described in nitric acid and hf etching PMOS source Hole；

It S126, is 10~20nm metal W, formation PMOS source drain contact and NMOS using electron beam evaporation process deposition thickness Source and drain contact；

S127, the metal W that specified region is etched away using selective etch technique are formed source-drain area electrode, ultimately formed Modified Ge channel NMOS device.

A kind of direct band gap Ge channel CMOS integrated device that another embodiment of the present invention proposes, comprising: Si substrate layer, First Ge layers, the 2nd Ge layers and Si_0.5Ge_0.5Layer, GeO₂Passivation layer, HfO₂Gate dielectric layer, TaN grid layer；Wherein, described direct Prepared by band gap Ge channel CMOS integrated device method as described in above-described embodiment forms.

A kind of preparation method for direct band gap Ge channel CMOS integrated device that another embodiment of the present invention proposes, packet It includes:

Choose Si substrate；

At one Ge layers of the Si substrate surface growth regulation；

At two Ge layers of the first Ge layer surface growth regulation；

In the described 2nd Ge layers of interior formation shallow trench isolation；

In the 2nd Ge layer specific region, injection B ion forms NMOS active area；

Gate dielectric layer and grid layer are continuously grown in the 2nd Ge layer surface, selective etch technique etches the grid and is situated between Matter layer and the grid layer form PMOS grid and NMOS gate；

Grid protection layer is formed in the PMOS grid and the NMOS gate surface；

Etch the described 2nd Ge layers of formation Ge step at the PMOS grid and NMOS gate position；

Si is grown in the 2nd Ge layer surface using epitaxy technique_0.5Ge_0.5Layer；

The grid protection layer is removed, forms PMOS source drain electrode and NMOS source-drain electrode using ion implantation technology；

Contact zone is formed in PMOS source drain electrode and the NMOS source and drain pole surface deposited metal, it is described to ultimately form Direct band gap Ge channel CMOS integrated device.

In one embodiment of invention, first temperature is less than the second temperature.

In one embodiment of invention, the range of first temperature is 275 DEG C~325 DEG C；The second temperature Range is 500 DEG C~600 DEG C.

In one embodiment of the invention, in the described 2nd Ge layers of interior formation shallow trench isolation, comprising:

Utilize CVD process deposits Si₃N₄Layer；

Photoetching shallow trench isolation region, using dry etch process, in the Si₃N₄Layer, the described 2nd Ge layers of interior etching form shallow Slot；

SiO is deposited in the shallow slot using CVD technique₂Material fills up the groove；

The Si is removed using CMP process₃N₄The SiO of layer surface₂Material, and using described in hot phosphoric acid wet processing etching Si₃N₄Layer.

In one embodiment of the invention, gate protection is formed in the PMOS grid and the NMOS gate surface Layer, comprising:

SiO is deposited on the described 2nd Ge layers, the PMOS grid and the NMOS gate surface₂Material；

Using CVD technique in the SiO₂Material surface deposits Si₃N₄Material；

Using selective etch technique etching except at the top of the PMOS grid and the NMOS gate and in addition to side wall place The SiO₂Material and the Si₃N₄Material forms grid protection layer in the PMOS grid and the NMOS gate surface.

In one embodiment of the invention, Ge layers of etching the described 2nd is at the PMOS grid and NMOS gate position Form Ge step, comprising:

Smear photoresist in entire substrate surface, using photoetching process exposure photo-etching glue, retain the PMOS grid and The photoresist on NMOS gate surface；

The described 2nd Ge layers of the entire substrate surface are etched using sense coupling technique, forms institute State Ge step；

Remove photomask surface glue.

In one embodiment of the invention, Si is grown in the 2nd Ge layer surface_0.5Ge_0.5Layer, comprising:

At 500 DEG C~600 DEG C, using silane, germane as gas source, using chemical vapor deposition process in the Ge step week Enclose the Si that growth thickness is 20nm_0.5Ge_0.5Material.

A kind of direct band gap Ge channel CMOS integrated device that another embodiment of the present invention proposes, Si substrate layer, first Ge layers, the 2nd Ge layers and Si_0.5Ge_0.5Layer, GeO₂Passivation layer, HfO₂Gate dielectric layer, TaN grid layer；Wherein, the direct band gap Prepared by Ge channel CMOS integrated device method as described in above-described embodiment forms.

Above-described embodiment, the CMOS of Ge modification mode and direct band gap Ge based on the realization of prior art condition as channel The carrier mobility of cmos device is effectively promoted in device preparation method.And direct band gap Ge material is due to its current-carrying Sub- combined efficiency greatly improves, and applies also for photonic device active layer.Therefore, direct band gap Ge proposed by the invention CMOS also has the advantage of monolithic optoelectronic integration.Specific advantage is as follows:

1, the process of cmos device of the present invention and existing Si ic process compatibility, technique manufacture, reduce at Present aspect has fairly obvious advantage；

2, the present invention is based on hypo-hyperthermia two-step growth methods to prepare Ge material, and is introduced and opened using selective epitaxial SiGe Stress, obtained direct band gap Ge crystalline quality of material are high；

3, the channel material of CMOS of the present invention is direct band gap Ge material, is had relative to traditional Ge material carrier mobility Very big promotion, to improve the electric current driving and frequency characteristic of cmos device；

4, the direct band gap Ge material that the present invention realizes, carrier mobility is high, can be applied to monolithic optoelectronic integration, can Enhance the key performances such as circuit function, speed.

Through the following detailed description with reference to the accompanying drawings, other aspects of the invention and feature become obvious.But it should know Road, which is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they only try hard to concept Ground illustrates structure and process described herein.

Detailed description of the invention

Below in conjunction with attached drawing, specific embodiments of the present invention will be described in detail.

Fig. 1 is a kind of process flow chart of direct band gap Ge channel CMOS integrated device provided in an embodiment of the present invention；

Fig. 2 is a kind of schematic top plan view of direct band gap Ge structure provided in an embodiment of the present invention；

Fig. 3 a- Fig. 3 z is a kind of technique signal of direct band gap Ge channel CMOS integrated device provided in an embodiment of the present invention Figure.

Specific embodiment

In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.

Embodiment one

Referring to Figure 1, Fig. 1 is a kind of technique of direct band gap Ge channel CMOS integrated device provided in an embodiment of the present invention Flow chart.This method comprises the following steps:

Step a, Si substrate is chosen；

Step b, at one Ge layers of the Si substrate surface growth regulation；

Step c, at two Ge layers of the first Ge layer surface growth regulation；

Step d, in the described 2nd Ge layers of interior formation shallow trench isolation；

Step e, in the 2nd Ge layer specific region, injection B ion forms NMOS active area；

Step f, gate dielectric layer and grid layer are continuously grown in the 2nd Ge layer surface, selective etch technique etches institute It states gate dielectric layer and the grid layer forms PMOS grid and NMOS grid

Step g, grid protection layer is formed in the PMOS grid and the NMOS gate surface；

Step h, Ge step is formed at Ge layers of etching the described 2nd, the PMOS grid and NMOS gate position；

Step i, Si is grown in the 2nd Ge layer surface using epitaxy technique_0.5Ge_0.5Layer；

Step j, the grid protection layer is removed, forms PMOS source drain electrode and NMOS source-drain electrode using ion implantation technology；

Step k, contact zone is formed in PMOS source drain electrode and the NMOS source and drain pole surface deposited metal, with most end form At the direct band gap Ge channel CMOS integrated device.

Wherein, in step b and step c, first temperature is less than the second temperature.Further, first temperature The range of degree is 275 DEG C~325 DEG C；The range of the second temperature is 500 DEG C~600 DEG C.

Optionally, step d can specifically include:

Step d1, CVD process deposits Si is utilized₃N₄Layer；

Step d2, photoetching shallow trench isolation region, using dry etch process, in the Si₃N₄Layer, the described 2nd Ge layers of interior quarter Erosion forms shallow slot；

Step d3, SiO is deposited in the shallow slot using CVD technique₂Material fills up the groove；

Step d4, the Si is removed using CMP process₃N₄The SiO of layer surface₂Material, and carved using hot phosphoric acid wet processing Lose the Si₃N₄Layer

Optionally, step g is specifically included:

Step g1, SiO is deposited on the described 2nd Ge layers, the PMOS grid and the NMOS gate surface₂Material；

Step g2, using CVD technique in the SiO₂Material surface deposits Si₃N₄Material；

Step e3, using selective etch technique etching except at the top of the PMOS grid and the NMOS gate and at side wall Other than the SiO₂Material and the Si₃N₄Material forms grid in the PMOS grid and the NMOS gate surface and protects Sheath.

Optionally, step h, comprising:

Step h1, photoresist is smeared in entire substrate surface retain the PMOS grid using photoetching process exposure photo-etching glue The photoresist of pole and NMOS gate surface；

Step h2, the 2nd Ge of the entire substrate surface is etched using sense coupling technique Layer, forms the Ge step；

Step h3, photomask surface glue is removed.

Wherein, for step, concrete technology can be with are as follows:

At 500 DEG C~600 DEG C, using silane, germane as gas source, using chemical vapor deposition process in the Ge step week Enclose the Si that growth thickness is 20nm_0.5Ge_0.5Material；Wherein, SiH₄Volume flow is 5mL/min, GeH₄Volume flow is 2mL/ Min, growth time 1h.

The working principle of the invention specifically:

Modified Ge technology be it is a kind of by introduced in monocrystalline Ge certain stress make its by indirect band gap transitions directly Bandgap semiconductor material further increases the technology of its carrier mobility.Modified Ge material, due to energy level splitting, effective matter Amount reduction etc., carrier mobility further increases, and is applied to microelectronic component and its integrated circuit, and speed will be mentioned significantly It rises；Under certain condition, band gap conversion can even occur for modified Ge, become direct band gap material from indirect bandgap material, carry It flows sub- combined efficiency to greatly improve, is applied to opto-electronic device, luminous efficiency will be substantially improved；Meanwhile direct band gap situation Lower Ge material carrier mobility is high, and the modified material is integrated applied to silicon-based monolithic photoelectricity, can enhance circuit function, speed etc. Key performance.Currently, the Ge modification technology of primary study has following three types both at home and abroad: 1., by low-intensity tensile stress and N-shaped mixing Miscellaneous adjusting, by the material of direct band gap subject to Ge material modification；2., apply high-intensitive tensile stress, be changed into Ge material directly Tape splicing gap material；3., using the means (typical as GeSn alloy) of alloying, obtain the modified Ge material of direct band gap.It is ideal Stress incorporation way should have many advantages, such as adjustable stress, process compatible, lattice zero defect, select appropriate stress introducing side Method is to prepare the premise of high performance strained Ge cmos device.

Based on these principles, Fig. 2 is referred to, Fig. 2 is a kind of bowing for direct band gap Ge structure provided in an embodiment of the present invention Depending on schematic diagram.The present invention obtains the straight of better quality by selective epitaxial germanium silicon (SiGe) the introducing tensile stress around Ge Tape splicing gap Ge material.Concrete principle is the SiGe material since the lattice constant of Ge is bigger than sige material, below source and drain areas Material will be forced to adapt to the lattice constant of Ge material, therefore SiGe transverse direction lattice will be by tensile stress；And above source and drain areas Sige material has reached relaxed state since thickness is thicker.Since total device length remains unchanged, with SiGe transverse direction lattice Diminution, cause the Ge material of central area will be by tensile stress.In addition, directly use Ge material expensive as substrate, It is unfavorable for large-scale application.Current solution is to prepare Ge epitaxial layer on a si substrate, and epitaxial Ge material is most common Method is hypo-hyperthermia two-step growth method.This method elder generation low-temperature epitaxy a thin layer Ge inhibits due to caused by big lattice mismatch Island growth.High growth temperature main body Ge epitaxial layer again.Compared with traditional graded buffer layer growth method, this approach reduce gradual changes Thickness degree, and Ge epi-layer surface roughness is significantly reduced.

To sum up, the CMOS the present invention is based on the Ge modification mode and direct band gap Ge of the realization of prior art condition as channel The carrier mobility of cmos device is effectively promoted in device preparation method.And direct band gap Ge material is due to its current-carrying Sub- combined efficiency greatly improves, and applies also for photonic device active layer.Therefore, direct band gap Ge proposed by the invention CMOS also has the advantage of monolithic optoelectronic integration.

Embodiment two

Referring to Fig. 3 a- Fig. 3 z, Fig. 3 a- Fig. 3 z is a kind of direct band gap Ge channel CMOS collection provided in an embodiment of the present invention At the process schematic representation of device, on the basis of the above embodiments, the present embodiment will be in more detail to technique stream of the invention Journey is introduced.This method comprises:

S101, substrate are chosen: as shown in Figure 3a, selection N-type silicon (Si) substrate slice 001 is original material, and carries out surface Cleaning, to remove protective layer and impurity.

S102, two-step method grow epitaxial germanium layer:

S1021, using the method for chemical vapor deposition (CVD), on substrate, with two method growing n-type Ge of low and high temperature (001) film, doping concentration are 1~5 × 10¹⁶cm^-3；

S1022, as shown in Figure 3b, " low temperature " Ge ((LT-Ge) film of one layer of 50nm thickness of growth at 275~325 DEG C 002.The relaxation of most of elastic stress occurs in Ge layers of low temperature less than 10 nanometers, but to avoid crystal quality loss from needing thickness Spend Ge layers of low temperature of larger (being greater than 27 nanometers).Therefore the present invention is set as 50nm for LT-Ge layers.Low growth temperature presses down simultaneously The relaxed stress that the formation and dislocation for having made the three-dimensional island Ge are formed；

S1023, as shown in Figure 3c, under 500~600 DEG C of growth temperature, deposit the Ge layer 003 of 900-950nm；

It S1024, is to improve lattice quality, in H₂750~850 DEG C of annealing in atmosphere (in fixed a temperature or circulation) No more than 10-15 minutes.

S1025, in order to obtain good electrology characteristic and stability at Ge channel and MOS oxide interface, need The surface Ge forms one layer of GeO₂Passivation layer.Method is the H for placing the substrate in 75 DEG C₂O₂In solution, immersing the time is 10 minutes, The surface Ge will form one layer of very thin GeO₂Passivation layer 004, as shown in Figure 3d.

S103, shallow-trench isolation technology:

Shown in S1031, Fig. 3 e, using the method for CVD, the Si that a layer thickness is about 200nm is deposited₃N₄005 as chemistry The stop-layer of mechanical polishing；

Shown in S1032, Fig. 3 f, photoetching shallow trench isolation region, using dry etch process, NMOS and PMOS device isolated area are carved Lose the shallow slot that depth out is 300~500nm；Using the method for CVD, at 750~850 DEG C, titanium dioxide is deposited in crystal column surface Silicon (SiO₂) 006, fill up shallow slot；

Shown in S1033, Fig. 3 g, the oxide layer on surface is removed with the method for chemically mechanical polishing, and is used under the conditions of 180 DEG C Hot phosphoric acid wet etching removes Si₃N₄。

S104, p-well is formed:

As illustrated in figure 3h, the molding of photoresist 007 is to stop ion implanting, then carries out boron ion injection, forms localized p-type area Domain, for manufacturing NMOS tube.

S105, CMOS gate is formed:

S1051, as shown in figure 3i at 250~300 DEG C, deposits 2~3nm using the method for atomic layer deposition (ALD) Thick hafnium oxide (HfO₂) layer 008；

S1052, as shown in Fig. 3 j, using the method for chemical vapor deposition (CVD) at 750~850 DEG C, surface deposition one The tantalum nitride (TaN) 009 of layer 110nm thickness；

S1053, as shown in figure 3k by photoetching and etches the HfO in other regions using chlorine based plasma₂With TaN shape At gate regions.

S106, protection grid.Grid must obtain during carrying out source and drain etching and selective germanium and silicon epitaxial growth To protection.

S1061, as shown in Fig. 3 l, gate surface deposit one layer of thin SiO₂Layer 010, thickness is about 10nm；

S1062, as shown in figure 3m, with chemical vapor deposition with a thickness of the Si of 20~30nm₃N₄Layer 011 is as sacrificial Domestic animal protective layer, effect are that protection grid is without damage in source and drain areas etching and selective germanium and silicon epitaxial growth course, separately The self-registered technology of source and drain ion implanting is not influenced outside；

S1063, as shown in figure 3n etches the SiO in addition to grid₂And SiN layer.

S107, selective epitaxial sige material.

S1071, photoetching, gluing and selection region exposure.As shown in Fig. 3 o, photoresist 012 in central reservations domain, four The photoresist in week is etched away；

S1072, etching Ge material.As shown in Fig. 3 p, in CF₄And SF₆In gaseous environment, using inductively coupled plasma (ICP) method etches.Due to the etch resistance of photoresist, the Ge material at center retained for central area；The four of etching grid All regions；

S1073, at 500~600 DEG C, using silane, germane as gas source, using chemical vapor deposition (CVD) technology sudden and violent The Si of one layer of 20nm thickness is grown on the Si substrate of exposing_0.5Ge_0.5Layer 013, wherein SiH₄Volume flow is 5mL/min, GeH₄Body Product flow is 2mL/min, and growth time 1h, Fig. 3 q are its top view main views as shown in Fig. 3 r；

S1074, such as Fig. 3 s shows, the Si of grid covering is removed using wet etching mode₃N₄And SiO₂。

S108, CMOS source and drain areas is formed:

S1081, ion implanting form PMOS source drain region.As shown in Fig. 3 t, region gluing 015 is specified in NMOS device, is adopted With self-registered technology, boron (B) injection is carried out to the source-drain area of PMOS, source-drain area is formed, later in 250~300 DEG C of nitrogen environments Lower rapid thermal annealing (RTA) 30s forms source-drain electrode；

S1082, ion implanting form NMOS source-drain area.As shown in Fig. 3 u, region gluing 016 is specified in PMOS device, is adopted With self-registered technology, phosphorus (P) injection is carried out to the source-drain area of NMOS, source-drain area is formed, later in 250~300 DEG C of nitrogen environments Lower rapid thermal annealing (RTA) 30s forms source-drain electrode.

S109, deposition CMOS electrode:

S1091, metallization medium layer.As shown in Fig. 3 v, the BPSG of 20~30nm is deposited using chemical meteorology deposition (CVD), Dielectric layer (PMD) 017 is formed, moving iron can be captured by mixing BPSG, damage device performance to prevent them to be diffused into grid；

S1092, etching contact hole.As shown in Fig. 3 w, source and drain contact hole is formed with nitric acid and hf etching BPSG；

S1093, deposited metal.As shown in Fig. 3 x, using the tungsten (W) 018 of electron beam evaporation deposition 10~20nm thickness, formed Source and drain contact；

S1094, etching metal.As shown in Fig. 3 y, the metal W that selective eating away specifies region is carved using etching technics, is adopted Planarization process is carried out with chemically mechanical polishing (CMP)；

S1095, passivation.As shown in Fig. 3 z, the silicon nitride 019 of 20~30nm is deposited using chemical meteorology deposition (CVD), is used In passivation dielectric.

Embodiment three

Refer to Fig. 3 z, a kind of direct band gap Ge channel CMOS integrated device provided in an embodiment of the present invention, comprising: Si lining Bottom, the first Ge layers, the 2nd Ge layers and Si_0.5Ge_0.5Layer, GeO₂Passivation layer, HfO₂Gate dielectric layer, TaN grid layer；Wherein, described Prepared by direct band gap Ge channel CMOS integrated device method as described in above-described embodiment forms.

In conclusion specific case used herein is to direct band gap Ge channel CMOS integrated device of the present invention and its system The principle and embodiment of Preparation Method is expounded, method of the invention that the above embodiments are only used to help understand And its core concept；At the same time, for those skilled in the art, according to the thought of the present invention, in specific embodiment and There will be changes in application range, in conclusion the contents of this specification are not to be construed as limiting the invention, the present invention Protection scope should be subject to the attached claims.

Claims (2)

1. a kind of preparation method of direct band gap Ge channel CMOS integrated device characterized by comprising

S101, n-type doping single crystalline Si (001) substrate is chosen；

S102, epitaxial growth is on the single crystal Si substrate with a thickness of the first Ge layers of 50nm at 275 DEG C~325 DEG C, to keep away Exempt from crystal quality loss；

S103, at 500 DEG C~600 DEG C, growth thickness is the 2nd Ge layers of 900~950nm on the first Ge layer；

S104, at 750 DEG C~850 DEG C, in H₂It anneals 10~15 minutes in atmosphere；

S105, in 75 DEG C of H₂O₂In solution, immersing the time is 10 minutes, forms GeO in the 2nd Ge layer surface₂Passivation layer；

S106, using CVD process layer with a thickness of the Si of 150~200nm₃N₄Layer；

S107, photoetching shallow trench isolation region, using dry etch process, in the Si₃N₄Layer, the GeO₂Passivation layer, described second The shallow slot that depth is 300~500nm is etched in Ge layers；

S108, using CVD technique at 750 DEG C~850 DEG C, deposit SiO in the shallow slot₂Material fills up the shallow slot；

S109, the Si is removed using CMP process₃N₄The SiO of layer surface₂Material, and it is wet using hot phosphoric acid under the conditions of 180 DEG C Method technique etches the Si₃N₄Layer；

S110, using ion implantation technology in the GeO₂Passivation layer surface specific region inject B ion, formed p type island region domain to Form NMOS active area；

S111, at 250 DEG C~300 DEG C, use atom layer deposition process deposition thickness for the HfO of 2~3nm₂Material is situated between as grid Matter layer；

S112, using CVD technique, growth thickness is 110nm TaN material as grid layer at 750 DEG C~850 DEG C；

S113, the TaN material, the HfO that specified region is etched using selective etch technique₂Material and the GeO₂It is blunt Change layer and forms NMOS gate and PMOS grid；

It S114, in the described 2nd Ge layers and the NMOS gate and the PMOS gate surface deposition thickness is 10~20nm's SiO₂Material；

S115, using CVD technique in the SiO₂Material surface deposition thickness is the Si of 20~30nm₃N₄Material；

S116, it is etched in addition to the NMOS gate and the PMOS top portions of gates and side wall place using selective etch technique SiO₂Material and Si₃N₄Material forms grid protection layer on the NMOS gate surface and the PMOS gate surface；

S117, retain the NMOS gate surface using photoetching process exposure photo-etching glue in entire substrate surface smearing photoresist With the photoresist of the PMOS gate surface；

S118, the described 2nd Ge layers that the entire substrate surface is etched using sense coupling technique, are formed Ge step；

S119, removal photomask surface glue；

S120, at 500 DEG C~600 DEG C, using silane, germane as gas source, using chemical vapor deposition process in the Ge step Surrounding growth with a thickness of 20nm Si_0.5Ge_0.5Material；

S121, the SiO is removed using wet-etching technology₂Material and the Si₃N₄The grid protection layer that material is formed；

S122, photoresist is smeared on surface, carries out B ion implanting using self-registered technology and form PMOS source drain electrode, removes photoetching Glue；

S123, photoresist is smeared on surface, carries out P ion using self-registered technology and inject to form NMOS source-drain electrode, removes photoetching Glue；

S124, using CVD process deposits with a thickness of the BPSG of 20~30nm to form dielectric layer；

S125, contact hole and NMOS source and drain contact hole are missed using the formation of dielectric layer described in nitric acid and hf etching PMOS source；

It S126, is 10~20nm metal W, formation PMOS source drain contact and NMOS source and drain using electron beam evaporation process deposition thickness Contact；

S127, the metal W that specified region is etched away using selective etch technique are formed source-drain area electrode, ultimately form modification Ge channel NMOS device.

2. a kind of direct band gap Ge channel CMOS integrated device characterized by comprising Si substrate layer, the first Ge layers, the 2nd Ge Layer and Si_0.5Ge_0.5Layer, GeO₂Passivation layer, HfO₂Gate dielectric layer, TaN grid layer；Wherein, the direct band gap Ge channel CMOS collection It is prepared and is formed by method described in claim 1 at device.