CN107546177A - Direct band gap Ge channel CMOS integrated devices and preparation method thereof - Google Patents
Direct band gap Ge channel CMOS integrated devices and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to a kind of direct band gap Ge channel CMOS integrated devices and preparation method thereof.The preparation method includes：Choose Si substrates；The Ge layers of growth regulation one；The Ge layers of growth regulation two；Form shallow trench isolation；Inject B ions and form NMOS active areas；Gate dielectric layer and grid layer are grown, etching forms PMOS grids and NMOS gate；Form grid protection layer；Etch the 2nd Ge layers, the PMOS grids and NMOS gate opening position and form Ge steps；Grow Si0.5Ge0.5Layer；Grid protection layer is removed, PMOS source drain electrode and NMOS source-drain electrodes are formed using ion implantation technology；Deposit metal and form contact zone, ultimately form cmos device.The Ge modification modes that the present invention realizes i.e. direct band gap Ge is prepared as the cmos device of raceway groove, adds the carrier mobility of cmos device, while be also equipped with the advantage of monolithic optoelectronic integration.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of direct band gap Ge raceway grooves
CMOS integrated devices and preparation method thereof.
Background technology
Traditional silicon base CMOS (Complementary Metal-Oxide-Semiconductor
Transistor) technology is with its low-power consumption, low noise, high input impedance, high integration, reliable
The advantages that property is good is in occupation of leading position and continuous according to Moore's Law in integrated circuit fields
Advance.However, with the development of semiconductor micro-nano process technology, work as device feature size
Nanometer scale is stepped into, the size for further reducing transistor is faced with the problem of more and more
And challenge, such as radiating, serious, to be electrically interconnected power consumption big, parasitic RC cause transmission speed decline and
The problems such as MOSFET element mobility declines, all limits the further development of integrated circuit.
In order to solve these problems, a new development trend is exactly by existing ripe microelectronics and light
Electronic technology combines, and gives full play to the advanced and mature technology of microelectronic, high density collection
Into, cheap and high photon transmission rate, high noise immunity and the advantage of low-power consumption,
Realize that silicon based opto-electronicses integrate.Meanwhile in order to further improve the carrier mobility of cmos device
Rate and then the driving current for improving device, the research of new mobility channel material, which turns into, to be continued
Improve the new way of MOSFET performances.
In numerous novel semiconductor materials, Ge receives each research aircraft with its exclusive advantage
The extensive concern of structure.Its advantage includes：It is all IV races element with Si and there is identical crystal
Structure；Hole mobility (1900cm with 4 times of Si2/ Vs) and higher electronics
Mobility (3900cm2/Vs)；It is easier on a si substrate relative to compound semiconductor materials
It is integrated.Ge channel mosfets also receive the extensive concern of industry with its high hole mobility.
In addition, in recent years, with the continuous diminution of device size, the continuous reduction of operating voltage, with
And high-k gate dielectric technology is progressively ripe, for Ge channel mosfets application provide it is good
Good condition.
In this context, Ge MOSFET have turned into lifting CMOS performances, continue Moore's Law
Important technical.And significantly, since strain gauge technique is in Si MOSFET
Successful application, it is also grinding for Ge CMOS technologies that strain gauge technique, which is combined, and introduces Ge MOSFET
Study carefully emphasis.Research is found, by applying certain effect to Ge materials, can effectively lift Ge
The carrier mobility of semiconductor.Particularly, if further increase applies stress intensity, Ge
Direct band-gap semicondictor can be changed into by indirect band-gap semiconductor, its carrier mobility will obtain
Further enhance.Cmos device using direct band gap Ge as raceway groove, can not only improve its load
Transport factor and driving current are flowed, and it is completely compatible with current microelectronics prevailing technology, for height
Fast device provides another new technology evolutionary path with circuit.
However, the key issue faced at present is that the Ge materials for how preparing large strain are realized
The transformation of Ge material band gap types, and how to design, realize the direct of high carrier mobility
Band gap Ge cmos devices.
The content of the invention
Therefore, to solve technological deficiency and deficiency existing for prior art, the present invention proposes a kind of
Direct band gap Ge channel CMOS integrated devices and preparation method thereof.
Specifically, a kind of direct band gap Ge channel CMOSs that one embodiment of the invention proposes
The preparation method of integrated device, including：
S101, choose n-type doping monocrystalline silicon (001) substrate；
S102, it is in the single crystal Si substrate Epitaxial growth thickness at 275 DEG C~325 DEG C
The Ge layers of 50nm the first, to avoid crystal mass from losing；
S103, at 500 DEG C~600 DEG C, growth thickness is on the first Ge layers
900~950nm the 2nd Ge layers；
S104, at 750 DEG C~850 DEG C, in H2Annealed 10~15 minutes in atmosphere；
S105, in 75 DEG C of H2O2In solution, it is 10 minutes to immerse the time, described second
Ge layer surfaces form GeO2Passivation layer；
S106, utilize the Si that CVD technique illuviums thickness is 150~200nm3N4Layer；
S107, photoetching shallow trench isolation region, using dry etch process, in the Si3N4Layer,
The GeO2It is the shallow of 300~500nm that depth is etched in passivation layer, the 2nd Ge layers
Groove；
S108, using CVD techniques at 750 DEG C~850 DEG C, deposit SiO in the shallow slot2
Material, the groove is filled up；
S109, utilize the CMP removal Si3N4The SiO of layer surface2Material, and
Under the conditions of 180 DEG C the Si is etched using hot phosphoric acid wet processing3N4Layer；
S110, using ion implantation technology in the GeO2Passivation layer surface specific region is injected
B ions, p type island region domain is formed so as to form NMOS active areas；
S111, at 250 DEG C~300 DEG C, use atomic layer deposition processes deposition thickness as 2~3nm
HfO2Material is as gate dielectric layer；
S112, using CVD techniques, growth thickness is 110nm TaN at 750 DEG C~850 DEG C
Material is as grid layer；
S113, the TaN materials, described for etching using selective etch technique designated area
HfO2Material and the GeO2Passivation layer forms NMOS gate and PMOS grids；
S114, in the 2nd Ge layers and the NMOS gate and the PMOS grids table
Face deposition thickness is 10~20nm SiO2Material；
S115, using CVD techniques in the SiO2Material surface deposition thickness is 20~30nm
Si3N4Material；
S116, etched using selective etch technique and remove the NMOS gate and the PMOS
SiO beyond top portions of gates and side wall place2Material and Si3N4Material, in the NMOS grid
Pole surface and the PMOS gate surfaces form grid protection layer；
S117, in whole substrate surface photoresist is smeared, using photoetching process exposure photo-etching glue,
Retain the photoresist of the NMOS gate surface and the PMOS gate surfaces；
S118, utilize the sense coupling technique etching whole substrate surface
The 2nd Ge layers, form Ge steps；
S119, remove photomask surface glue；
S120, at 500 DEG C~600 DEG C, using silane, germane as source of the gas, using chemical gaseous phase
Depositing technics is in the Si that the Ge steps surrounding growth thickness is 20nm0.5Ge0.5Material；
S121, utilize the wet-etching technology removal SiO2Material and the Si3N4Material shape
Into the grid protection layer；
S122, in surface smear photoresist, carry out B ion implantings using self-registered technology and formed
PMOS source drains, and removes photoresist；
S123, in surface smear photoresist, carry out P ion using self-registered technology and inject to be formed
NMOS source-drain electrodes, remove photoresist；
S124, using the BPSG that CVD techniques deposition thickness is 20~30nm to form medium
Layer；
S125, using described in nitric acid and hf etching dielectric layer formed PMOS source miss contact hole
With NMOS source and drain contact holes；
S126, using electron beam evaporation process deposition thickness it is 10~20nm metal Ws, is formed
PMOS source drain contact and the contact of NMOS source and drain；
S127, the metal W for etching away using selective etch technique designated area, form source and drain
Region electrode, ultimately form the modified Ge raceway grooves nmos device.
A kind of direct band gap Ge channel CMOS integrators that another embodiment of the present invention proposes
Part, including：Si substrate layers, the first Ge layers, the 2nd Ge layers and Si0.5Ge0.5Layer, GeO2
Passivation layer, HfO2Gate dielectric layer, TaN grid layers；Wherein, the direct band gap Ge raceway grooves
CMOS integrated devices are prepared as the method described in above-described embodiment and formed.
A kind of direct band gap Ge channel CMOS integrators that another embodiment of the present invention proposes
The preparation method of part, including：
Choose Si substrates；
In the Ge layers of Si substrate surfaces growth regulation one；
In the Ge layers of the first Ge layer surfaces growth regulation two；
Shallow trench isolation is formed in the 2nd Ge layers；
In the 2nd Ge layer specifics region, injection B ions form NMOS active areas；
Gate dielectric layer and grid layer, selective etch are continuously grown in the 2nd Ge layer surfaces
Technique etches the gate dielectric layer and the grid layer forms PMOS grids and NMOS gate；
Grid protection layer is formed in the PMOS grids and the NMOS gate surface；
The 2nd Ge layers are etched to be formed in the PMOS grids and NMOS gate opening position
Ge steps；
Si is grown in the 2nd Ge layer surfaces using epitaxy technique0.5Ge0.5Layer；
Remove the grid protection layer, using ion implantation technology formed PMOS source drain electrode and
NMOS source-drain electrodes；
Contact is formed in PMOS source drain electrode and the NMOS source-drain electrodes surface deposition metal
Area, to ultimately form the direct band gap Ge channel CMOS integrated devices.
In one embodiment of invention, first temperature is less than the second temperature.
In one embodiment of invention, the scope of first temperature is 275 DEG C~325 DEG C；
The scope of the second temperature is 500 DEG C~600 DEG C.
In one embodiment of the invention, shallow trench isolation is formed in the 2nd Ge layers,
Including：
Si is deposited using CVD techniques3N4Layer；
Photoetching shallow trench isolation region, using dry etch process, in the Si3N4Layer, described the
Etching forms shallow slot in two Ge layers；
Using CVD techniques SiO is deposited in the shallow slot2Material, the groove is filled up；
The Si is removed using CMP3N4The SiO of layer surface2Material, and utilize hot phosphoric acid
Wet processing etches the Si3N4Layer.
In one embodiment of the invention, in the PMOS grids and the NMOS gate
Surface forms grid protection layer, including：
In the 2nd Ge layers, the PMOS grids and the NMOS gate surface deposition
SiO2Material；
Using CVD techniques in the SiO2Material surface deposits Si3N4Material；
The PMOS grids and the NMOS gate top are removed using selective etch technique etching
The SiO beyond portion and side wall place2Material and the Si3N4Material, in the PMOS
Grid and the NMOS gate surface form grid protection layer.
In one embodiment of the invention, the 2nd Ge layers are etched in the PMOS grid
Pole and NMOS gate opening position form Ge steps, including：
Photoresist is smeared in whole substrate surface, using photoetching process exposure photo-etching glue, retains institute
State PMOS grids and the photoresist on NMOS gate surface；
Using described in the sense coupling technique etching whole substrate surface
2nd Ge layers, form the Ge steps；
Remove photomask surface glue.
In one embodiment of the invention, Si is grown in the 2nd Ge layer surfaces0.5Ge0.5
Layer, including：
At 500 DEG C~600 DEG C, using silane, germane as source of the gas, using chemical vapor deposition work
Skill is in the Si that the Ge steps surrounding growth thickness is 20nm0.5Ge0.5Material.
A kind of direct band gap Ge channel CMOS integrators that another embodiment of the present invention proposes
Part, Si substrate layers, the first Ge layers, the 2nd Ge layers and Si0.5Ge0.5Layer, GeO2Passivation layer,
HfO2Gate dielectric layer, TaN grid layers；Wherein, the direct band gap Ge channel CMOS collection
Prepared and formed as the method described in above-described embodiment into device.
Above-described embodiment, the Ge modification modes realized based on existing process condition and direct band gap
Cmos device preparation methods of the Ge as raceway groove, effectively improve the load of cmos device
Flow transport factor.And direct band gap Ge materials are greatly improved due to its Carrier recombination efficiency,
Apply also for photonic device active layer.Therefore, direct band gap Ge proposed by the invention
CMOS also has the advantage of monolithic optoelectronic integration.Specific advantage is as follows：
1st, the process of cmos device of the present invention and existing Si ic process compatibilities,
There is fairly obvious advantage in terms of technique manufactures, reduces cost；
2nd, the present invention prepares Ge materials based on hypo-hyperthermia two-step growth method, and utilizes selection
Property epitaxy Si Ge introduce tensile stress, obtained direct band gap Ge crystalline quality of material is high；
3rd, CMOS of the present invention channel material is direct band gap Ge materials, relative to tradition
Ge material carrier mobilities have very big lifting, so as to improve the electric current of cmos device
Driving and frequency characteristic；
4th, the direct band gap Ge materials that the present invention realizes, its carrier mobility is high, can apply
In monolithic optoelectronic integration, the key performances such as circuit function, speed can be strengthened.
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become bright
It is aobvious.It is understood that the accompanying drawing is only the purpose design explained, not as this hair
The restriction of bright scope, because it should refer to appended claims.It should also be noted that
Unless otherwise noted, it is not necessary to which scale accompanying drawing, they only try hard to conceptually illustrate this
Locate the structure and flow of description.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.
Fig. 1 is a kind of direct band gap Ge channel CMOS integrators provided in an embodiment of the present invention
The process chart of part；
Fig. 2 is a kind of schematic top plan view of direct band gap Ge structures provided in an embodiment of the present invention；
Fig. 3 a- Fig. 3 z are a kind of direct band gap Ge channel CMOSs provided in an embodiment of the present invention
The process schematic representation of integrated device.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, tie below
Accompanying drawing is closed to be described in detail the embodiment of the present invention.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of direct band gap Ge raceway grooves provided in an embodiment of the present invention
The process chart of CMOS integrated devices.This method comprises the following steps：
Step a, Si substrates are chosen；
Step b, in the Ge layers of Si substrate surfaces growth regulation one；
Step c, in the Ge layers of the first Ge layer surfaces growth regulation two；
Step d, shallow trench isolation is formed in the 2nd Ge layers；
Step e, in the 2nd Ge layer specifics region, it is active to form NMOS for injection B ions
Area；
Step f, gate dielectric layer and grid layer are continuously grown in the 2nd Ge layer surfaces, selected
Selecting property etching technics etch the gate dielectric layer and the grid layer formed PMOS grids and
NMOS grid
Step g, gate protection is formed in the PMOS grids and the NMOS gate surface
Layer；
Step h, the 2nd Ge layers, the PMOS grids and the NMOS gate position are etched
The place of putting forms Ge steps；
Step i, Si is grown in the 2nd Ge layer surfaces using epitaxy technique0.5Ge0.5Layer；
Step j, the grid protection layer is removed, PMOS source is formed using ion implantation technology
Drain electrode and NMOS source-drain electrodes；
Step k, in PMOS source drain electrode and the NMOS source-drain electrodes surface deposition metal
Contact zone is formed, to ultimately form the direct band gap Ge channel CMOS integrated devices.
Wherein, in step b and step c, first temperature is less than the second temperature.Enter
One step, the scope of first temperature is 275 DEG C~325 DEG C；The scope of the second temperature
For 500 DEG C~600 DEG C.
Alternatively, step d can specifically include：
Step d1, Si is deposited using CVD techniques3N4Layer；
Step d2, photoetching shallow trench isolation region, using dry etch process, in the Si3N4Layer,
Etching forms shallow slot in the 2nd Ge layers；
Step d3, SiO is deposited in the shallow slot using CVD techniques2Material, by the ditch
Groove fills up；
Step d4, the Si is removed using CMP3N4The SiO of layer surface2Material, and
The Si is etched using hot phosphoric acid wet processing3N4Layer
Alternatively, step g is specifically included：
Step g1, in the 2nd Ge layers, the PMOS grids and the NMOS gate
Surface deposition SiO2Material；
Step g2, using CVD techniques in the SiO2Material surface deposits Si3N4Material；
Step e3, using selective etch technique etching except PMOS grids and described
The SiO at the top of NMOS gate and beyond side wall place2Material and the Si3N4Material,
Grid protection layer is formed in the PMOS grids and the NMOS gate surface.
Alternatively, step h, including：
Step h1, photoresist is smeared in whole substrate surface, utilizes photoetching process exposure photo-etching
Glue, retain the PMOS grids and the photoresist on NMOS gate surface；
Step h2, the sense coupling technique etching whole substrate table is utilized
The 2nd Ge layers in face, form the Ge steps；
Step h3, photomask surface glue is removed.
Wherein, can be for step, concrete technology：
At 500 DEG C~600 DEG C, using silane, germane as source of the gas, using chemical vapor deposition work
Skill is in the Si that the Ge steps surrounding growth thickness is 20nm0.5Ge0.5Material；Wherein, SiH4
Volume flow is 5mL/min, GeH4Volume flow is 2mL/min, growth time 1h.
The present invention operation principle be specially：
Modified Ge technologies be it is a kind of by introduced in monocrystalline Ge certain stress make its by
Tape splicing gap is changed into direct band-gap semicondictor material, further improves the skill of its carrier mobility
Art.Modified Ge materials, due to energy level splitting, effective mass reduction etc., its carrier mobility
Rate is further improved, and applied to microelectronic component and its integrated circuit, speed will be obviously improved；
Under certain condition, band gap conversion can even occur for modified Ge, be changed into from indirect bandgap material
Direct band gap material, its Carrier recombination efficiency greatly improve, applied to opto-electronic device, its
Luminous efficiency will be substantially improved；Meanwhile Ge material carrier mobilities in the case of direct band gap
Height, this is material modified to integrate applied to silicon-based monolithic photoelectricity, can strengthen circuit function, speed etc.
Key performance.At present, the Ge modification technologies of domestic and international primary study have following three types：①、
The regulation adulterated by low-intensity tensile stress and n-type, Ge material modifications are defined direct band gap
Material；2., apply high intensity tensile stress, Ge materials is changed into direct band gap material；
3., using the means (typical as GeSn alloy) of alloying, obtain direct band gap and be modified
Ge materials.Preferable stress incorporation way should have adjustable stress, process compatible, lattice
The advantages that zero defect, it is to prepare high performance strained Ge CMOS to select appropriate stress introducing method
The premise of device.
Based on these principles, Fig. 2 is referred to, Fig. 2 is provided in an embodiment of the present invention a kind of straight
The schematic top plan view of tape splicing gap Ge structures.The present invention passes through the selective epitaxial germanium around Ge
Silicon (SiGe) introduces tensile stress, obtains the direct band gap Ge materials of better quality.Specifically
Principle is due to that Ge lattice constant is bigger than sige material, the SiGe below source and drain areas
Material will be forced the lattice constant of adaptation Ge materials, therefore SiGe transverse directions lattice will be answered by opening
Power；And the sige material above source and drain areas has reached relaxation shape because thickness is thicker
State.Because total device length keeps constant, with the diminution of SiGe transverse direction lattices, in causing
The Ge materials in heart district domain will be by tensile stress.In addition, Ge materials are directly used as substrate
It is expensive, it is unfavorable for large-scale application.Current solution method is to prepare on a si substrate
Ge epitaxial layers, and the most common method of epitaxial Ge material is hypo-hyperthermia two-step growth method.
This method elder generation low-temperature epitaxy a thin layer Ge, suppress the island caused by big lattice mismatch and give birth to
It is long.High growth temperature main body Ge epitaxial layers again.Compared with traditional graded buffer layer growth method,
Graded layer thickness is this approach reduce, and Ge epi-layer surface roughness is significantly reduced.
To sum up, the Ge modification modes and direct band gap that the present invention is realized based on existing process condition
Cmos device preparation methods of the Ge as raceway groove, effectively improve the load of cmos device
Flow transport factor.And direct band gap Ge materials are greatly improved due to its Carrier recombination efficiency,
Apply also for photonic device active layer.Therefore, direct band gap Ge proposed by the invention
CMOS also has the advantage of monolithic optoelectronic integration.
Embodiment two
It is direct for one kind provided in an embodiment of the present invention to refer to Fig. 3 a- Fig. 3 z, Fig. 3 a- Fig. 3 z
The process schematic representation of band gap Ge channel CMOS integrated devices, on the basis of above-described embodiment,
Technological process in more detail to the present invention is introduced the present embodiment.This method includes：
S101, substrate are chosen：As shown in Figure 3 a, N-type silicon (Si) substrate slice 001 is chosen
For original material, and surface clean is carried out, to remove protective layer and impurity.
S102, two-step method growth epitaxial germanium layer：
S1021, the method using chemical vapor deposition (CVD), on substrate, with it is low,
Two method growing n-type Ge (001) films of high temperature, doping concentration are 1~5 × 1016cm-3；
S1022, as shown in Figure 3 b, thick " low of one layer of 50nm is grown at 275~325 DEG C
Temperature " Ge ((LT-Ge) films 002.The relaxation of most of elastic stress occurs to receive less than 10
The low temperature Ge layers of rice, but to avoid crystal mass loss from needing thickness larger (being more than 27 nanometers)
Low temperature Ge layers.Therefore LT-Ge layers are set as 50nm by the present invention.Low growth temperature is same
When inhibit three-dimensional Ge islands formation and dislocation formed relaxed stress；
S1023, as shown in Figure 3 c, under 500~600 DEG C of growth temperature, deposit 900-950nm
Ge layers 003；
S1024, it is to improve lattice quality, in H2750~850 DEG C of annealing are (at one in atmosphere
Fixed temperature or circulation) it is no more than 10-15 minutes.
S1025, in order to obtain good electrology characteristic at Ge raceway grooves and MOS oxide interfaces
With stability, it is necessary to form one layer of GeO on Ge surfaces2Passivation layer.Method is to place the substrate in
75 DEG C of H2O2In solution, it is 10 minutes to immerse the time, will be formed on Ge surfaces one layer very thin
GeO2Passivation layer 004, as shown in Figure 3 d.
S103, shallow-trench isolation technology：
Shown in S1031, Fig. 3 e, using CVD method, deposit a layer thickness is about 200nm
Si3N4005 stop-layer as chemically mechanical polishing；
Shown in S1032, Fig. 3 f, photoetching shallow trench isolation region, dry etch process, NMOS are utilized
The shallow slot that depth is 300~500nm is etched with PMOS device isolated area；Utilize CVD's
Method, at 750~850 DEG C, in crystal column surface deposit silica (SiO2) 006, fill up
Shallow slot；
Shown in S1033, Fig. 3 g, the oxide layer on surface is removed with the method for chemically mechanical polishing,
And remove Si with hot phosphoric acid wet etching under the conditions of 180 DEG C3N4。
S104, form p-well：
As illustrated in figure 3h, photoresist 007 is molded to stop ion implanting, then carries out boron ion
Injection, localized p-type region is formed, for manufacturing NMOS tube.
S105, form CMOS gate：
S1051, as shown in figure 3i, using atomic layer deposition (ALD) method, at 250~300 DEG C
Under, hafnium oxide (HfO thick 2~3nm of deposit2) layer 008；
S1052, as shown in Fig. 3 j, the method using chemical vapor deposition (CVD) exists
At 750~850 DEG C, tantalum nitride (TaN) 009 thick one layer of 110nm of surface deposition；
S1053, as shown in figure 3k, pass through photoetching using chlorine based plasma and etch other areas
The HfO in domain2Gate regions are formed with TaN.
S106, protection grid.Grid is carrying out source and drain etching and the growth of selective germanium and silicon epitaxial
During must be protected.
S1061, as shown in Fig. 3 l, gate surface deposit one layer of thin SiO2Layer 010 is thick
Degree is about 10nm；
S1062, as shown in figure 3m, is 20~30nm with chemical vapour deposition technique deposition thickness
Si3N4Layer 011 is used as sacrificial protective layer, and it is in source and drain areas etching and selectivity that it, which is acted on,
Protect grid without prejudice in germanium and silicon epitaxial growth course, do not influence source and drain ion implanting in addition
Self-registered technology；
S1063, as shown in figure 3n, etches the SiO in addition to grid2And SiN layer.
S107, selective epitaxial sige material.
S1071, photoetching, gluing and selection region exposure.As shown in Fig. 3 o, retain at center
The photoresist 012 in region, the photoresist of surrounding are etched away；
S1072, etching Ge materials.As shown in Fig. 3 p, in CF4And SF6In gaseous environment,
Etched using inductively coupled plasma (ICP) method.Central area is anti-etching due to photoresist
Property, the Ge materials at center are retained；The peripheral regions of etching grid；
S1073, at 500~600 DEG C, using silane, germane as source of the gas, using chemical gaseous phase
(CVD) technology of deposit is in Si thick one layer of 20nm of the Si Growns exposed0.5Ge0.5
Layer 013, wherein, SiH4Volume flow is 5mL/min, GeH4Volume flow is 2mL/min,
Growth time is 1h, and Fig. 3 q are its top view front views as shown in Fig. 3 r；
S1074, such as Fig. 3 s show, the Si of grid covering is removed using wet etching mode3N4With
SiO2。
S108, form CMOS source and drain areas：
S1081, ion implanting form PMOS source drain region.As shown in Fig. 3 t, in NMOS devices
Part designated area gluing 015, using self-registered technology, boron (B) is carried out to PMOS source-drain area
Injection, source-drain area is formed, afterwards rapid thermal annealing (RTA) under 250~300 DEG C of nitrogen environments
30s, form source-drain electrode；
S1082, ion implanting form NMOS source-drain areas.As shown in Fig. 3 u, in PMOS
Device designated area gluing 016, using self-registered technology, phosphorus is carried out to NMOS source-drain area
(P) inject, form source-drain area, afterwards rapid thermal annealing (RTA) under 250~300 DEG C of nitrogen environments
30s, form source-drain electrode.
S109, deposit CMOS electrodes：
S1091, dielectric layer deposited.As shown in Fig. 3 v, using chemical vapor deposition (CVD)
20~30nm BPSG is deposited, forms dielectric layer (PMD) 017, shifting can be captured by mixing BPSG
Dynamic ion, device performance is damaged to prevent them to be diffused into grid；
S1092, etching contact hole.As shown in Fig. 3 w, with nitric acid and hf etching BPSG
Form source and drain contact hole；
S1093, deposit metal.As shown in Fig. 3 x, 10~20nm is deposited using electron beam evaporation
Thick tungsten (W) 018, form source and drain contact；
S1094, etching metal.As shown in Fig. 3 y, carve selective eating away using etching technics and refer to
Determine the metal W in region, planarization process is carried out using chemically mechanical polishing (CMP)；
S1095, passivation.As shown in Fig. 3 z, deposited using chemical vapor deposition (CVD)
20~30nm silicon nitride 019, for passivation dielectric.
Embodiment three
Refer to Fig. 3 z, a kind of direct band gap Ge channel CMOSs provided in an embodiment of the present invention
Integrated device, including：Si substrate layers, the first Ge layers, the 2nd Ge layers and Si0.5Ge0.5Layer,
GeO2Passivation layer, HfO2Gate dielectric layer, TaN grid layers；Wherein, the direct band gap Ge
Channel CMOS integrated device is prepared as the method described in above-described embodiment and formed.
In summary, specific case used herein is to direct band gap Ge raceway grooves of the present invention
The principle and embodiment of CMOS integrated devices and preparation method thereof are set forth, and the above is real
The explanation for applying example is only intended to help the method and its core concept for understanding the present invention；It is meanwhile right
In those of ordinary skill in the art, according to the thought of the present invention, in embodiment and answer
With there will be changes in scope, in summary, this specification content should not be construed as to this
The limitation of invention, protection scope of the present invention should be defined by appended claim.
Claims (10)
1. a kind of preparation method of direct band gap Ge channel CMOS integrated devices, its feature exist
In, including：
S101, choose n-type doping single crystalline Si (001) substrate；
S102, it is in the single crystal Si substrate Epitaxial growth thickness at 275 DEG C~325 DEG C
The Ge layers of 50nm the first, to avoid crystal mass from losing；
S103, at 500 DEG C~600 DEG C, growth thickness is on the first Ge layers
900~950nm the 2nd Ge layers；
S104, at 750 DEG C~850 DEG C, in H2Annealed 10~15 minutes in atmosphere；
S105, in 75 DEG C of H2O2In solution, it is 10 minutes to immerse the time, described second
Ge layer surfaces form GeO2Passivation layer；
S106, utilize the Si that CVD technique illuviums thickness is 150~200nm3N4Layer；
S107, photoetching shallow trench isolation region, using dry etch process, in the Si3N4Layer,
The GeO2It is the shallow of 300~500nm that depth is etched in passivation layer, the 2nd Ge layers
Groove；
S108, using CVD techniques at 750 DEG C~850 DEG C, deposit SiO in the shallow slot2
Material, the groove is filled up；
S109, utilize the CMP removal Si3N4The SiO of layer surface2Material, and
Under the conditions of 180 DEG C the Si is etched using hot phosphoric acid wet processing3N4Layer；
S110, using ion implantation technology in the GeO2Passivation layer surface specific region is injected
B ions, p type island region domain is formed so as to form NMOS active areas；
S111, at 250 DEG C~300 DEG C, use atomic layer deposition processes deposition thickness as 2~3nm
HfO2Material is as gate dielectric layer；
S112, using CVD techniques, growth thickness is 110nm TaN at 750 DEG C~850 DEG C
Material is as grid layer；
S113, the TaN materials, described for etching using selective etch technique designated area
HfO2Material and the GeO2Passivation layer forms NMOS gate and PMOS grids；
S114, in the 2nd Ge layers and the NMOS gate and the PMOS grids table
Face deposition thickness is 10~20nm SiO2Material；
S115, using CVD techniques in the SiO2Material surface deposition thickness is 20~30nm
Si3N4Material；
S116, etched using selective etch technique and remove the NMOS gate and the PMOS
SiO beyond top portions of gates and side wall place2Material and Si3N4Material, in the NMOS grid
Pole surface and the PMOS gate surfaces form grid protection layer；
S117, in whole substrate surface photoresist is smeared, using photoetching process exposure photo-etching glue,
Retain the photoresist of the NMOS gate surface and the PMOS gate surfaces；
S118, utilize the sense coupling technique etching whole substrate surface
The 2nd Ge layers, form Ge steps；
S119, remove photomask surface glue；
S120, at 500 DEG C~600 DEG C, using silane, germane as source of the gas, using chemical gaseous phase
Depositing technics is in the Si that the Ge steps surrounding growth thickness is 20nm0.5Ge0.5Material；
S121, utilize the wet-etching technology removal SiO2Material and the Si3N4Material shape
Into the grid protection layer；
S122, in surface smear photoresist, carry out B ion implantings using self-registered technology and formed
PMOS source drains, and removes photoresist；
S123, in surface smear photoresist, carry out P ion using self-registered technology and inject to be formed
NMOS source-drain electrodes, remove photoresist；
S124, using the BPSG that CVD techniques deposition thickness is 20~30nm to form medium
Layer；
S125, using described in nitric acid and hf etching dielectric layer formed PMOS source miss contact hole
With NMOS source and drain contact holes；
S126, using electron beam evaporation process deposition thickness it is 10~20nm metal Ws, is formed
PMOS source drain contact and the contact of NMOS source and drain；
S127, the metal W for etching away using selective etch technique designated area, form source and drain
Region electrode, ultimately form the modified Ge raceway grooves nmos device.
A kind of 2. direct band gap Ge channel CMOS integrated devices, it is characterised in that including：
Si substrate layers, the first Ge layers, the 2nd Ge layers and Si0.5Ge0.5Layer, GeO2Passivation layer, HfO2
Gate dielectric layer, TaN grid layers；Wherein, the direct band gap Ge channel CMOS integrators
Part is prepared as the method described in claim 1 and formed.
3. a kind of preparation method of direct band gap Ge channel CMOS integrated devices, its feature exist
In, including：
Choose Si substrates；
At the first temperature, in the Ge layers of Si substrate surfaces growth regulation one；
At the second temperature, in the Ge layers of the first Ge layer surfaces growth regulation two；
Shallow trench isolation is formed in the 2nd Ge layers；
In the 2nd Ge layer specifics region, injection B ions form NMOS active areas；
Gate dielectric layer and grid layer, selective etch are continuously grown in the 2nd Ge layer surfaces
Technique etches the gate dielectric layer and the grid layer forms PMOS grids and NMOS gate；
Grid protection layer is formed in the PMOS grids and the NMOS gate surface；
The 2nd Ge layers are etched to be formed in the PMOS grids and NMOS gate opening position
Ge steps；
Si is grown in the 2nd Ge layer surfaces using epitaxy technique0.5Ge0.5Layer；
Remove the grid protection layer, using ion implantation technology formed PMOS source drain electrode and
NMOS source-drain electrodes；
Contact is formed in PMOS source drain electrode and the NMOS source-drain electrodes surface deposition metal
Area, to ultimately form the direct band gap Ge channel CMOS integrated devices.
4. method as claimed in claim 3, it is characterised in that first temperature is less than institute
State second temperature.
5. method as claimed in claim 4, it is characterised in that the scope of first temperature
For 275 DEG C~325 DEG C；The scope of the second temperature is 500 DEG C~600 DEG C.
6. method as claimed in claim 3, it is characterised in that in the 2nd Ge layers
Shallow trench isolation is formed, including：
Si is deposited using CVD techniques3N4Layer；
Photoetching shallow trench isolation region, using dry etch process, in the Si3N4Layer, described the
Etching forms shallow slot in two Ge layers；
Using CVD techniques SiO is deposited in the shallow slot2Material, the groove is filled up；
The Si is removed using CMP3N4The SiO of layer surface2Material, and utilize hot phosphoric acid
Wet processing etches the Si3N4Layer.
7. method as claimed in claim 3, it is characterised in that in the PMOS grids and
The NMOS gate surface forms grid protection layer, including：
In the 2nd Ge layers, the PMOS grids and the NMOS gate surface deposition
SiO2Material；
Using CVD techniques in the SiO2Material surface deposits Si3N4Material；
The PMOS grids and the NMOS gate top are removed using selective etch technique etching
Portion and side wall sentence the outer SiO2Material and the Si3N4Material, in the PMOS grid
Pole and the NMOS gate surface form grid protection layer.
8. method as claimed in claim 3, it is characterised in that etching the 2nd Ge layers
Ge steps are formed in the PMOS grids and NMOS gate opening position, including：
Photoresist is smeared in whole substrate surface, using photoetching process exposure photo-etching glue, retains institute
State PMOS grids and the photoresist on NMOS gate surface；
Using described in the sense coupling technique etching whole substrate surface
2nd Ge layers, form the Ge steps；
Remove photomask surface glue.
9. method as claimed in claim 3, it is characterised in that in the 2nd Ge layer tables
Look unfamiliar long Si0.5Ge0.5Layer, including：
At 500 DEG C~600 DEG C, using silane, germane as source of the gas, using chemical vapor deposition work
Skill is in the Si that the Ge steps surrounding growth thickness is 20nm0.5Ge0.5Material.
A kind of 10. direct band gap Ge channel CMOS integrated devices, it is characterised in that including：
Si substrate layers, the first Ge layers, the 2nd Ge layers and Si0.5Ge0.5Layer, GeO2Passivation layer, HfO2
Gate dielectric layer, TaN grid layers；Wherein, the direct band gap Ge channel CMOS integrators
Part is prepared as the method described in any one of claim 3~9 and formed.
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| KR20050121479A (en) * | 2004-06-22 | 2005-12-27 | 삼성전자주식회사 | Fabricating method of cmos transistor and cmos transistor fabricated by the same method |
| CN101962802A (en) * | 2010-07-14 | 2011-02-02 | 中国科学院半导体研究所 | Method for growing GeSn alloy on Si substrate by molecular beam epitaxy |
| CN102184954A (en) * | 2011-03-10 | 2011-09-14 | 清华大学 | Ge channel device and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20050121479A (en) * | 2004-06-22 | 2005-12-27 | 삼성전자주식회사 | Fabricating method of cmos transistor and cmos transistor fabricated by the same method |
| CN101962802A (en) * | 2010-07-14 | 2011-02-02 | 中国科学院半导体研究所 | Method for growing GeSn alloy on Si substrate by molecular beam epitaxy |
| CN102184954A (en) * | 2011-03-10 | 2011-09-14 | 清华大学 | Ge channel device and forming method thereof |
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