CN102738177A - Strain Si BiCMOS (Bipolar-Complementary Metal-Oxide-Semiconductor) integrated device based on SOI (Silicon on Insulator) substrate and preparation method thereof - Google Patents

Strain Si BiCMOS (Bipolar-Complementary Metal-Oxide-Semiconductor) integrated device based on SOI (Silicon on Insulator) substrate and preparation method thereof Download PDF

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CN102738177A
CN102738177A CN2012102443749A CN201210244374A CN102738177A CN 102738177 A CN102738177 A CN 102738177A CN 2012102443749 A CN2012102443749 A CN 2012102443749A CN 201210244374 A CN201210244374 A CN 201210244374A CN 102738177 A CN102738177 A CN 102738177A
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CN102738177B (en
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胡辉勇
宣荣喜
张鹤鸣
宋建军
王斌
舒斌
戴显英
郝跃
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Xidian University
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Abstract

The invention discloses a strain Si BiCMOS (Bipolar-Complementary Metal-Oxide-Semiconductor) integrated device based on an SOI (Silicon on Insulator) substrate and a preparation method thereof. The preparation method comprises the following steps: growing N-type Si epitaxy on the SOI substrate, preparing trench isolation, and manufacturing a conventional Si bipolar transistor in a bipolar device region; respectively photoetching the ditch grooves of the active regions of an NMOS (Negative-channel Metal Oxide Semiconductor) and a PMOS (Positive-channel Metal Oxide Semiconductor) devices, continuously growing an Si buffer layer, a gradually varied SiGe layer, a fixed component SiGe layer and an N-type strain Si channel layer in the ditch groove of the active region of the NMOS device and continuously growing an Si buffer layer, a gradually varied SiGe layer, a fixed component SiGe layer, a strain Si P-LDD layer, a strain Si channel layer, a strain Si P-LDD layer and a fixed component SiGe layer in the ditch groove of the active region of the PMOS device, and preparing a drain and a grid on the active region of the PMOS device to form the PMOS device; preparing a gate dielectric layer and a gate polycrystal in the active region of the NMOS device to form the NMOS device; and photoetching leads to form an Si BICMOS integrated circuit in which an MOS (Metal Oxide Semiconductor) conducting channel is 22-45nm. According to the invention, based on the full use of the characteristic that tension strain Si material has mobility anisotropism, the strain Si BiCMOS integrated device with strengthened performance based on SOI substrate and the circuit thereof are prepared at the temperature of 600-800 DEG C.

Description

A kind of strain Si BiCMOS integrated device and preparation method based on the SOI substrate
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of strain Si BiCMOS integrated device and preparation method based on the SOI substrate.
Background technology
The integrated circuit that occurred in 1958 is one of invention of tool influence of 20th century; The microelectronics that is born based on this invention has become the basis of existing modern technologies, quickens changing more educated, the IT application process of human society, has also changed the human mode of thinking simultaneously; It not only is the human instrument that strong nature remodeling is provided, but also has opened up a wide development space.
Semiconductor integrated circuit has become the basis of electronics industry, and people impel the development in this field very rapid to the great demand of electronics industry; In decades in the past, the fast development of electronics industry has produced tremendous influence to social development and national economy; At present, electronics industry has become worldwide largest industry, and in occupation of very big share, the output value has surpassed 10,000 hundred million dollars in the world market.
Silicon materials are used as semi-conducting material and have been experienced more than 50 year; Traditional Si CMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly advance according to Moore's Law; At present, in the semi-conductor market in the whole world 90%, all be that the Si basis set becomes circuit.
But along with device feature size reduces, the enhancing of integrated level and complexity, a series of new problems that relate to aspects such as material, device physics, device architecture and technology have appearred; Particularly when IC chip features size entering nanoscale; See from device angles; Problems such as the influence of the short channel effect in the nanoscale devices, high-field effect, quantum effect, parasitic parameter, technological parameter fluctuation are more and more outstanding to Effect on Performance such as device leakage electric current, subthreshold characteristic, ON state, off-state currents; The contradiction of circuit speed and power consumption will be more serious also, on the other hand, and along with the develop rapidly of wireless mobile communications; Performance to device and circuit; Have higher requirement like frequency characteristic, noise characteristic, package area, power consumption and cost etc., the device of traditional silica-based prepared and integrated circuit are especially simulated and composite signal integrated circuits, more and more can't satisfy demand novel, the high-velocity electrons system.
In order to improve the performance of device and integrated circuit, the researcher by novel semi-conducting material like GaAs, InP etc., obtaining to be suitable for the high speed device and the integrated circuit of wireless mobile communications development; Although GaAs and InP based compound device frequency excellent, its preparation technology is higher than Si complex process, cost, and the major diameter single crystal preparation is difficult, mechanical strength is low, and heat dispersion is bad, resembles SiO with Si difficult technique compatibility and shortage 2Such effects limit such as passivation layer its extensive use and development.
Therefore; Industrial quarters is when manufacturing large scale integrated circuit especially hybrid digital-analog integrated circuit at present; Still adopt Si BiCMOS or SiGe BiCMOS technology (Si BiCMOS is Si bipolar transistor BJT+Si CMOS, and SiGe BiCMOS is SiGe heterojunction bipolar transistor HBT+Si CMOS).
Because Si material carrier material transition rate is lower, so the performance of integrated circuits, the especially frequency performance that adopt Si BiCMOS technology to make have received great restriction; And for SiGe BiCMOS technology, though bipolar transistor has adopted SiGe HBT, the unipolar device that promotes for restriction BiCMOS integrated circuit frequency characteristic still adopts Si CMOS, further promotes so these all limit BiCMOS performance of integrated circuits ground.
Summary of the invention
The object of the present invention is to provide strain Si BiCMOS integrated device and the preparation method of a kind of preparation based on the SOI substrate; To be implemented under the condition that does not change existing equipment and increase cost, preparing conducting channel is the strain Si BiCMOS integrated circuit of 22～45nm.
The object of the present invention is to provide a kind of strain Si BiCMOS device based on the SOI substrate, said pair of strain plane BiCMOS device adopts common Si bipolar transistor, strain Si planar channeling nmos device and strain Si vertical-channel PMOS device.
Further, the nmos device conducting channel is strain Si material, is tensile strain along channel direction.
Further, described strain Si BiCMOS device based on the SOI substrate, PMOS device strained Si channel is a vertical-channel in the cmos device, is compressive strain along channel direction, and is back the type structure.
Further, bipolar device adopts body Si material preparation on same SOI substrate.
Further, PMOS device conducting channel is strain Si material, is compressive strain along channel direction.
Another object of the present invention is to provide a kind of preparation method of the strain Si BiCMOS integrated device based on the SOI substrate, this preparation method comprises the steps:
The first step, to choose oxidated layer thickness be 150 ~ 300nm, and upper strata Si thickness is 100～120nm, and N type doping content is 1 * 10 16～1 * 10 17Cm -3The SOI substrate slice;
Second the step, epitaxial growth one deck doping content is 1 * 10 on the SOI substrate 16～1 * 10 17Cm -3The Si layer, thickness is 2～3 μ m, as collector region;
The 3rd step, be the SiO of 300～500nm at substrate surface thermal oxidation one layer thickness 2Layer, the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 ~ 5 μ m in the deep trench isolation zone; Utilize the method for chemical vapor deposition (CVD),, in deep trouth, fill SiO at 600～800 ℃ 2, with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
The 4th step, photoetching collector region contact zone carry out the injection of N type impurity to collector region, and at 800～950 ℃, annealing 30～90min activator impurity, forming doping content is 1 * 10 19～1 * 10 20Cm -3The heavy doping collector electrode;
The 5th the step, at substrate surface thermal oxidation one SiO 2Layer, the photoetching base carries out the injection of p type impurity to the base, and at 800～950 ℃, annealing 30～90min activator impurity, forming doping content is 1 * 10 18～5 * 10 18Cm -3The base;
The 6th the step, at substrate surface thermal oxidation one SiO 2Layer, the injection of N type impurity is carried out to substrate in the photoetching emitter region, and at 800～950 ℃, annealing 30～90min activator impurity, forming doping content is 5 * 10 19～5 * 10 20Cm -3The heavy doping emitter region, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer;
The 7th step, photoetching PMOS device active region are used dry etch process, at the PMOS device active region, etch the deep trouth that the degree of depth is 2～3 μ m; Utilize chemical vapor deposition (CVD) method, at 600～750 ℃, at PMOS device active region (being deep trouth) selective epitaxial growth seven layer materials: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.4～1.7 μ m, and bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 18Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the drain region of PMOS device; The 4th layer is that thickness is the P type strain Si layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD); Layer 5 is that thickness is the N type strain Si layer of 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, as the raceway groove of PMOS device; Layer 6 is that thickness is the P type strain Si layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD); Layer 7 is that the Ge component is 15～25%, and thickness is the P type SiGe of 200～400nm, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the active area of PMOS device;
The 8th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, at substrate surface deposit one deck SiO 2Photoetching nmos device active area at the nmos device active area, etches the deep trouth that the degree of depth is 1.9～2.8 μ m; Utilize chemical vapor deposition (CVD) method, at 600～750 ℃, at nmos device active area selective epitaxial growth four layer materials: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.5～2 μ m, and bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 5 * 10 16～5 * 10 17Cm -3The 4th layer is that thickness is the P type strain Si layer of 10～15nm, and doping content is 5 * 10 16～5 * 10 17Cm -3Raceway groove as nmos device;
The 9th step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching PMOS device source is leaked isolated area, utilizes dry etch process, etches the shallow slot that the degree of depth is 0.3～0.5 μ m in this zone; Utilize chemical vapor deposition (CVD) method again,, in shallow slot, fill SiO at 600～800 ℃ 2, form shallow-trench isolation;
Trench openings is leaked in the tenth step, photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is that 0.4～0.7 μ m leaks groove; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 1～5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad;
The 11 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching gate groove window utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4～0.7 μ m gate groove; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as the gate dielectric layer of PMOS device; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, the deposit doping content is 1～5 * 10 in gate groove 20Cm -3P type Poly-SiGe, the Ge component is 10～30%, and PMOS device gate groove is filled up; Photoetching gate medium and grid Poly-SiGe form grid and source electrode, finally form the PMOS device architecture;
The 12 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching nmos device active area utilizes atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at nmos device active area deposition thickness 2Layer is as the gate dielectric layer of nmos device; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is the P type Poly-SiGe of 200～300nm at nmos device active area deposition thickness, and doping content is 1～5 * 10 20Cm -3, the Ge component is 10～30%, photoetching gate medium and grid Poly-SiGe form grid; Utilize ion implantation technology, the nmos device active area is carried out N type ion inject, form N type lightly-doped source drain structure (N-LDD), doping content is 1～5 * 10 18Cm -3
The 13 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 3～5nm at entire substrate deposit one thickness 2Layer utilizes dry etch process, etches away the SiO on surface 2, form the nmos device grid curb wall, utilize ion implantation technology, the nmos device active area to be carried out N type ion inject, autoregistration generates the source region and the drain region of nmos device, and rapid thermal annealing, makes the doping content in nmos device source region and drain region reach 1～5 * 10 20Cm -3
The 14 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching lead-in wire window, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the CMOS Metal Contact; The photoetching lead-in wire forms drain electrode, source electrode and gate metal lead-in wire, and constituting the MOS conducting channel is the strain Si BiCMOS integrated device based on the SOI substrate of 22～45nm.
Further, wherein, the PMOS device channel length confirms that according to the N type strain Si layer thickness of the 8th step deposit get 22～45nm, the channel length of nmos device is determined by technology, gets 22～45nm.
Chemical vapor deposition (CVD) technological temperature during further, related maximum temperature went on foot to the 15 according to the 7th step in the strain Si cmos device manufacture process among this preparation method determines that maximum temperature is smaller or equal to 800 ℃.
Another object of the present invention is to provide a kind of preparation method of the strain Si BiCMOS integrated circuit based on the SOI substrate, this preparation method comprises the steps:
Step 1, epitaxially grown implementation method is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 150nm, upper layer of material is that doping content is 1 * 10 16Cm -3N type Si, thickness is 100nm;
Be the SiO of 300nm (1b) at substrate surface thermal oxidation one layer thickness 2Layer;
Step 2, the implementation method of isolated area preparation is:
(2a) epitaxial growth one deck doping content is 1 * 10 on the SOI substrate 16Cm -3The Si layer, thickness is 2 μ m, as collector region;
Be the SiO of 300nm (2b) at substrate surface thermal oxidation one layer thickness 2Layer;
(2c) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
Step 3, the implementation method of bipolar device preparation is:
(3a) photoetching collector region contact zone carries out the injection of N type impurity to collector region, and at 800 ℃, annealing 90min activator impurity, forming doping content is 1 * 10 19Cm -3The heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2Layer, the photoetching base carries out the injection of p type impurity to the base, and at 800 ℃, annealing 90min activator impurity, forming doping content is 1 * 10 18Cm -3The base;
(3c) at substrate surface thermal oxidation one SiO 2Layer, the injection of N type impurity is carried out to substrate in the photoetching emitter region, and at 800 ℃, annealing 90min activator impurity, becoming doping content is 5 * 10 19Cm -3The heavy doping emitter region, constitute bipolar transistor;
(3d) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
Step 4, the implementation method of PMOS device active region epitaxial material preparation is:
(4a) photoetching PMOS device active region is used dry etching method, at the PMOS device active region, etches the deep trouth that the degree of depth is 2 μ m;
(4b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type Si resilient coating of 200nm in deep trouth, doping content 1 * 10 15Cm -3
(4c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type SiGe layer of 1.4 μ m on the Si resilient coating, and Ge component bottom is 0%, and the upper strata is 25% Gradient distribution, and doping content is 1 * 10 18Cm -3
(4d) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one deck Ge component is 25% on the SiGe layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 * 10 19Cm -3, as the drain region of PMOS device;
(4e) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type strain Si layer of 3nm on P type SiGe layer, and doping content is 1 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the N type strain Si layer of 22nm on P type strain Si layer, and as the PMOS device channel region, doping content is 5 * 10 16Cm -3
(4g) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type strain Si layer of 3nm on N type strain Si layer, and doping content is 1 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4h) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is that the Ge component of 200nm is fixed as 25% P type strain SiGe layer on strain Si layer, and as PMOS device source region, doping content is 5 * 10 19Cm -3, form the PMOS device active region;
Step 5, the implementation method of nmos device active area materials preparation is:
(5a) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO 2
(5b) photoetching nmos device active area is used dry etching method, at the nmos device active area, etches the deep trouth that the degree of depth is 1.9 μ m;
(5c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm at nmos device active area selective growth one layer thickness, doping content 1 * 10 15Cm -3
(5d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type SiGe layer of 1.5 μ m on the Si resilient coating, and the Ge composition gradient distributes, and the bottom is 0%, and the top is 25%, and doping content is 1 * 10 15Cm -3
(5e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one deck Ge component is 25% on the SiGe layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 * 10 16Cm -3
(5f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type strain Si layer of 10nm on the SiGe layer, the nmos device channel region, and doping content is 5 * 10 16Cm -3, form the nmos device active area;
Step 6, the PMOS device isolation with the implementation method of leaking the groove preparation is:
(6a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(6b) photoetching PMOS device source is leaked isolated area, utilizes dry etch process, leaks isolated area in the PMOS device source and etches the shallow slot that the degree of depth is 0.3 μ m;
(6c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, shallow-trench isolation is leaked in the formation source;
(6d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is that 0.4 μ m leaks groove;
(6e) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad;
Step 7, the implementation method that the PMOS device forms is:
(7a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(7b) photoetching gate groove window utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4 μ m gate groove;
(7c) utilize atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, at the HfO of substrate surface depositing high dielectric constant 2Layer, as the gate dielectric layer of PMOS device, thickness is 6nm;
(7d) utilize chemical vapor deposition (CVD) method, at 600 ℃, the deposit doping content is 1 * 10 in gate groove 20Cm -3P type Poly-SiGe, the Ge component is 30%, and PMOS device gate groove is filled up;
(7e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS device grids and source electrode, finally form the PMOS device;
Step 8, the implementation method that nmos device forms is:
(8a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(8b) photoetching nmos device active area utilizes atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 6nm at nmos device surfaces of active regions deposit one layer thickness 2Layer is as the gate medium of nmos device;
(8c) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one deck Ploy-SiGe layer on gate dielectric layer, the Ge component is 30%, and thickness is 200nm, and doping content is 1 * 10 20Cm -3
(8d) photoetching gate medium and grid Poly-SiGe form grid;
(8e) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, form N type lightly-doped source drain structure (N-LDD), doping content is 1 * 10 18Cm -3
(8f) utilize chemical vapor deposition (CVD) method, at 600 ℃, at the SiO of nmos device surfaces of active regions deposit one deck 3nm 2Layer utilizes dry etch process, etches away the SiO on surface 2Layer retains SiO at the Ploy-SiGe sidewall 2Form the grid side wall;
(8g) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, autoregistration generates the source region and the drain region of nmos device, and rapid thermal annealing, makes the doping content of nmos device active area reach 1 * 10 20Cm -3, finally form nmos device;
Step 9, the implementation method that constitutes the BiCMOS integrated circuit is:
(9a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(9b) lithography fair lead;
(9c) at substrate surface sputter layer of metal titanium (Ti), alloy;
(9d) photoetching lead-in wire; Form PMOS device drain metal lead wire, source metal lead-in wire; The gate metal lead-in wire; Nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 22nm.
The present invention has following advantage:
1. in the BiCMOS device architecture that the present invention makes; CMOS has partly adopted strain Si material manufacture conducting channel; Because strain Si material carrier mobility is far above body Si material, simulation and the hybrid digital-analog integrated circuit performance therefore made with this BiCMOS device architecture are excellent with the circuit performance that body Si makes;
2. the CMOS structure in the BiCMOS device architecture made of the present invention has made full use of the anisotropy of strain Si material stress, introduces tensile strain in the horizontal direction, has improved the nmos device electron mobility; Introduce compressive strain in vertical direction, improved the PMOS hole mobility; Therefore, performances such as this device frequency and current driving ability are higher than unidimensional relaxation Si cmos device;
3. in the preparation process of the present invention, strain Si layer is with the deposit of chemical vapor deposition (CVD) method, accurately control growing thickness; And the channel length of the PMOS among the CMOS is the thickness of Si layer; Thereby avoided the small size photoetching, reduced process complexity, reduced cost;
4. the raceway groove of PMOS is back type in the BiCMOS device architecture of the present invention's preparation; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. the MOS device in the BiCMOS device of the present invention's preparation has adopted the HfO of high K value 2As gate medium, improved the grid-control ability of MOS device, strengthened the electric property of cmos device;
6. the CMOS structure in the BiCMOS device of the present invention's preparation adopts the Poly-SiGe material as gate electrode, and its work function changes with the variation of Ge component; Through regulating Ge component among the Poly-SiGe; Realization CMOS threshold voltage can be adjusted continuously, has reduced processing step, has reduced technology difficulty;
7. to prepare strain Si vertical-channel cmos device be after the bipolar device manufacturing is accomplished in the present invention; And the maximum temperature that relates in its technical process is 800 ℃; Be lower than the technological temperature that causes strained Si channel stress relaxation; Therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;
8. the BiCMOS device architecture of the present invention's preparation has adopted the SOI substrate, has improved the reliability of device and circuit.
Description of drawings
Fig. 1 is strain Si BiCMOS integrated device preparation method's provided by the invention realization flow figure.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of strain Si BiCMOS device based on the SOI substrate, and said pair of strain plane BiCMOS device adopts common Si bipolar transistor, strain Si planar channeling nmos device and strain Si vertical-channel PMOS device.
As a prioritization scheme of the embodiment of the invention, the nmos device conducting channel is a strain Si material, is tensile strain along channel direction.
As a prioritization scheme of the embodiment of the invention, PMOS device strained Si channel is a vertical-channel in the cmos device, is compressive strain along channel direction, and is back the type structure.
As a prioritization scheme of the embodiment of the invention, bipolar device adopts body Si material preparation on same SOI substrate.
As a prioritization scheme of the embodiment of the invention, PMOS device conducting channel is a strain Si material, is compressive strain along channel direction.
Following with reference to accompanying drawing 1, the technological process of strain Si BiCMOS integrated device of the present invention and circuit preparation is described in further detail.
Embodiment 1: the preparation channel length is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 22nm, and concrete steps are following:
Step 1, epitaxial growth.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 150nm, upper layer of material is that doping content is 1 * 10 16Cm -3N type Si, thickness is 100nm;
Be the SiO of 300nm (1b) at substrate surface thermal oxidation one layer thickness 2Layer.
Step 2, the isolated area preparation.
(2a) epitaxial growth one deck doping content is 1 * 10 on the SOI substrate 16Cm -3The Si layer, thickness is 2 μ m, as collector region;
Be the SiO of 300nm (2b) at substrate surface thermal oxidation one layer thickness 2Layer;
(2c) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 3, the bipolar device preparation.
(3a) photoetching collector region contact zone carries out the injection of N type impurity to collector region, and at 800 ℃, annealing 90min activator impurity, forming doping content is 1 * 10 19Cm -3The heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2Layer, the photoetching base carries out the injection of p type impurity to the base, and at 800 ℃, annealing 90min activator impurity, forming doping content is 1 * 10 18Cm -3The base;
(3c) at substrate surface thermal oxidation one SiO 2Layer, the injection of N type impurity is carried out to substrate in the photoetching emitter region, and at 800 ℃, annealing 90min activator impurity, becoming doping content is 5 * 10 19Cm -3The heavy doping emitter region, constitute bipolar transistor;
(3d) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer.
Step 4, the preparation of PMOS active area epitaxial material.
(4a) photoetching PMOS active area is used dry etching method, at the PMOS active area, etches the deep trouth that the degree of depth is 2 μ m;
(4b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type Si resilient coating of 200nm in deep trouth, doping content 1 * 10 15Cm -3
(4c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type SiGe layer of 1.4 μ m on the Si resilient coating, and Ge component bottom is 0%, and the upper strata is 25% Gradient distribution, and doping content is 1 * 10 18Cm -3
(4d) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one deck Ge component is 25% on the SiGe layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 * 10 19Cm -3, as the drain region of PMOS;
(4e) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type strain Si layer of 3nm on P type SiGe layer, and doping content is 1 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the N type strain Si layer of 22nm on P type strain Si layer, and as the PMOS channel region, doping content is 5 * 10 16Cm -3
(4g) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type strain Si layer of 3nm on N type strain Si layer, and doping content is 1 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4h) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is that the Ge component of 200nm is fixed as 25% P type strain SiGe layer on strain Si layer, and as the PMOS source region, doping content is 5 * 10 19Cm -3, form the PMOS active area.
Step 5, the preparation of nmos device active area materials.
(5a) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO 2
(5b) photoetching nmos device active area is used dry etching method, at the nmos device active area, etches the deep trouth that the degree of depth is 1.9 μ m;
(5c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm at nmos device active area selective growth one layer thickness, doping content 1 * 10 15Cm -3
(5d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type SiGe layer of 1.5 μ m on the Si resilient coating, and the Ge composition gradient distributes, and the bottom is 0%, and the top is 25%, and doping content is 1 * 10 15Cm -3
(5e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one deck Ge component is 25% on the SiGe layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 * 10 16Cm -3
(5f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type strain Si layer of 10nm on the SiGe layer, the nmos device channel region, and doping content is 5 * 10 16Cm -3, form the nmos device active area.
Step 6, PMOS isolates and leaks groove and prepares.
(6a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(6b) isolated area is leaked in photoetching PMOS source, utilizes dry etch process, leaks isolated area in the PMOS source and etches the shallow slot that the degree of depth is 0.3 μ m;
(6c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, shallow-trench isolation is leaked in the formation source;
(6d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at the PMOS drain region is that 0.4 μ m leaks groove;
(6e) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, PMOS is leaked groove fills up, get rid of PMOS again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad.
Step 7, PMOS forms.
(7a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(7b) photoetching gate groove window utilizes dry etch process, and etching the degree of depth in the PMOS gate region is 0.4 μ m gate groove;
(7c) utilize atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, at the HfO of substrate surface depositing high dielectric constant 2Layer, as the gate dielectric layer of PMOS, thickness is 6nm;
(7d) utilize chemical vapor deposition (CVD) method, at 600 ℃, the deposit doping content is 1 * 10 in gate groove 20Cm -3P type Poly-SiGe, the Ge component is 30%, and the PMOS gate groove is filled up;
(7e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS grid and source electrode, finally form the PMOS device.
Step 8, nmos device forms.
(8a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(8b) photoetching nmos device active area utilizes atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 6nm at nmos device surfaces of active regions deposit one layer thickness 2Layer is as the gate medium of nmos device;
(8c) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one deck Ploy-SiGe layer on gate dielectric layer, the Ge component is 30%, and thickness is 200nm, and doping content is 1 * 10 20Cm -3
(8d) photoetching gate medium and grid Poly-SiGe form grid;
(8e) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, form N type lightly-doped source drain structure (N-LDD), doping content is 1 * 10 18Cm -3
(8f) utilize chemical vapor deposition (CVD) method, at 600 ℃, at the SiO of nmos device surfaces of active regions deposit one deck 3nm 2Layer utilizes dry etch process, etches away the SiO on surface 2Layer retains SiO at the Ploy-SiGe sidewall 2Form the grid side wall;
(8g) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, autoregistration generates the source region and the drain region of nmos device, and rapid thermal annealing, makes the doping content of nmos device active area reach 1 * 10 20Cm -3, finally form nmos device.
Step 9 constitutes the BiCMOS integrated circuit.
(9a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(9b) lithography fair lead;
(9c) at substrate surface sputter layer of metal titanium (Ti), alloy;
(9d) photoetching lead-in wire; Form PMOS drain metal lead-in wire, source metal lead-in wire; The gate metal lead-in wire; Nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 22nm.
Embodiment 2: the preparation channel length is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 30nm, and concrete steps are following:
Step 1, epitaxial growth.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 220nm, upper layer of material is that doping content is 5 * 10 16Cm -3N type Si, thickness is 110nm;
Be the SiO of 400nm (1b) at substrate surface thermal oxidation one layer thickness 2Layer.
Step 2, the isolated area preparation.
(2a) epitaxial growth one deck doping content is 5 * 10 on the SOI substrate 16Cm -3The Si layer, thickness is 2.5 μ m, as collector region;
Be the SiO of 400nm (2b) at substrate surface thermal oxidation one layer thickness 2Layer;
(2c) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 4 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 700 ℃ 2
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation 6.
Step 3, the bipolar device preparation.
(3a) photoetching collector region contact zone carries out the injection of N type impurity to collector region, and at 900 ℃, annealing 45min activator impurity, forming doping content is 5 * 10 19Cm -3The heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2Layer, the photoetching base carries out the injection of p type impurity to the base, and at 900 ℃, annealing 45min activator impurity, forming doping content is 3 * 10 18Cm -3The base;
(3c) at substrate surface thermal oxidation one SiO 2Layer, the injection of N type impurity is carried out to substrate in the photoetching emitter region, and at 900 ℃, annealing 45min activator impurity, becoming doping content is 1 * 10 20Cm -3The heavy doping emitter region, constitute bipolar transistor;
(3d) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 700 ℃, deposit one SiO 2Layer.
Step 4, the preparation of PMOS active area epitaxial material.
(4a) photoetching PMOS active area is used dry etching method, at the PMOS active area, etches the deep trouth that the degree of depth is 2.4 μ m;
(4b) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one layer thickness is the P type Si resilient coating of 300nm in deep trouth, doping content 3 * 10 15Cm -3
(4c) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one layer thickness is the P type SiGe layer of 1.4 μ m on the Si resilient coating, and Ge component bottom is 0%, and the upper strata is 20% Gradient distribution, and doping content is 3 * 10 18Cm -3
(4d) with the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one deck Ge component is 20% on the SiGe layer, and thickness is the P type SiGe layer of 300nm, and doping content is 8 * 10 19Cm -3, as the drain region of PMOS;
(4e) with the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one layer thickness is the P type strain Si layer of 4nm on P type SiGe layer, and doping content is 3 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4f) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one layer thickness is the N type strain Si layer of 30nm on P type strain Si layer, and as the PMOS channel region, doping content is 1 * 10 17Cm -3
(4g) with the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one layer thickness is the P type strain Si layer of 4nm on N type strain Si layer, and doping content is 3 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4h) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one layer thickness is that the Ge component of 300nm is fixed as 20% P type strain SiGe layer on strain Si layer, and as the PMOS source region, doping content is 8 * 10 19Cm -3, form the PMOS active area.
Step 5, the preparation of nmos device active area materials.
(5a) utilize the method for chemical vapor deposition (CVD), at 700 ℃, at substrate surface deposit one deck SiO 2
(5b) photoetching nmos device active area is used dry etching method, at the nmos device active area, etches the deep trouth that the degree of depth is 2.4 μ m;
(5c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the P type Si resilient coating of 300nm at nmos device active area selective growth one layer thickness, doping content 3 * 10 15Cm -3
(5d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one layer thickness is the P type SiGe layer of 1.8 μ m on the Si resilient coating, and the Ge composition gradient distributes, and the bottom is 0%, and the top is 20%, and doping content is 3 * 10 15Cm -3
(5e) utilize the method for chemical vapor deposition (CVD), at 700 ℃, selective growth one deck Ge component is 20% on the SiGe layer, and thickness is the P type SiGe layer of 300nm, and doping content is 1 * 10 17Cm -3
(5f) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type strain Si layer of 12nm on the SiGe layer, the nmos device channel region, and doping content is 1 * 10 17Cm -3, form the nmos device active area.
Step 6, PMOS isolates and leaks groove and prepares.
(6a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 700 ℃, deposit one SiO 2Layer;
(6b) isolated area is leaked in photoetching PMOS source, utilizes dry etch process, leaks isolated area in the PMOS source and etches the shallow slot that the degree of depth is 0.4 μ m;
(6c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, shallow-trench isolation is leaked in the formation source;
(6d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at the PMOS drain region is that 0.5 μ m leaks groove;
(6e) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 3 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, PMOS is leaked groove fills up, get rid of PMOS again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad.
Step 7, PMOS forms.
(7a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 700 ℃, deposit one SiO 2Layer;
(7b) photoetching gate groove window utilizes dry etch process, and etching the degree of depth in the PMOS gate region is 0.5 μ m gate groove;
(7c) utilize atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, at the HfO of substrate surface depositing high dielectric constant 2Layer, as the gate dielectric layer of PMOS, thickness is 8nm;
(7d) utilize chemical vapor deposition (CVD) method, at 700 ℃, the deposit doping content is 3 * 10 in gate groove 20Cm -3P type Poly-SiGe, the Ge component is 20%, and the PMOS gate groove is filled up;
(7e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS grid and source electrode, finally form the PMOS device.
Step 8, nmos device forms.
(8a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 700 ℃, deposit one SiO 2Layer;
(8b) photoetching nmos device active area utilizes atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, is the HfO of 8nm at nmos device surfaces of active regions deposit one layer thickness 2Layer is as the gate medium of nmos device;
(8c) utilize chemical vapor deposition (CVD) method, at 700 ℃, deposit one deck Ploy-SiGe layer on gate dielectric layer, the Ge component is 20%, and thickness is 240nm, and doping content is 3 * 10 20Cm -3
(8d) photoetching gate medium and grid Poly-SiGe form grid;
(8e) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, form N type lightly-doped source drain structure (N-LDD), doping content is 3 * 10 18Cm -3
(8f) utilize chemical vapor deposition (CVD) method, at 700 ℃, at the SiO of nmos device surfaces of active regions deposit one deck 4nm 2Layer utilizes dry etch process, etches away the SiO on surface 2Layer retains SiO at the Ploy-SiGe sidewall 2Form the grid side wall;
(8g) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, autoregistration generates the source region and the drain region of nmos device, and rapid thermal annealing, makes the doping content of nmos device active area reach 3 * 10 20Cm -3, finally form nmos device.
Step 9 constitutes the BiCMOS integrated circuit.
(9a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 700 ℃, deposit one SiO 2Layer;
(9b) lithography fair lead;
(9c) at substrate surface sputter layer of metal titanium (Ti), alloy;
(9d) photoetching lead-in wire; Form PMOS drain metal lead-in wire, source metal lead-in wire; The gate metal lead-in wire; Nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 30nm.
Embodiment 3: the preparation channel length is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 45nm, and concrete steps are following:
Step 1, epitaxial growth.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 300nm, upper layer of material is that doping content is 5 * 10 16Cm -3N type Si, thickness is 120nm;
Be the SiO of 500nm (1b) at substrate surface thermal oxidation one layer thickness 2Layer.
Step 2, the isolated area preparation.
(2a) epitaxial growth one deck doping content is 1 * 10 on the SOI substrate 17Cm -3The Si layer, thickness is 3 μ m, as collector region;
Be the SiO of 500nm (2b) at substrate surface thermal oxidation one layer thickness 2Layer;
(2c) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 800 ℃ 2
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 3, the bipolar device preparation.
(3a) photoetching collector region contact zone carries out the injection of N type impurity to collector region, and at 950 ℃, annealing 30min activator impurity, forming doping content is 1 * 10 20Cm -3The heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2Layer, the photoetching base carries out the injection of p type impurity to the base, and at 950 ℃, annealing 30min activator impurity, forming doping content is 5 * 10 18Cm -3The base;
(3c) at substrate surface thermal oxidation one SiO 2Layer, the injection of N type impurity is carried out to substrate in the photoetching emitter region, and at 950 ℃, annealing 30min activator impurity, becoming doping content is 5 * 10 20Cm -3The heavy doping emitter region, constitute bipolar transistor;
(3d) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 800 ℃, deposit one SiO 2Layer.
Step 4, the preparation of PMOS active area epitaxial material.
(4a) photoetching PMOS active area is used dry etching method, at the PMOS active area, etches the deep trouth that the degree of depth is 2.9 μ m;
(4b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one layer thickness is the P type Si resilient coating of 400nm in deep trouth, doping content 5 * 10 15Cm -3
(4c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one layer thickness is the P type SiGe layer of 1.7 μ m on the Si resilient coating, and Ge component bottom is 0%, and the upper strata is 15% Gradient distribution, and doping content is 5 * 10 18Cm -3
(4d) with the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one deck Ge component is 15% on the SiGe layer, and thickness is the P type SiGe layer of 400nm, and doping content is 1 * 10 20Cm -3, as the drain region of PMOS;
(4e) with the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one layer thickness is the P type strain Si layer of 5nm on P type SiGe layer, and doping content is 5 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one layer thickness is the N type strain Si layer of 45nm on P type strain Si layer, and as the PMOS channel region, doping content is 5 * 10 17Cm -3
(4g) with the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one layer thickness is the P type strain Si layer of 5nm on N type strain Si layer, and doping content is 5 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4h) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one layer thickness is that the Ge component of 400nm is fixed as 15% P type strain SiGe layer on strain Si layer, and as the PMOS source region, doping content is 1 * 10 20Cm -3, form the PMOS active area.
Step 5, the preparation of nmos device active area materials.
(5a) utilize the method for chemical vapor deposition (CVD), at 800 ℃, at substrate surface deposit one deck SiO 2
(5b) photoetching nmos device active area is used dry etching method, at the nmos device active area, etches the deep trouth that the degree of depth is 2.8 μ m;
(5c) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the P type Si resilient coating of 400nm at nmos device active area selective growth one layer thickness, doping content 5 * 10 15Cm -3
(5d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one layer thickness is the P type SiGe layer of 2 μ m on the Si resilient coating, and the Ge composition gradient distributes, and the bottom is 0%, and the top is 15%, and doping content is 5 * 10 15Cm -3
(5e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, selective growth one deck Ge component is 15% on the SiGe layer, and thickness is the P type SiGe layer of 400nm, and doping content is 5 * 10 17Cm -3
(5f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type strain Si layer of 15nm on the SiGe layer, the nmos device channel region, and doping content is 5 * 10 17Cm -3, form the nmos device active area.
Step 6, PMOS isolates and leaks groove and prepares.
(6a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 800 ℃, deposit one SiO 2Layer;
(6b) isolated area is leaked in photoetching PMOS source, utilizes dry etch process, leaks isolated area in the PMOS source and etches the shallow slot that the degree of depth is 0.5 μ m;
(6c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, shallow-trench isolation is leaked in the formation source;
(6d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at the PMOS drain region is that 0.6 μ m leaks groove;
(6e) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, PMOS is leaked groove fills up, get rid of PMOS again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad.
Step 7, preparation of PMOS grid and PMOS form.
(7a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 800 ℃, deposit one SiO 2Layer;
(7b) photoetching gate groove window utilizes dry etch process, and etching the degree of depth in the PMOS gate region is 0.7 μ m gate groove;
(7c) utilize atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, at the HfO of substrate surface depositing high dielectric constant 2Layer, as the gate dielectric layer of PMOS, thickness is 10nm;
(7d) utilize chemical vapor deposition (CVD) method, at 800 ℃, the deposit doping content is 5 * 10 in gate groove 20Cm -3P type Poly-SiGe, the Ge component is 10%, and the PMOS gate groove is filled up;
(7e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS grid and source electrode, finally form the PMOS device.
Step 8, nmos device forms.
(8a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 800 ℃, deposit one SiO 2Layer;
(8b) photoetching nmos device active area utilizes atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of 10nm at nmos device surfaces of active regions deposit one layer thickness 2Layer is as the gate medium of nmos device;
(8c) utilize chemical vapor deposition (CVD) method, at 800 ℃, deposit one deck Ploy-SiGe layer on gate dielectric layer, the Ge component is 10%, and thickness is 300nm, and doping content is 5 * 10 20Cm -3
(8d) photoetching gate medium and grid Poly-SiGe form grid;
(8e) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, form N type lightly-doped source drain structure (N-LDD), doping content is 5 * 10 18Cm -3
(8f) utilize chemical vapor deposition (CVD) method, at 800 ℃, at the SiO of nmos device surfaces of active regions deposit one deck 5nm 2Layer utilizes dry etch process, etches away the SiO on surface 2Layer retains SiO at the Ploy-SiGe sidewall 2Form the grid side wall;
(8g) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, autoregistration generates the source region and the drain region of nmos device, and rapid thermal annealing, makes the doping content of nmos device active area reach 5 * 10 20Cm -3, finally form nmos device.
Step 9 constitutes the BiCMOS integrated circuit.
(9a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 800 ℃, deposit one SiO 2Layer;
(9b) lithography fair lead;
(9c) at substrate surface sputter layer of metal titanium (Ti), alloy;
(9d) photoetching lead-in wire; Form PMOS drain metal lead-in wire, source metal lead-in wire; The gate metal lead-in wire; Nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 45nm.
The preparation that the embodiment of the invention provides has following advantage based on the strain Si BiCMOS integrated device and the preparation method of SOI substrate:
1. in the BiCMOS device architecture that the present invention makes; CMOS has partly adopted strain Si material manufacture conducting channel; Because strain Si material carrier mobility is far above body Si material, simulation and the hybrid digital-analog integrated circuit performance therefore made with this BiCMOS device architecture are excellent with the circuit performance that body Si makes;
2. the CMOS structure in the BiCMOS device architecture made of the present invention has made full use of the anisotropy of strain Si material stress, introduces tensile strain in the horizontal direction, has improved the nmos device electron mobility; Introduce compressive strain in vertical direction, improved the PMOS hole mobility; Therefore, performances such as this device frequency and current driving ability are higher than unidimensional relaxation Si cmos device;
3. in the preparation process of the present invention, strain Si layer is with the deposit of chemical vapor deposition (CVD) method, accurately control growing thickness; And the channel length of the PMOS among the CMOS is the thickness of Si layer; Thereby avoided the small size photoetching, reduced process complexity, reduced cost;
4. the raceway groove of PMOS is back type in the BiCMOS device architecture of the present invention's preparation; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. the MOS device in the BiCMOS device of the present invention's preparation has adopted the HfO of high K value 2As gate medium, improved the grid-control ability of MOS device, strengthened the electric property of cmos device;
6. the CMOS structure in the BiCMOS device of the present invention's preparation adopts the Poly-SiGe material as gate electrode, and its work function changes with the variation of Ge component; Through regulating Ge component among the Poly-SiGe; Realization CMOS threshold voltage can be adjusted continuously, has reduced processing step, has reduced difficult technique;
7. to prepare strain Si vertical-channel cmos device be after the bipolar device manufacturing is accomplished in the present invention; And the maximum temperature that relates in its technical process is 800 ℃; Be lower than the technological temperature that causes strained Si channel stress relaxation; Therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;
8. the BiCMOS device architecture of the present invention's preparation has adopted the SOI substrate, has improved the reliability of device and circuit.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (8)

1. the strain Si BiCMOS integrated device based on the SOI substrate is characterized in that said pair of strain plane BiCMOS device adopts common Si bipolar transistor, strain Si planar channeling nmos device and strain Si vertical-channel PMOS device.
2. the strain Si BiCMOS device based on the SOI substrate according to claim 1 is characterized in that the nmos device conducting channel is a strain Si material, is tensile strain along channel direction.
3. the strain Si BiCMOS device based on the SOI substrate according to claim 1 is characterized in that PMOS device strained Si channel is a vertical-channel in the cmos device, is compressive strain along channel direction, and is back the type structure.
4. the strain Si BiCMOS device based on the SOI substrate according to claim 1 is characterized in that, bipolar device adopts body Si material preparation on same SOI substrate.
5. the preparation method based on the strain Si BiCMOS integrated device of SOI substrate is characterized in that this preparation method comprises the steps:
The first step, to choose oxidated layer thickness be 150 ~ 300nm, and upper strata Si thickness is 100～120nm, and N type doping content is 1 * 10 16～1 * 10 17Cm -3The SOI substrate slice;
Second the step, epitaxial growth one deck doping content is 1 * 10 on the SOI substrate 16～1 * 10 17Cm -3The Si layer, thickness is 2～3 μ m, as collector region;
The 3rd step, be the SiO of 300～500nm at substrate surface thermal oxidation one layer thickness 2Layer, the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 ~ 5 μ m in the deep trench isolation zone; Utilize the method for chemical vapor deposition (CVD),, in deep trouth, fill SiO at 600～800 ℃ 2, with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
The 4th step, photoetching collector region contact zone carry out the injection of N type impurity to collector region, and at 800～950 ℃, annealing 30～90min activator impurity, forming doping content is 1 * 10 19～1 * 10 20Cm -3The heavy doping collector electrode;
The 5th the step, at substrate surface thermal oxidation one SiO 2Layer, the photoetching base carries out the injection of p type impurity to the base, and at 800～950 ℃, annealing 30～90min activator impurity, forming doping content is 1 * 10 18～5 * 10 18Cm -3The base;
The 6th the step, at substrate surface thermal oxidation one SiO 2Layer, the injection of N type impurity is carried out to substrate in the photoetching emitter region, and at 800～950 ℃, annealing 30～90min activator impurity, forming doping content is 5 * 10 19～5 * 10 20Cm -3The heavy doping emitter region, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer;
The 7th step, photoetching PMOS device active region are used dry etch process, at the PMOS device active region, etch the deep trouth that the degree of depth is 2～3 μ m; Utilize chemical vapor deposition (CVD) method, at 600～750 ℃, at PMOS device active region (being deep trouth) selective epitaxial growth seven layer materials: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.4～1.7 μ m, and bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 18Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the drain region of PMOS device; The 4th layer is that thickness is the P type strain Si layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD); Layer 5 is that thickness is the N type strain Si layer of 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, as the raceway groove of PMOS device; Layer 6 is that thickness is the P type strain Si layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD); Layer 7 is that the Ge component is 15～25%, and thickness is the P type SiGe of 200～400nm, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the active area of PMOS device;
The 8th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, at substrate surface deposit one deck SiO 2Photoetching nmos device active area at the nmos device active area, etches the deep trouth that the degree of depth is 1.9～2.8 μ m; Utilize chemical vapor deposition (CVD) method, at 600～750 ℃, at nmos device active area selective epitaxial growth four layer materials: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.5～2 μ m, and bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 5 * 10 16～5 * 10 17Cm -3The 4th layer is that thickness is the P type strain Si layer of 10～15nm, and doping content is 5 * 10 16～5 * 10 17Cm -3Raceway groove as nmos device;
The 9th step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching PMOS device source is leaked isolated area, utilizes dry etch process, etches the shallow slot that the degree of depth is 0.3～0.5 μ m in this zone; Utilize chemical vapor deposition (CVD) method again,, in shallow slot, fill SiO at 600～800 ℃ 2, form shallow-trench isolation;
Trench openings is leaked in the tenth step, photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is that 0.4～0.7 μ m leaks groove; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 1～5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad;
The 11 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching gate groove window utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4～0.7 μ m gate groove; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as the gate dielectric layer of PMOS device; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, the deposit doping content is 1～5 * 10 in gate groove 20Cm -3P type Poly-SiGe, the Ge component is 10～30%, and PMOS device gate groove is filled up; Photoetching gate medium and grid Poly-SiGe form grid and source electrode, finally form the PMOS device architecture;
The 12 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching nmos device active area utilizes atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at nmos device active area deposition thickness 2Layer is as the gate dielectric layer of nmos device; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is the P type Poly-SiGe of 200～300nm at nmos device active area deposition thickness, and doping content is 1～5 * 10 20Cm -3, the Ge component is 10～30%, photoetching gate medium and grid Poly-SiGe form grid; Utilize ion implantation technology, the nmos device active area is carried out N type ion inject, form N type lightly-doped source drain structure (N-LDD), doping content is 1～5 * 10 18Cm -3
The 13 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 3～5nm at entire substrate deposit one thickness 2Layer utilizes dry etch process, etches away the SiO on surface 2, form the nmos device grid curb wall, utilize ion implantation technology, the nmos device active area to be carried out N type ion inject, autoregistration generates the source region and the drain region of nmos device, and rapid thermal annealing, makes the doping content in nmos device source region and drain region reach 1～5 * 10 20Cm -3
The 14 step, utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer; Photoetching lead-in wire window, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the CMOS Metal Contact; The photoetching lead-in wire forms drain electrode, source electrode and gate metal lead-in wire, and constituting the MOS conducting channel is the strain Si BiCMOS integrated device based on the SOI substrate of 22～45nm.
6. method according to claim 5, wherein, the PMOS device channel length confirms that according to the N type strain Si layer thickness of the 8th step deposit get 22～45nm, the channel length of nmos device is determined by technology, gets 22～45nm.
7. method according to claim 5, chemical vapor deposition (CVD) the technological temperature decision during related maximum temperature went on foot to the 15 according to the 7th step in the strain Si cmos device manufacture process among this preparation method, maximum temperature is smaller or equal to 800 ℃.
8. the preparation method based on the strain Si BiCMOS integrated circuit of SOI substrate is characterized in that this preparation method comprises the steps:
Step 1, epitaxially grown implementation method is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 150nm, upper layer of material is that doping content is 1 * 10 16Cm -3N type Si, thickness is 100nm;
Be the SiO of 300nm (1b) at substrate surface thermal oxidation one layer thickness 2Layer;
Step 2, the implementation method of isolated area preparation is:
(2a) epitaxial growth one deck doping content is 1 * 10 on the SOI substrate 16Cm -3The Si layer, thickness is 2 μ m, as collector region;
Be the SiO of 300nm (2b) at substrate surface thermal oxidation one layer thickness 2Layer;
(2c) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2
(2e) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
Step 3, the implementation method of bipolar device preparation is:
(3a) photoetching collector region contact zone carries out the injection of N type impurity to collector region, and at 800 ℃, annealing 90min activator impurity, forming doping content is 1 * 10 19Cm -3The heavy doping collector electrode;
(3b) at substrate surface thermal oxidation one SiO 2Layer, the photoetching base carries out the injection of p type impurity to the base, and at 800 ℃, annealing 90min activator impurity, forming doping content is 1 * 10 18Cm -3The base;
(3c) at substrate surface thermal oxidation one SiO 2Layer, the injection of N type impurity is carried out to substrate in the photoetching emitter region, and at 800 ℃, annealing 90min activator impurity, becoming doping content is 5 * 10 19Cm -3The heavy doping emitter region, constitute bipolar transistor;
(3d) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
Step 4, the implementation method of PMOS device active region epitaxial material preparation is:
(4a) photoetching PMOS device active region is used dry etching method, at the PMOS device active region, etches the deep trouth that the degree of depth is 2 μ m;
(4b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type Si resilient coating of 200nm in deep trouth, doping content 1 * 10 15Cm -3
(4c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type SiGe layer of 1.4 μ m on the Si resilient coating, and Ge component bottom is 0%, and the upper strata is 25% Gradient distribution, and doping content is 1 * 10 18Cm -3
(4d) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one deck Ge component is 25% on the SiGe layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 * 10 19Cm -3, as the drain region of PMOS device;
(4e) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type strain Si layer of 3nm on P type SiGe layer, and doping content is 1 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the N type strain Si layer of 22nm on P type strain Si layer, and as the PMOS device channel region, doping content is 5 * 10 16Cm -3
(4g) with the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type strain Si layer of 3nm on N type strain Si layer, and doping content is 1 * 10 18Cm -3, as P type lightly-doped source drain structure (P-LDD);
(4h) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is that the Ge component of 200nm is fixed as 25% P type strain SiGe layer on strain Si layer, and as PMOS device source region, doping content is 5 * 10 19Cm -3, form the PMOS device active region;
Step 5, the implementation method of nmos device active area materials preparation is:
(5a) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO 2
(5b) photoetching nmos device active area is used dry etching method, at the nmos device active area, etches the deep trouth that the degree of depth is 1.9 μ m;
(5c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm at nmos device active area selective growth one layer thickness, doping content 1 * 10 15Cm -3
(5d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one layer thickness is the P type SiGe layer of 1.5 μ m on the Si resilient coating, and the Ge composition gradient distributes, and the bottom is 0%, and the top is 25%, and doping content is 1 * 10 15Cm -3
(5e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, selective growth one deck Ge component is 25% on the SiGe layer, and thickness is the P type SiGe layer of 200nm, and doping content is 5 * 10 16Cm -3
(5f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type strain Si layer of 10nm on the SiGe layer, the nmos device channel region, and doping content is 5 * 10 16Cm -3, form the nmos device active area;
Step 6, the PMOS device isolation with the implementation method of leaking the groove preparation is:
(6a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(6b) photoetching PMOS device source is leaked isolated area, utilizes dry etch process, leaks isolated area in the PMOS device source and etches the shallow slot that the degree of depth is 0.3 μ m;
(6c) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, shallow-trench isolation is leaked in the formation source;
(6d) trench openings is leaked in photoetching, utilizes dry etch process, and etching the degree of depth at PMOS device drain region is that 0.4 μ m leaks groove;
(6e) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad;
Step 7, the implementation method that preparation of PMOS device grid and PMOS device form is:
(7a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(7b) photoetching gate groove window utilizes dry etch process, and etching the degree of depth in PMOS device gate region is 0.4 μ m gate groove;
(7c) utilize atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, at the HfO of substrate surface depositing high dielectric constant 2Layer, as the gate dielectric layer of PMOS device, thickness is 6nm;
(7d) utilize chemical vapor deposition (CVD) method, at 600 ℃, the deposit doping content is 1 * 10 in gate groove 20Cm -3P type Poly-SiGe, the Ge component is 30%, and PMOS device gate groove is filled up;
(7e) carve gate medium and grid Poly-SiGe, in gate groove, form PMOS device grids and source electrode, finally form the PMOS device;
Step 8, the implementation method that nmos device forms is:
(8a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(8b) photoetching nmos device active area utilizes atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 6nm at nmos device surfaces of active regions deposit one layer thickness 2Layer is as the gate medium of nmos device;
(8c) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one deck Ploy-SiGe layer on gate dielectric layer, the Ge component is 30%, and thickness is 200nm, and doping content is 1 * 10 20Cm -3
(8d) photoetching gate medium and grid Poly-SiGe form grid;
(8e) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, form N type lightly-doped source drain structure (N-LDD), doping content is 1 * 10 18Cm -3
(8f) utilize chemical vapor deposition (CVD) method, at 600 ℃, at the SiO of nmos device surfaces of active regions deposit one deck 3nm 2Layer utilizes dry etch process, etches away the SiO on surface 2Layer retains SiO at the Ploy-SiGe sidewall 2Form the grid side wall;
(8g) utilize ion implantation technology, the nmos device active area is carried out N type ion inject, autoregistration generates the source region and the drain region of nmos device, and rapid thermal annealing, makes the doping content of nmos device active area reach 1 * 10 20Cm -3, finally form nmos device;
Step 9, the implementation method that constitutes the BiCMOS integrated circuit is:
(9a) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
(9b) lithography fair lead;
(9c) at substrate surface sputter layer of metal titanium (Ti), alloy;
(9d) photoetching lead-in wire; Form PMOS device drain metal lead wire, source metal lead-in wire; The gate metal lead-in wire; Nmos device drain metal lead-in wire, source metal lead-in wire, gate metal lead-in wire, bipolar transistor emitter metal lead-in wire, base metal lead-in wire, collector electrode metal lead-in wire, constituting the MOS conducting channel is strain Si BiCMOS integrated device and the circuit based on the SOI substrate of 22nm.
CN201210244374.9A 2012-07-16 2012-07-16 Strain Si BiCMOS (Bipolar-Complementary Metal-Oxide-Semiconductor) integrated device based on SOI (Silicon on Insulator) substrate and preparation method thereof Expired - Fee Related CN102738177B (en)

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