CN116598296A

CN116598296A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN116598296A
Application number: CN202310560859.7A
Authority: CN
Inventors: 李永亮; 刘昊炎; 罗军; 王文武
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2023-05-17
Filing date: 2023-05-17
Publication date: 2023-08-15

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, which relate to the technical field of semiconductors, and improve the working performance of a three-dimensional laminated complementary transistor when the transistor positioned at the upper part of the three-dimensional laminated complementary transistor is a P-type gate-all-around transistor and a semiconductor substrate and a channel region included in the P-type gate-all-around transistor contain germanium. The semiconductor device includes: the semiconductor device comprises a first semiconductor substrate, an N-type gate-all-around transistor, a second semiconductor substrate, a bonding interconnection layer and a P-type gate-all-around transistor. The N-type gate-all-around transistor is formed on the first semiconductor substrate. The second semiconductor substrate is formed over the N-type gate-all-around transistor. The bonding interconnection layer is positioned between the N-type gate-all-around transistor and the second semiconductor substrate. The material of the bonding interconnection layer comprises yttrium oxide, and the second semiconductor substrate and the N-type ring gate transistor are bonded through the bonding interconnection layer. The P-type gate-all-around transistor is formed on the second semiconductor substrate. The second semiconductor substrate and the P-type gate-all-around transistor comprise channel regions which contain germanium.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same.

Background

The three-dimensional stacked complementary transistor comprises an N-type transistor and a P-type transistor which are vertically stacked, the lateral distance between the N-type transistor and the P-type transistor is eliminated, and the effective channel width is allowed to be further increased, so that the working performance and the integration level of the semiconductor device are improved.

However, when the upper transistor of the three-dimensional stacked complementary transistor is a P-type gate-all-around transistor, and the semiconductor substrate and the channel region included in the P-type gate-all-around transistor contain germanium, the three-dimensional stacked complementary transistor manufactured by the conventional manufacturing method has poor operation performance.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for improving the working performance of a three-dimensional laminated complementary transistor under the condition that the transistor positioned at the upper part of the three-dimensional laminated complementary transistor is a P-type gate-all-around transistor and the semiconductor substrate and a channel region included in the P-type gate-all-around transistor contain germanium.

In order to achieve the above object, the present invention provides, in a first aspect, a semiconductor device comprising: the semiconductor device comprises a first semiconductor substrate, an N-type gate-all-around transistor, a second semiconductor substrate, a bonding interconnection layer and a P-type gate-all-around transistor.

The N-type gate-all-around transistor is formed on the first semiconductor substrate. The second semiconductor substrate is formed over the N-type gate-all-around transistor. The bonding interconnection layer is positioned between the N-type gate-all-around transistor and the second semiconductor substrate. The material of the bonding interconnection layer comprises yttrium oxide, and the second semiconductor substrate and the N-type ring gate transistor are bonded through the bonding interconnection layer. The P-type gate-all-around transistor is formed on the second semiconductor substrate. The second semiconductor substrate and the P-type gate-all-around transistor comprise channel regions which contain germanium.

Under the condition of adopting the technical scheme, the bonding interconnection layer and the second semiconductor substrate are sequentially formed on the N-type gate-all-around transistor along the thickness direction of the first semiconductor substrate. And, the P-type gate-all-around transistor is located on the second semiconductor substrate, so the P-type gate-all-around transistor is located on the N-type gate-all-around transistor. Meanwhile, the conductivity types of the P-type ring gate transistor and the N-type ring gate transistor are opposite, so that the N-type ring gate transistor and the P-type ring gate transistor form a three-dimensional laminated complementary transistor. In this case, the germanium-containing semiconductor material such as germanium-silicon or germanium has higher carrier mobility than the silicon material, and therefore, in the case where germanium is contained in the channel region included in the P-type gate-all-around transistor, the carrier mobility in the channel region included in the P-type gate-all-around transistor can be improved, and the driving performance of the P-type gate-all-around transistor can be improved. And the P-type ring gate transistor is formed on the second semiconductor substrate, germanium is also contained in the second semiconductor substrate, and at the moment, the material of the second semiconductor substrate is the same as or similar to the material of a channel region included in the P-type ring gate transistor, so that the degree of mismatch between the second semiconductor substrate and the material of the channel region included in the P-type ring gate transistor can be reduced, the formation quality of the channel region included in the P-type ring gate transistor is improved, and the working performance of the P-type ring gate transistor is further improved.

And secondly, the bonding interconnection layer between the N-type ring gate transistor and the second semiconductor substrate comprises yttrium oxide, so that the N-type ring gate transistor and the second semiconductor substrate are bonded together at a low temperature through the yttrium oxide, the crystal quality of the second semiconductor substrate is prevented from being influenced by a higher bonding temperature (for example, in the case that the material of the second semiconductor substrate is germanium, the second semiconductor substrate is easily oxidized in a higher bonding environment, and the like), and the crystal quality of the P-type ring gate transistor formed on the second semiconductor substrate is further improved. In addition, the semiconductor device provided by the invention is characterized in that a second semiconductor substrate is formed on the formed N-type gate-all-around transistor in a bonding mode, and a P-type gate-all-around transistor is formed on the second semiconductor substrate. The aspect ratio of the structure when the N-type ring gate transistor and the P-type ring gate transistor are independently formed is the same as that of the conventional ring gate transistor, and the vertical aspect ratio of the operation is larger because the corresponding film layers for manufacturing the N-type ring gate transistor and the P-type ring gate transistor are not required to be processed simultaneously like the existing single chip (monolithic) integration mode, so that the manufacturing difficulty of the three-dimensional laminated complementary transistor is reduced.

In a second aspect, the present invention also provides a method for manufacturing a semiconductor device, the method comprising: first, a first semiconductor substrate and a second semiconductor substrate are provided. Next, an N-type gate-all-around transistor and a first bond interconnect sub-layer are sequentially formed on the first semiconductor substrate. The material of the first bond interconnect sublayer comprises yttria. A second bond interconnect sub-layer is formed on one side of the second semiconductor substrate. The material of the second bond interconnect sublayer comprises yttria. And then, bonding the N-type gate-all-around transistor and the second semiconductor substrate together through the first bonding interconnection sub-layer and the second bonding interconnection sub-layer by adopting a low-temperature bonding process, and forming a bonding interconnection layer. The bond interconnect layer includes a first bond interconnect sublayer and a second bond interconnect sublayer. And forming a P-type gate-all-around transistor on the second semiconductor substrate. The second semiconductor substrate and the P-type gate-all-around transistor comprise channel regions which contain germanium.

The advantages of the second aspect and various implementations of the present invention may be referred to for analysis of the advantages of the first aspect and various implementations of the first aspect, which are not described here in detail.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

fig. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention in a manufacturing process;

fig. 2 is a schematic diagram of a second structure of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a semiconductor device according to an embodiment of the present invention in a manufacturing process;

fig. 4 is a schematic diagram of a semiconductor device according to an embodiment of the present invention in a manufacturing process;

fig. 5 is a schematic diagram showing a structure of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 6 is a schematic diagram showing a structure of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a semiconductor device according to an embodiment of the present invention in a manufacturing process;

fig. 8 is a schematic structural diagram eight of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a semiconductor device according to an embodiment of the present invention in a manufacturing process;

Fig. 10 is a schematic diagram showing a structure of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 11 is a schematic diagram eleven structural diagrams of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 12 is a schematic diagram showing a semiconductor device according to an embodiment of the present invention in a manufacturing process;

fig. 13 is a schematic diagram of a semiconductor device according to an embodiment of the present invention in a manufacturing process;

fig. 14 is a schematic diagram showing a structure fourteen of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 15 is a schematic diagram fifteen of a semiconductor device according to an embodiment of the present invention in a manufacturing process;

fig. 16 is a schematic diagram showing a structure of a semiconductor device in a manufacturing process according to an embodiment of the present invention;

fig. 17 is a schematic diagram showing seventeen structures of a semiconductor device in a manufacturing process according to an embodiment of the present invention.

Reference numerals: 11 is a first semiconductor substrate, 12 is an N-type ring gate transistor, 13 is a first bonding interconnection sublayer, 14 is a silicon-based semiconductor substrate, 15 is a buffer layer, 16 is an etching stop layer, 17 is a second semiconductor substrate, 18 is a second bonding interconnection sublayer, 19 is a bonding interconnection layer, 20 is a silicon dioxide layer, 21 is a yttrium oxide layer, 22 is a sacrificial layer, 23 is a channel layer, 24 is a fin structure, 25 is a shallow trench isolation structure, 26 is a sacrificial gate, 27 is a gate sidewall, 28 is a source region, 29 is a drain region, 30 is an interlayer dielectric layer, 31 is a channel region, 32 is a gate stack structure, 33 is a first connection portion, 34 is a second connection portion, 35 is a third connection portion, and 36 is a fourth connection portion.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

However, when the upper transistor of the three-dimensional stacked complementary transistor is a P-type gate-all-around transistor, and the semiconductor substrate and the channel region included in the P-type gate-all-around transistor contain germanium, the three-dimensional stacked complementary transistor manufactured by the conventional manufacturing method has poor operation performance. Specifically, the existing manufacturing method of the three-dimensional laminated complementary transistor mainly comprises the following two integration schemes:

first kind: a three-dimensional stacked complementary transistor is fabricated using a monolithic (monolithic) approach. Specifically, the process of manufacturing the three-dimensional stacked complementary transistor by using the conventional manufacturing method will be described by taking the example that the N-type transistor and the P-type transistor are both the gate-around transistor and the P-type transistor is located above the N-type transistor as an example: first, a fin structure is formed on a semiconductor substrate. The fin structure includes at least two layers of a laminate. Each laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, and the materials of the sacrificial layer and the channel layer are semiconductor materials. Then, sacrificial gates and sidewalls are formed across portions of the fin structure. And selectively etching the fin structure by taking the sacrificial gate and the side wall as masks to remove the part of the fin structure exposed outside the sacrificial gate and the side wall. Then, a first semiconductor material for manufacturing a source region and a drain region included in the N-type transistor is formed on the semiconductor substrate. At this time, since the sacrificial layer and the channel layer corresponding to the N-type transistor and the P-type transistor are exposed to the outside after etching, the sacrificial layer and the channel layer can be used as seed layers for epitaxial growth of the first semiconductor material, and the first semiconductor material is formed not only on both sides of the sacrificial layer and the channel layer corresponding to the N-type transistor but also on both sides of the sacrificial layer and the channel layer corresponding to the P-type transistor after etching. Then, the first semiconductor material located on two sides of the corresponding sacrificial layer and the etched residual part of the channel layer of the P-type transistor is required to be removed, and the residual part of the first semiconductor material forms a source region and a drain region included in the N-type transistor. Then, forming an epitaxial isolation layer covering the surface of the source region and the drain region, which are included in the N-type transistor and are away from the substrate; and forming a source region and a drain region of the P-type transistor on the epitaxial isolation layer by adopting an epitaxial growth process. Finally, the sacrificial gate and the part of the sacrificial layer in the gate forming region are removed; and forming a gate stack structure surrounding the periphery of the channel region to obtain the three-dimensional laminated complementary transistor.

Second kind: the three-dimensional stacked complementary transistor is fabricated in a sequential manner by forming the underlying transistor according to conventional semiconductor device fabrication processes, and after forming the corresponding contact electrode of the underlying transistor, covering the top of the underlying transistor with a semiconductor layer by wafer transfer using wafer-to-wafer bonding techniques. And then, based on the semiconductor layer integrated top-layer transistor, connecting the top gate and the bottom gate to obtain the three-dimensional laminated complementary transistor.

As can be seen from the above-mentioned manufacturing process of the first manner, in order to isolate the source region, the drain region and the channel region included in the transistors of the bottom layer and the top layer, the vertical distance between the two transistors is relatively large, so that the manner has a relatively high aspect ratio vertical structure, which results in a relatively large technical challenge in subsequent patterning of fin structures, sacrificial gates, gate sidewalls, source and drain electrodes, and the like, and the manufacturing process of the three-dimensional stacked complementary transistor corresponding to the manner is relatively complex. The bonding temperature of the second three-dimensional stacked complementary transistor is high, which results in poor formation quality of the semiconductor substrate bonded above the underlying transistor and made of germanium, which is not beneficial to improving the working performance of the three-dimensional stacked complementary transistor.

In order to solve the technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. The semiconductor device provided by the embodiment of the invention comprises a bonding interconnection layer, a second semiconductor substrate and a P-type gate-all-around transistor, wherein the bonding interconnection layer, the second semiconductor substrate and the P-type gate-all-around transistor are sequentially arranged on the N-type gate-all-around transistor. Wherein the material of the bonding interconnect layer comprises yttria to reduce a bonding temperature when the N-type gate-all-around transistor and the second semiconductor substrate are bonded together through the bonding interconnect layer.

As shown in fig. 15 and 16, a semiconductor device provided in an embodiment of the present invention includes: a first semiconductor substrate 11, an N-type gate-all-around transistor 12, a second semiconductor substrate 17, a bonding interconnection layer 19, and a P-type gate-all-around transistor. The N-type gate around transistor 12 is formed on the first semiconductor substrate 11. A second semiconductor substrate 17 is formed over the N-type gate-all-around transistor 12. A bond interconnect layer 19 is located between the N-type gate-all-around transistor 12 and the second semiconductor substrate 17. The material of the bonding interconnect layer 19 includes yttrium oxide, and the second semiconductor substrate 17 and the N-type gate around transistor 12 are bonded through the bonding interconnect layer 19. A P-type gate-all-around transistor is formed on the second semiconductor substrate 17. The second semiconductor substrate 17 and the P-type gate-all-around transistor comprise a channel region 31 which contains germanium.

Specifically, the specific structure, materials, and the like of the first semiconductor substrate may be determined according to the actual application scenario, and are not specifically limited herein. The first semiconductor base may be a silicon-based semiconductor substrate on which no structure is formed, for example. Alternatively, the first semiconductor base may be a semiconductor substrate formed with some structures. For example: when the semiconductor device provided in the embodiment of the invention is a semiconductor device of a second layer or higher in an integrated circuit, the first semiconductor substrate includes a semiconductor structure located under an N-type gate-all-around transistor, and the like.

For the N-type gate-all-around transistor described above, the N-type gate-all-around transistor may include a source region, a drain region, a channel region, and a gate stack structure. The channel region included in the N-type gate-all-around transistor is located between the source region and the drain region included in the N-type gate-all-around transistor and is respectively contacted with the source region and the drain region included in the N-type gate-all-around transistor from the structural aspect. The channel region included in the N-type gate-all-around transistor may include at least one nanostructure, each of which is in a gap with the first semiconductor substrate. Specifically, when the channel region included in the N-type gate-all-around transistor includes at least two nanostructures, the different nanostructures may be disposed at intervals along the thickness direction of the first semiconductor substrate, or may be disposed at intervals along the width direction of the gate stack structure included in the N-type gate-all-around transistor. As for the crystal orientation of the channel region included in the N-type gate-all-around transistor, the crystal orientation may be set according to the actual application scenario. For example: the N-type gate-all-around transistor may include a channel region having a [100] crystal orientation. In this case, in a practical application process, electron mobility and hole mobility corresponding to channel regions having different crystal orientations are different. The channel region with the [100] crystal orientation is favorable for transmitting electrons, and channel carriers of the N-type gate-all-around transistor are electrons, so that when the crystal orientation of the channel region included in the N-type gate-all-around transistor is the [100] crystal orientation, the electron mobility of the channel region included in the N-type gate-all-around transistor can be improved, and the driving performance of the N-type gate-all-around transistor can be improved.

The gate stack structure included in the N-type gate-all-around transistor surrounds the periphery of the channel region included in the N-type gate-all-around transistor. The gate stack structure included in the N-type gate-all-around transistor may include a gate dielectric layer and a gate electrode. The gate dielectric layer of the N-type gate-all-around transistor surrounds the periphery of the channel region of the N-type gate-all-around transistor, and the grid electrode of the N-type gate-all-around transistor is formed on the gate dielectric layer of the N-type gate-all-around transistor.

From the aspect of materials, the N-type gate-all-around transistor comprises a source region, a drain region and a channel region which are made of semiconductor materials. Specifically, the source region, the drain region and the channel region of the N-type gate-all-around transistor may be made of polycrystalline semiconductor material or monocrystalline semiconductor material. Preferably, the N-type gate-all-around transistor includes source, drain and channel regions of single crystal semiconductor material. Compared with the polycrystalline semiconductor material, the single crystal semiconductor material has lower resistance, can reduce the on-resistance of a source region and a drain region included in the N-type gate-all-around transistor, and is beneficial to improving the driving performance of the N-type gate-all-around transistor.

As for the material of the gate stack structure included in the N-type gate-all-around transistor, the material of the gate dielectric layer included in the gate stack structure in the N-type gate-all-around transistor may be HfO ₂ 、ZrO ₂ 、TiO ₂ Or Al ₂ O ₃ And insulating materials. The gate stack structure of the N-type gate-all-around transistor may include a gate made of a conductive material such as TiN, taN or TiSiN.

In some cases, as shown in fig. 16, the N-type gate-all-around transistor 12 may further include a shallow trench isolation structure 25, a gate sidewall 27, and an interlayer dielectric layer 30. The N-type gate-all-around transistor 12 includes a shallow trench isolation structure 25 for isolating different active regions of the first semiconductor substrate 11 from leakage. The thickness of the shallow trench isolation structure 25 may be set according to practical situations. The material of the shallow trench isolation structure 25 may be SiN, si ₃ N ₄ 、SiO ₂ Or an insulating material such as SiCO. The gate sidewall 27 included in the N-type gate-all-around transistor 12 is formed at least on both sides of the gate stack 32 included in the N-type gate-all-around transistor 12 along the length direction thereof, so as to isolate the gate stack 32 included in the N-type gate-all-around transistor 12 from other conductive structures, thereby improving the electrical characteristics of the N-type gate-all-around transistor 12. The gate sidewall 27 included in the N-type surrounding gate transistor 12 may have the same thickness at portions of the gate stack 32 included in the N-type surrounding gate transistor 12 along both sides in the length direction. The material of the gate sidewall 27 included in the N-type gate-all-around transistor 12 may be an insulating material such as silicon oxide or silicon nitride. In addition, the interlayer dielectric layer 30 included in the N-type gate-all-around transistor 12 is covered on the first semiconductor substrate 11, and the top thereof is flush with the top of the gate stack structure 32 included in the N-type gate-all-around transistor 12. In the actual manufacturing process, the existence of the interlayer dielectric layer 30 included in the N-type gate-all-around transistor 12 can protect the source region 28 and the drain region included in the N-type gate-all-around transistor 12 from the subsequent removal of the sacrificial gate and the sacrificial layer The yield of the N-type gate-all-around transistor 12 is improved. The material of the interlayer dielectric layer 30 included in the N-type gate-all-around transistor 12 may be an insulating material such as silicon oxide or silicon nitride.

For the P-type gate-all-around transistor described above, the P-type gate-all-around transistor may include a source region, a drain region, a channel region, and a gate stack structure. The channel region included in the P-type gate-all-around transistor is located between the source region and the drain region included in the P-type gate-all-around transistor and is respectively contacted with the source region and the drain region included in the P-type gate-all-around transistor from the structural aspect. And, the channel region included in the P-type gate-all-around transistor includes at least one nanostructure. Each nanostructure has a void with the second semiconductor substrate. In addition, when the channel region included in the P-type gate-all-around transistor includes at least two nanostructures, the different nanostructures of the P-type gate-all-around transistor may be disposed at intervals along the thickness direction of the second semiconductor substrate, or may be disposed at intervals along the width direction of the gate stack structure included in the P-type gate-all-around transistor. As for the crystal orientation of the channel region included in the P-type gate-all-around transistor, the crystal orientation may be set according to the practical application scenario. For example: the P-type gate-all-around transistor may include a channel region having a [110] crystal orientation. In this case, as described above, the electron mobility and the hole mobility corresponding to the channel regions having different crystal orientations are different. In addition, the channel region with the [110] crystal orientation is favorable for transporting holes, and channel carriers of the P-type gate-all-around transistor are holes, so that when the crystal orientation of the channel region included in the P-type gate-all-around transistor is the [110] crystal orientation, the hole mobility of the channel region included in the P-type gate-all-around transistor can be improved, and the driving performance of the P-type gate-all-around transistor can be improved.

As for the gate stack structure included in the P-type gate-all-around transistor, it may include a gate dielectric layer and a gate electrode. The gate dielectric layer of the P-type gate-all-around transistor surrounds the periphery of the channel region of the P-type gate-all-around transistor, and the grid electrode of the P-type gate-all-around transistor is formed on the gate dielectric layer of the P-type gate-all-around transistor.

In terms of materials, the source region and the drain region of the P-type gate-all-around transistor are made of silicon, germanium-silicon or germanium semiconductor materials. The material of the channel region included in the P-type gate-all-around transistor can be germanium or germanium-containing semiconductor material such as germanium and silicon. Specifically, the content of germanium in the material of the channel region included in the P-type gate-all-around transistor may be set according to the actual application scenario, so long as the P-type gate-all-around transistor can be applied to the semiconductor device provided by the embodiment of the present invention. Illustratively, the P-type gate-all-around transistor may include a channel region having a germanium content of 50% or more and 100% or less. In this case, the P-type gate-all-around transistor has a higher germanium content in the channel region, which is beneficial to improving the carrier mobility of the P-type gate-all-around transistor and further improving the electrical performance of the P-type gate-all-around transistor. Furthermore, the material of the channel region included in the P-type gate-all-around transistor may be a polycrystalline germanium semiconductor material or a monocrystalline germanium semiconductor material. Preferably, the channel region of the P-type gate-all-around transistor is made of monocrystalline germanium-containing semiconductor material, so that on-resistance of a source region and a drain region of the P-type gate-all-around transistor is reduced, and driving performance of the N-type gate-all-around transistor is improved.

As for the material of the gate stack included in the P-type gate-all-around transistor, reference may be made to the material of the gate stack included in the N-type gate-all-around transistor described above, and the description thereof will be omitted here. In addition, the P-type gate-all-around transistor can also comprise a shallow trench isolation structure, a grid side wall and an interlayer dielectric layer. The information such as the material and the formation position of the shallow trench isolation structure, the grid side wall and the interlayer dielectric layer included in the P-type gate-all-around transistor can refer to the information such as the material and the formation position of the shallow trench isolation structure, the grid side wall and the interlayer dielectric layer included in the N-type gate-all-around transistor, and will not be described herein.

It should be noted that, as shown in fig. 17, the semiconductor device provided in the embodiment of the present invention further includes a connection structure. The connection structure is used for realizing interconnection between the N-type gate-all-around transistor and the P-type gate-all-around transistor and leading out a source region, a drain region 29 and a gate stack structure 32 respectively included in the N-type gate-all-around transistor and the P-type gate-all-around transistor. Specifically, the specific formation position and connection correspondence of the connection structure can be determined according to the effect of the connection structure on the three-dimensional stacked complementary transistor formed by the N-type gate-all-around transistor and the P-type gate-all-around transistor in an actual application scene. For example: as shown in fig. 17, in the case of using the above three-dimensional stacked complementary transistor as an inverter, the connection structure includes a first connection portion 33, a second connection portion 34, a third connection portion 35, and a fourth connection portion 36 that are insulated from each other. The first connection portion 33 may be located at one side of the gate stack structure 32 included in the P-type gate-all-around transistor in the width direction thereof and penetrates the second semiconductor substrate and the bonding interconnection layer. The first connection portion 33 is used for electrically connecting and extracting the gate stack 32 included in the N-type gate-all-around transistor and the P-type gate-all-around transistor. The second connection portion 34 is used to electrically connect and lead out the drain region 29 included in the N-type gate-all-around transistor and the P-type gate-all-around transistor. The third connection portion 35 is used to realize extraction of a source region included in the N-type gate-all-around transistor. The fourth connection portion 36 is used to realize extraction of a source region included in the P-type gate-all-around transistor.

For the second semiconductor substrate, the material of the second semiconductor substrate may be any germanium-containing semiconductor material. The material of the second semiconductor substrate is the same as or different from the material of the channel region included in the P-type gate-all-around transistor. In addition, the germanium content in the second semiconductor substrate may be determined according to the germanium content in the channel region included in the P-type gate-all-around transistor and the actual application scenario. Illustratively, the germanium content in the second semiconductor substrate may be 50% or more and 100% or less. At this time, the germanium content in the second semiconductor substrate is higher, which is advantageous for forming a channel region included in the P-type gate-all-around transistor having the same higher germanium content thereon, so as to improve carrier mobility of the P-type gate-all-around transistor formed on the second semiconductor substrate.

The crystal orientation of the second semiconductor substrate can be determined according to the crystal orientation of the channel region included in the P-type gate-all-around transistor and the practical application scenario. The crystal orientation of the second semiconductor substrate may be the same as that of the channel region included in the P-type gate-all-around transistor, so that the channel region included in the P-type gate-all-around transistor with the same crystal orientation is formed on the second semiconductor substrate with the crystal orientation meeting the working requirement, and the yield of the P-type gate-all-around transistor is improved.

In terms of conductivity type, the second semiconductor substrate may be doped with impurities, and the conductivity type of the impurities in the second semiconductor substrate is opposite to that of the impurities in the source region and the drain region included in the P-type gate-all-around transistor, so as to inhibit parasitic channel leakage in the P-type gate-all-around transistor. Alternatively, the second semiconductor substrate may be an intrinsic semiconductor substrate whose portion located under a channel region included in the P-type gate-all-around transistor is recessed inward. At this time, compared with the top contact of the parasitic channel with a flat surface, the gate stack structure included in the conventional P-type gate-all-around transistor has a larger contact area between the gate stack structure included in the P-type gate-all-around transistor and the second semiconductor substrate due to the contact of the portion of the gate stack structure included in the P-type gate-all-around transistor below the channel region and the surface of the portion of the second semiconductor substrate recessed inwards, thereby increasing the length of the gate stack structure in contact with the portion (parasitic channel) of the second semiconductor substrate below the channel region, enhancing the control capability of the gate stack structure included in the P-type gate-all-around transistor on the portion of the second semiconductor substrate below the channel region, further suppressing parasitic channel leakage, and facilitating the improvement of the operating performance of the P-type gate-all-around transistor

For the above-mentioned bonding interconnection layer, the thickness of the bonding interconnection layer may be set according to actual requirements. For example, the thickness of the bonding interconnection layer may be 20nm or more and 100nm or less. In this case, the thickness of the above-mentioned bonding interconnection layer is within the above-mentioned range, it is possible to prevent the bonding strength between the N-type gate-all-around transistor and the second semiconductor substrate from being weak due to the small thickness of the bonding interconnection layer, and it is also possible to prevent the bonding temperature from being high due to the small thickness of the bonding interconnection layer such that the thickness of the portion of the bonding interconnection layer in which the material is yttria is also small. Meanwhile, the problems of material waste and the like caused by the larger thickness of the bonding interconnection layer can be prevented, the manufacturing cost of the semiconductor device can be controlled, and the integration level of the semiconductor device in the longitudinal direction can be improved.

The bonding interconnection layer may have a single-layer structure made of only yttrium oxide material, or may have a stacked-layer structure made of a plurality of materials. When the bonding interconnection layer has the laminated structure, the specific materials and structure of the bonding interconnection layer can be set according to the actual application scene. As illustrated in fig. 16, the bonding interconnection layer 19 may include a yttria layer 21, and a silicon dioxide layer 20 located at both sides of the yttria layer 21, along a thickness direction of the second semiconductor substrate 17. In this case, in an actual manufacturing process, an atomic layer deposition process may be used to form a portion of the bonding interconnection layer 19 where the material is yttria, so as to improve the compactness of the portion of the material that is yttria, and further improve the bonding strength between the N-type gate-all-around transistor 12 and the second semiconductor substrate 17. Also, in order to achieve bonding of the N-type gate all around transistor 12 and the second semiconductor substrate 17 together, the total thickness of the above-mentioned bonding interconnection layer 19 needs to reach a corresponding value. In this case, a process with a relatively high deposition rate such as chemical vapor deposition may be used before bonding, and after forming a silicon oxide layer 20 with a certain thickness on the bonding surface of the N-type gate all-around transistor 12 and the second semiconductor substrate 17, an atomic layer deposition process may be used to form a corresponding thickness of yttrium oxide on each silicon oxide layer 20, so as to increase the manufacturing rate while reducing the bonding temperature and increasing the bonding strength through the yttrium oxide layer 21. Meanwhile, the silicon dioxide layer 20 has higher lattice matching degree with the N-type gate-all-around transistor 12 and the second semiconductor substrate 17 respectively, so that the silicon dioxide layer has better surface morphology, the adhesiveness to the stacked yttrium oxide layer 21 is realized, and the structural stability of the semiconductor device is further improved.

Specifically, the thicknesses of the silicon dioxide layer and the yttrium oxide layer can be set according to actual requirements. For example: the thickness of the silicon dioxide layer may be 5nm or more and 35nm or less. For example: the thickness of the yttria layer may be 10nm or more and 30nm or less.

Next, as shown in fig. 5 to 16, the bonding interconnection layer 19 between the N-type gate around transistor 12 and the second semiconductor substrate 17 is made of a material including yttria so as to bond the N-type gate around transistor 12 and the second semiconductor substrate 17 together at a low temperature by means of yttria, thereby preventing the bonding temperature from being high and affecting the crystal quality of the second semiconductor substrate 17 (for example, in the case where the material of the second semiconductor substrate is germanium, the second semiconductor substrate is easily oxidized in a high bonding environment, etc.), and further improving the crystal quality of the P-type gate around transistor formed on the second semiconductor substrate 17. In addition, the semiconductor device provided in the embodiment of the invention forms the second semiconductor substrate 17 on the formed N-type gate around transistor 12 by bonding, and forms the P-type gate around transistor on the second semiconductor substrate 17. The aspect ratio of the structure when the N-type gate-all-around transistor 12 and the P-type gate-all-around transistor are formed independently is the same as that of the conventional gate-all-around transistor, and the vertical aspect ratio of the operation is larger because the corresponding film layers for manufacturing the N-type gate-all-around transistor 12 and the P-type gate-all-around transistor are not required to be processed simultaneously like the existing single-chip (single) integration mode, so that the manufacturing difficulty of the three-dimensional stacked complementary transistor is reduced.

In a second aspect, embodiments of the present invention provide a method for manufacturing a semiconductor device. Hereinafter, the manufacturing process will be described based on perspective views of the operations shown in fig. 1 to 17. Specifically, the method for manufacturing the semiconductor device comprises the following steps:

first, a first semiconductor substrate and a second semiconductor substrate are provided. For information such as specific structures and materials of the first semiconductor substrate, reference may be made to the foregoing, and details are not repeated herein.

In an actual manufacturing process, this step may be to provide only the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate may be the same as or greater than the thickness of the second semiconductor substrate in the manufactured semiconductor device.

Alternatively, as shown in fig. 3, the buffer layer 15 and the second semiconductor base 17 may be sequentially formed on the silicon-based semiconductor substrate 14 using an epitaxial process or the like before providing the first semiconductor base and the second semiconductor base. In this case, the total thickness of the silicon-based semiconductor substrate 14, the buffer layer 15, and the second semiconductor base 17 is greater than the thickness of the second semiconductor base 17. Based on this, the subsequent formation of the second bonding interconnect sub-layer 18 on the second semiconductor substrate 17 and the transfer of the low-temperature bonding can be realized by transferring the composite structure with a larger thickness (the composite structure includes the silicon-based semiconductor substrate 14, the buffer layer 15 and the second semiconductor substrate 17) to prevent the second semiconductor substrate 17 from being damaged in the transfer process due to the smaller thickness of the second semiconductor substrate 17, and the yield of the semiconductor device can be improved.

The existence of the buffer layer can reduce the lattice mismatch degree between the second semiconductor substrate and the silicon-based semiconductor substrate, and is beneficial to improving the formation quality of the second semiconductor substrate. Specifically, the material of the buffer layer is the same as or similar to the material of the second semiconductor substrate. The thickness of the buffer layer can be set according to the actual application scene. For example: the thickness of the buffer layer may be 700nm or more and 2 μm or less.

As for the specific forming process of the buffer layer, the preparation of the buffer layer can be realized by adopting an epitaxial process at the same ambient temperature. Alternatively, an epitaxial process may be used, and the buffer layer may be formed sequentially in a high temperature environment and a low temperature environment. Wherein the temperature in the high-temperature environment is 600 ℃ or higher, and the temperature in the low-temperature environment is 400 ℃ or higher and 500 ℃ or lower. In this case, the epitaxial buffer layer is strained at different ambient temperatures along different regions of the thickness of the silicon-based semiconductor substrate by releasing the strain at the buffer material formed at low temperature, so that most dislocations and defects in the buffer layer are confined within the portion of the buffer layer that is epitaxial at low temperature, facilitating the formation of a high quality second semiconductor substrate on the buffer layer.

After the buffer layer is formed, a second semiconductor substrate may be directly formed on the buffer layer by using an epitaxial process or the like. Alternatively, as shown in fig. 3, after forming the buffer layer 15 on the silicon-based semiconductor substrate 14, and before forming the second semiconductor base 17, an etching stop layer 16 may be formed on the buffer layer 15 by an epitaxial process or the like. The material of the etching stop layer 16 is different from that of the second semiconductor substrate 17, so as to prevent the etching solution for removing the buffer layer 15 from damaging the second semiconductor substrate 17 after the subsequent low-temperature bonding process and removing the silicon-based semiconductor substrate 14, thereby ensuring a higher formation quality of the second semiconductor substrate 17.

Specifically, the material of the etching stop layer may be any semiconductor material different from the second semiconductor substrate, so long as the material can be applied to the method for manufacturing a semiconductor device provided in the embodiment of the present invention. The thickness of the etching stop layer can be set according to practical requirements. For example: the thickness of the etch stop layer may be 10nm or more and 50nm or less.

In the actual manufacturing process, after the second semiconductor substrate is provided and before the second bonding interconnection sub-layer is formed on one side of the second semiconductor substrate, a chemical mechanical polishing process and other processes can be adopted to planarize one side of the second semiconductor substrate corresponding to the second bonding interconnection sub-layer, so that the compactness of the second bonding interconnection sub-layer formed on the second semiconductor substrate in the follow-up process is improved, and the bonding strength of the follow-up low-temperature bonding is further improved.

After the first semiconductor substrate is provided as described above, as shown in fig. 1 and 2, an N-type gate around transistor 12 and a first bonding interconnect sublayer 13 are sequentially formed on the first semiconductor substrate 11. The material of the first bond interconnect sublayer 13 comprises yttria.

Specifically, the manufacturing process of the N-type gate-all-around transistor is not particularly limited in the embodiment of the present invention. In addition, the first bonding interconnect sub-layer may be formed using a chemical vapor deposition or atomic layer deposition process, or the like. The structure of the first bond interconnect sublayer may be determined with reference to the structure of the bond interconnect sublayer described previously.

For example: in the case where the bonding interconnect layer is a single-layer structure formed only of yttria, the first bonding interconnect sub-layer is a single-layer structure formed only of yttria and has a thickness smaller than that of the bonding interconnect layer.

Also for example: in the case where the bonding interconnect layer includes the above-described yttria layer and two silicon dioxide layers, the first bonding interconnect sub-layer includes one silicon dioxide layer and one yttria layer. And the first bonding interconnect sublayer comprises a thickness of the yttria layer that is less than a thickness of the yttria layer comprised by the bonding interconnect layer.

After the second semiconductor substrate is provided, as shown in fig. 4, a second bonding interconnect sub-layer 18 may be formed on one side of the second semiconductor substrate 17 using a chemical vapor deposition or atomic layer deposition process or the like. The material of the second bond interconnect sublayer 18 comprises yttria. The specific structure of the second bonding interconnection sub-layer 18 may refer to the structural analysis of the first bonding interconnection sub-layer described above, and will not be described herein.

Next, as shown in fig. 5 and 6, the N-type gate-all-around transistor 12 and the second semiconductor substrate 17 are bonded together by the first bonding interconnect sublayer and the second bonding interconnect sublayer using a low temperature bonding process, and the bonding interconnect layer 19 is formed. The bond interconnect layer 19 includes a first bond interconnect sublayer and a second bond interconnect sublayer.

In a practical application, as shown in fig. 5, a composite structure comprising at least the second semiconductor substrate 17 and the second bond interconnect sub-layer may be placed on the first bond interconnect sub-layer from the side of the second bond interconnect sub-layer facing away from the second semiconductor substrate 17. Then, as shown in fig. 6, bonding of the N-type gate-all-around transistor 12 and the second semiconductor substrate 17 is achieved using a low-temperature bonding process. The bonding temperature of the low-temperature bonding process may be set according to actual requirements, so long as the bonding temperature can be applied to the manufacturing method of the semiconductor device provided in the embodiment of the invention.

For example, the bonding temperature of the low temperature bonding process may be 50 ℃ or higher and 150 ℃ or lower. In this case, the bonding temperature of the low-temperature bonding process is within the above range, so that the bonding strength between the N-type gate-all-around transistor and the second semiconductor substrate is prevented from being poor due to the low bonding temperature, and the manufactured semiconductor device is ensured to have strong structural stability. Meanwhile, the influence of the bonding temperature on the crystal quality of the second semiconductor substrate can be prevented, and the high yield of the P-type gate-all-around transistor formed on the second semiconductor substrate is ensured.

In addition, if the buffer layer and the second semiconductor base are formed on the silicon-based semiconductor substrate before the second semiconductor base is provided as described above, it is necessary to remove the silicon-based semiconductor substrate and the buffer layer by a process such as dry etching or wet etching after the low-temperature bonding and before the subsequent operation is performed as shown in fig. 7. The etchant used for removing the silicon-based semiconductor substrate and the buffer layer may be determined according to the materials of the silicon-based semiconductor substrate and the buffer layer, and is not particularly limited herein.

Next, if the buffer layer is formed on the silicon-based semiconductor substrate and the etch stop layer is formed on the buffer layer before the second semiconductor substrate is formed as described above, then, as shown in fig. 7, the etch stop layer needs to be removed by a dry etching process or a wet etching process after the buffer layer is removed and before the P-type gate around transistor is formed on the second semiconductor substrate 17.

Then, as shown in fig. 16, a P-type gate around transistor is formed on the second semiconductor substrate 17. The second semiconductor substrate 17 and the P-type gate-all-around transistor comprise a channel region which contains germanium.

Specifically, the structure and the manufacturing process of the P-type gate-all-around transistor are not particularly limited in the embodiment of the invention. For example, as shown in fig. 8 and 9, the sacrificial layer 22 and the channel layer 23 may be alternately stacked on the second semiconductor substrate 17 using an epitaxial process or the like. Among the sacrificial layer 22 and the channel layer 23 which are alternately stacked, the underlying film layer may be the sacrificial layer 22 or the channel layer 23.

Specifically, in the case where the material of the second semiconductor substrate is the same as that of the channel layer, the film layer located at the bottom layer is a sacrificial layer among the sacrificial layer and the channel layer which are alternately stacked. At this time, the second semiconductor substrate may be doped with impurities, and the conductivity type of the impurities in the second semiconductor substrate is opposite to the conductivity type of the impurities in the source and drain regions, respectively, to suppress parasitic channel leakage.

Alternatively, in the case where the material of the second semiconductor substrate is different from the material of the channel layer, when the material of the second semiconductor substrate is the same as the material of the sacrificial layer, among the sacrificial layer and the channel layer which are alternately stacked, the film layer located at the bottom layer may be the channel layer, and in this case, the second semiconductor substrate may be regarded as the bottom sacrificial layer; alternatively, the underlying film layer may be a sacrificial layer in this case. When the material of the second semiconductor substrate is different from that of the sacrificial layer, the sacrificial layer and the channel layer are alternately laminated, and the film layer at the bottom layer is the sacrificial layer.

Next, a fin may be formed on the second semiconductor substrate using photolithography and etching processes. Then, as shown in fig. 10, a shallow trench isolation structure 25 is formed on the portion of the second semiconductor substrate 17 exposed outside the fin portion by sequentially performing deposition, etching, and the like. The portion of the fin exposed by the shallow trench isolation structure 25 is fin structure 24. Next, as shown in fig. 11, a sacrificial gate 26 and a gate sidewall 27 may be formed across a portion of fin structure 24 using deposition and etching processes. The sacrificial gate material can be polysilicon and other materials; the gate sidewall 27 is at least located on two sides of the sacrificial gate 26 along the length direction, and the material of the gate sidewall 27 may be referred to as above. Next, as shown in fig. 12, under the mask effect of the sacrificial gate 26 and the gate sidewall 27, a wet etching or a dry etching process may be used to remove the portion of the fin structure exposed outside the sacrificial gate 26 and the gate sidewall 27. Next, as shown in fig. 13, a source region 28 and a drain region 29 may be formed on both sides of the remaining portion of the fin structure along the length direction of the sacrificial gate 26 using an epitaxial process or the like. Next, as shown in fig. 14, an interlayer dielectric layer 30 may be formed using a deposition and planarization process or the like. The top of the interlayer dielectric layer 30 is level with the top of the sacrificial gate 26. The material of the interlayer dielectric layer 30 may be referred to as above. Then, as shown in fig. 15, a dry etching process or a wet etching process may be used to remove the sacrificial gate; and the exposed portions of each sacrificial layer are removed so that the remaining portions of the channel layer form channel regions 31. Next, as shown in fig. 16, a gate stack 32 surrounding the channel region may be formed by an atomic layer deposition process or the like, to obtain a P-type gate-all-around transistor.

As shown in fig. 17, after forming the P-type gate-all-around transistor, or during the process of manufacturing the P-type gate-all-around transistor, a connection structure is formed. The specific forming position, connection correspondence, etc. of the connection structure may be referred to the foregoing, and will not be described herein. In addition, the specific forming process of the connection structure is not particularly limited in the embodiment of the present invention.

The beneficial effects of the second aspect and various implementations of the embodiments of the present invention may refer to the beneficial effect analysis in the first aspect and various implementations of the first aspect, which are not described herein.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A semiconductor device, comprising: a first semiconductor substrate having a first semiconductor layer,

an N-type gate-all-around transistor formed on the first semiconductor substrate;

the second semiconductor substrate is formed above the N-type gate-all-around transistor;

a bonding interconnection layer located between the N-type gate-all-around transistor and the second semiconductor substrate; the material of the bonding interconnection layer comprises yttrium oxide, and the second semiconductor substrate and the N-type ring gate transistor are bonded through the bonding interconnection layer;

a P-type gate-all-around transistor formed on the second semiconductor substrate; the second semiconductor substrate and the P-type gate-all-around transistor comprise channel regions which contain germanium.

2. The semiconductor device according to claim 1, wherein the bonding interconnect layer includes a yttria layer and a silicon dioxide layer located on both sides of the yttria layer in a thickness direction of the second semiconductor substrate.

3. The semiconductor device according to claim 2, wherein a thickness of the bonding interconnect layer is 20nm or more and 100nm or less; and/or the number of the groups of groups,

the thickness of the yttrium oxide layer is more than or equal to 10nm and less than or equal to 30nm.

4. The semiconductor device of claim 1, wherein the N-type gate-all-around transistor and the P-type gate-all-around transistor comprise channel regions of a single crystal semiconductor material.

5. The semiconductor device of claim 1, wherein the N-type gate-all-around transistor includes a channel region having a [100] crystal orientation; the P-type gate-all-around transistor includes a channel region having a [110] crystal orientation.

6. The semiconductor device according to any one of claims 1 to 5, wherein the second semiconductor substrate and the P-type gate-all-around transistor include a channel region having a germanium content of 50% or more and 100% or less; and/or the number of the groups of groups,

the second semiconductor substrate is doped with impurities, and the conductivity type of the impurities in the second semiconductor substrate is opposite to that of the impurities in the source region and the drain region included in the P-type gate-all-around transistor; or, the second semiconductor substrate is an intrinsic semiconductor substrate, and a portion of the intrinsic semiconductor substrate located below a channel region included in the P-type gate-all-around transistor is recessed inward.

7. A method of manufacturing a semiconductor device, comprising:

Providing a first semiconductor substrate and a second semiconductor substrate;

sequentially forming an N-type gate-all-around transistor and a first bonding interconnection sub-layer on the first semiconductor substrate; the material of the first bonding interconnection sub-layer comprises yttrium oxide;

forming a second bonding interconnection sub-layer on one side of the second semiconductor substrate; the material of the second bonding interconnect sublayer comprises yttrium oxide;

bonding the N-type gate-all-around transistor and the second semiconductor substrate together through the first bonding interconnection sub-layer and the second bonding interconnection sub-layer by adopting a low-temperature bonding process, and forming a bonding interconnection layer; the bonding interconnection layer comprises the first bonding interconnection sub-layer and the second bonding interconnection sub-layer;

forming a P-type gate-all-around transistor on the second semiconductor substrate; the second semiconductor substrate and the P-type gate-all-around transistor comprise channel regions which contain germanium.

8. The method for manufacturing a semiconductor device according to claim 7, wherein a bonding temperature of the low-temperature bonding process is 50 ℃ or higher and 150 ℃ or lower.

9. The method of manufacturing a semiconductor device according to claim 7, wherein before the providing of the first semiconductor substrate and the second semiconductor substrate, the method further comprises: sequentially forming a buffer layer and the second semiconductor substrate on a silicon-based semiconductor substrate;

The method for manufacturing the semiconductor device further comprises the steps of after the bonding of the N-type gate-all-around transistor and the second semiconductor substrate through the first bonding interconnection sub-layer and the second bonding interconnection sub-layer by adopting a low-temperature bonding process and the formation of the bonding interconnection layer, and before the formation of the P-type gate-all-around transistor on the second semiconductor substrate, the method for manufacturing the semiconductor device further comprises the following steps: and removing the silicon-based semiconductor substrate and the buffer layer.

10. The method of manufacturing a semiconductor device according to claim 9, wherein after forming a buffer layer on a silicon-based semiconductor substrate and before forming the second semiconductor base, the method of manufacturing a semiconductor device further comprises: forming an etching stop layer on the buffer layer; the material of the etching stop layer is different from the material of the second semiconductor substrate;

after the buffer layer is removed, before the P-type gate-all-around transistor is formed on the second semiconductor substrate, the manufacturing method of the semiconductor substrate further comprises the following steps: and removing the etching stop layer.

11. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein an epitaxial process is employed, and the buffer layer is formed sequentially in a high-temperature environment and a low-temperature environment; wherein the temperature in the high-temperature environment is more than or equal to 600 ℃, and the temperature in the low-temperature environment is more than or equal to 400 ℃ and less than or equal to 500 ℃.

12. The method of manufacturing a semiconductor device according to any one of claims 7 to 11, wherein after providing a second semiconductor substrate, before forming a second bonding interconnect sub-layer on one side of the second semiconductor substrate, the method further comprises: and carrying out planarization treatment on one side of the second semiconductor substrate corresponding to the second bonding interconnection sub-layer.