CN113161435A - Thermosensitive detector structure and integration method thereof - Google Patents
Thermosensitive detector structure and integration method thereof Download PDFInfo
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- CN113161435A CN113161435A CN202110260894.8A CN202110260894A CN113161435A CN 113161435 A CN113161435 A CN 113161435A CN 202110260894 A CN202110260894 A CN 202110260894A CN 113161435 A CN113161435 A CN 113161435A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000010354 integration Effects 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 25
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000002407 reforming Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- 230000031700 light absorption Effects 0.000 abstract description 7
- 239000000725 suspension Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 5
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- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000001514 detection method Methods 0.000 description 1
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- 238000009499 grossing Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to a thermosensitive detector structure and an integration method thereof. A thermal detector structure comprising: the substrate is provided with a reading circuit structure, and a dielectric layer, a P-type doped germanium layer, an intrinsic layer and an N-type doped germanium layer are sequentially stacked on the substrate; wherein, the dielectric layer has a cavity structure therein, and the intrinsic layer is made of Ge1‑xSixThe layers and the Ge layers are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, and n is more than or equal to 2. The invention has a P-I-N suspension hollow structure, and light can be reflected to the P-I-N structure in the hollow structure after being absorbed, compared with the light absorption of the traditional detectorThe rate is obviously improved.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a thermosensitive detector structure and an integration method thereof.
Background
The heat-sensitive detector is a device for detecting by using the principle of thermal effect generated by irradiating an object with infrared radiation. This material, also known as a thermistor, has a conductivity that changes with the absorption of infrared photons. In the case of photons, when infrared photons emit light, electrons are obtained by the transition of the valence band to the conduction band. Due to the photon principle, imaging of such detectors provides high resolution in the short wavelength infrared band, but also absorbs longer infrared wavelengths. The influence on the absorption rate of infrared light directly influences the sensitivity, detection rate and other performances of the detector. The existing heat-sensitive detector is limited by low absorption rate of infrared light and has insufficient performance.
Disclosure of Invention
The invention mainly aims to provide a heat-sensitive detector structure, which is provided with a P-I-N suspension hollow structure, light can be reflected to the P-I-N structure in the hollow structure after being absorbed, and the light absorption rate is obviously improved compared with that of the traditional detector.
Another object of the present invention is to provide an integration method of the above-mentioned thermal detector structure, which uses amorphous silicon to form a cavity under the P-I-N stacked structure, and can improve the light absorption rate by utilizing the reflection of light in the cavity after light absorption, thereby improving the electrical performance of the thermal detector.
In order to achieve the above object, the present invention provides the following technical solutions.
A thermal detector structure comprising:
the substrate is provided with a reading circuit structure, and a dielectric layer, a P-type doped germanium layer, an intrinsic layer and an N-type doped germanium layer are sequentially stacked on the substrate;
wherein, the dielectric layer has a cavity structure therein, and the intrinsic layer is made of Ge1-xSixThe layers and the Ge layers are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, and n is more than or equal to 2.
A method of integrating a thermal-type detector structure, comprising:
providing a support substrate: providing a support substrate having a readout circuitry structure;
reforming a support substrate: sequentially stacking a first dielectric layer and an amorphous silicon layer on the surface of the supporting substrate close to the reading circuit structure; photoetching and etching the amorphous silicon layer to enable the amorphous silicon layer to only cover part of the surface of the first dielectric layer, then depositing a second dielectric layer, wherein the second dielectric layer is bordered by the first dielectric layer and wraps the amorphous silicon layer;
providing a sacrificial substrate: the sacrificial substrate is formed by sequentially stacking a back substrate, an intrinsic layer and a P-type doped germanium layer, wherein the intrinsic layer is formed by Ge1-xSixThe layer and the Ge layer are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, and n is more than or equal to 2;
bonding: after the second dielectric layer is deposited, the read-out circuit structure and the P-type doped germanium layer in the supporting substrate are respectively used as bonding surfaces, and the supporting substrate and the sacrificial substrate are bonded;
and (3) a post-bonding process:
removing the back substrate; forming an N-type doped germanium layer on the surface of the intrinsic layer;
and etching to remove the amorphous silicon layer, so that a cavity structure is formed between the second dielectric layer and the first dielectric layer.
Compared with the prior art, the invention achieves the following technical effects.
(1) According to the invention, the amorphous silicon is used for forming the cavity below the P-I-N stacked structure, so that the light absorption rate can be improved by utilizing the reflection of the light absorbed in the cavity, and the electrical property of the thermosensitive detector is improved.
(2) The invention bonds the substrate which is also manufactured into a part of the detector structure in the substrate of the reading circuit structure, simplifies the integration flow, improves the integration level, is beneficial to reducing the system size, improving the system performance (reducing the length of the interconnection line) and the like.
(3) The intrinsic layer adopts Ge1-xSixThe layers and the Ge layers are alternately stacked, so that the quantum effect is favorably improved, and the photoelectric conversion efficiency is enhanced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a schematic diagram of an integrated structure of a detector provided by the present invention;
fig. 2 to 9 are schematic structural diagrams obtained in steps of the detector integration method provided in embodiment 1.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The thermal-type detector shown in fig. 1 includes a substrate 101 having a read-out circuit structure (ROIC) on which a dielectric layer, a P-type doped germanium layer 203, an intrinsic layer 202, and an N-type doped germanium layer 204 are sequentially stacked.
The dielectric layer has a cavity 105 therein, and may be formed by compounding multiple layers of the same or different materials, and usually employs silicon oxide.
The intrinsic layer 202 is made of Ge1-xSixThe layers and the Ge layers are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, and n is more than or equal to 2. In the intrinsic layer, Ge1-xSixThe tensile stress layer is favorable for improving the quantum effect and enhancing the photoelectric conversion efficiency. Meanwhile, the material contacting the P-type doped germanium layer or the N-type doped germanium layer may be a Ge layer or Ge1-ySiyAnd (3) a layer.
In addition, the number of alternation can be arbitrarily adjusted according to the device requirements, and the intrinsic layer may have a multilayer structure of 2 layers, 3 layers, 4 layers, etc., including but not limited to the intrinsic layer structure listed in table 1 below.
TABLE 1
The thermal detector shown in fig. 1 has various integration methods, such as preparing discrete devices first and then integrating, but because of the problems of inaccurate alignment, the present invention provides a method for manufacturing a photonic device after integrating, and the basic flow is as follows.
Preparing a substrate:
and providing a sacrificial substrate and a supporting substrate with a readout circuit structure, wherein the sacrificial substrate is formed by sequentially stacking a back substrate, an intrinsic layer and a P-type doped germanium layer.
Reforming a support substrate:
sequentially stacking a first dielectric layer and an amorphous silicon layer on the surface of the supporting substrate close to the reading circuit structure;
and photoetching and etching the amorphous silicon layer to enable the amorphous silicon layer to only cover part of the surface of the first dielectric layer, and then depositing a second dielectric layer, wherein the second dielectric layer is adjacent to the first dielectric layer and wraps the amorphous silicon layer.
Bonding:
after the second dielectric layer is deposited, the read-out circuit structure and the P-type doped germanium layer in the supporting substrate are respectively used as bonding surfaces, and the supporting substrate and the sacrificial substrate are bonded;
and (3) bonding process:
removing the back substrate;
forming an N-type doped germanium layer on the surface of the intrinsic layer;
and etching to remove the amorphous silicon layer, so that a cavity structure is formed between the second dielectric layer and the first dielectric layer.
After the above procedure is completed, a specific detector structure may be fabricated in a P-I-N stack structure, and then the readout circuitry structure and the detector structure are interconnected.
According to the method provided by the invention, firstly, the amorphous silicon is used for forming the cavity below the P-I-N stacked structure, and the light absorption rate can be improved by utilizing the reflection in the cavity after light absorption, so that the electrical property of the thermosensitive detector is improved.
In addition, the invention simplifies the integration flow and improves the integration level, for example, the integration discrete devices have the problems of complexity, low integration level and the like in interconnection; another aspect is to fabricate the probe structure after integration, bypassing the problem of precise alignment (mainly referring to alignment of the electronic structure and the probe structure).
The method is suitable for any vertical type (indicating the arrangement direction of a PN structure) photoelectric device which needs to be integrated on a single silicon-based chip, so that no specific requirements are made on a reading circuit structure and a detector structure.
The supporting substrate and the sacrificial substrate targeted by the above method are mainly silicon-based substrates (but the invention is not limited thereto, and is also applicable to substrates of other semiconductor materials), but there is no specific requirement on the crystal orientation, the presence or absence of a buried oxide layer, and the like, and the supporting substrate and the sacrificial substrate may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), silicon germanium, and the like.
The method has no specific requirements on the first dielectric layer and the second dielectric layer. The dielectric layers mainly play a role in isolation, and the first dielectric layer and the second dielectric layer can be made of common silicon oxide. The first dielectric layer and the second dielectric layer can be respectively and independently selected from materials. The deposition method of the first dielectric layer and the second dielectric layer is also arbitrary, and includes but not limited to LPCVD, RTCVD, PECVD, thermal oxidation method, or plasma chemical vapor deposition method.
The method of forming the stacked intrinsic layers is also arbitrary and includes, but is not limited to, LPCVD, RTCVD, PECVD or evaporation, epitaxial growth, and the like.
The method of forming the N-type doped germanium layer is arbitrary and the N-doped germanium may be formed epitaxially or by implantation.
The above method has no particular requirement on the shape of the cavity, but is generally determined by the shape of the etched amorphous silicon. Therefore, it is necessary to define a good shape when lithographically etching amorphous silicon according to product requirements.
In addition, before bonding, the second dielectric layer can be subjected to planarization treatment such as chemical mechanical polishing.
The means for removing the back substrate after bonding is not limited, and one or more of grinding and polishing, wet etching, dry etching and CMP can be used for removing.
A preferred embodiment of the present invention is as follows.
Embodiment 1 a structure of a heat sensitive detector
Manufacturing a support substrate:
a substrate 101 having a readout circuitry structure is provided and then a first silicon oxide layer 102 is deposited on the surface of the readout circuitry structure resulting in the structure shown in fig. 2.
An amorphous silicon layer 103 is deposited on the surface of the first silicon oxide layer 102 resulting in the structure shown in fig. 3.
The amorphous silicon layer 103 is subjected to photolithography and etching, and a portion of amorphous silicon is removed to cover only a portion of the surface of the first silicon oxide layer 103, so as to obtain the structure shown in fig. 4.
A second silicon oxide layer 104 is deposited, the second silicon oxide layer 104 borders the first silicon oxide layer 102 and wraps the amorphous silicon layer to obtain the structure shown in fig. 5, and a planarization process (e.g., CMP) is performed.
Manufacturing a sacrificial substrate:
sequential deposition of Ge on a silicon substrate 2011-xSixlayers/Ge layers are alternately stacked intrinsic layer 202, P-type doped germanium layer 203 resulting in the structure shown in fig. 6, followed by a surface smoothing process. Wherein Ge is in the intrinsic layer1-xSnxlayer/Ge1-ySiyThe number of times the layers are alternately repeated is arbitrary.
Bonding:
and bonding the support substrate and the sacrificial substrate by using the second silicon dioxide layer 104 and the P-type doped germanium layer 203 as bonding surfaces to form the structure shown in fig. 7.
The silicon substrate 201 is removed to form the structure shown in fig. 8.
An N-type doped germanium layer 204 is formed on the surface of the intrinsic layer to form the structure shown in fig. 9.
And etching to remove the amorphous silicon layer 103, so that a cavity 105 is formed between the second silicon oxide layer 104 and the first silicon oxide layer 102, and the structure shown in fig. 1 is formed.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (9)
1. A structure for a heat-sensitive detector, comprising:
the substrate is provided with a reading circuit structure, and a dielectric layer, a P-type doped germanium layer, an intrinsic layer and an N-type doped germanium layer are sequentially stacked on the substrate;
wherein, the dielectric layer has a cavity structure therein, and the intrinsic layer is made of Ge1-xSixThe n-layer structure formed by alternately stacking the layers and the Ge layer, x is more than 0 and less than or equal to 0.3,n≥2。
2. a thermal detector structure according to claim 1, wherein said dielectric layer is a silicon oxide layer.
3. A method of integrating a thermal detector structure, comprising:
providing a support substrate: providing a support substrate having a readout circuitry structure;
reforming a support substrate: sequentially stacking a first dielectric layer and an amorphous silicon layer on the surface of the supporting substrate close to the reading circuit structure; photoetching and etching the amorphous silicon layer to enable the amorphous silicon layer to only cover part of the surface of the first dielectric layer, then depositing a second dielectric layer, wherein the second dielectric layer is bordered by the first dielectric layer and wraps the amorphous silicon layer;
providing a sacrificial substrate: the sacrificial substrate is formed by sequentially stacking a back substrate, an intrinsic layer and a P-type doped germanium layer, wherein the intrinsic layer is formed by Ge1-xSixThe layer and the Ge layer are alternately stacked to form an n-layer structure, x is more than 0 and less than or equal to 0.3, and n is more than or equal to 2;
bonding: after the second dielectric layer is deposited, the read-out circuit structure and the P-type doped germanium layer in the supporting substrate are respectively used as bonding surfaces, and the supporting substrate and the sacrificial substrate are bonded;
and (3) a post-bonding process:
removing the back substrate; forming an N-type doped germanium layer on the surface of the intrinsic layer;
and etching to remove the amorphous silicon layer, so that a cavity structure is formed between the second dielectric layer and the first dielectric layer.
4. The integration method of claim 3, wherein the second dielectric layer and the first dielectric layer are both silicon oxide layers.
5. The integration method of claim 3, wherein the back substrate is silicon.
6. The integrated method of claim 3, wherein the first dielectric layer and the second dielectric layer are formed using a plasma chemical vapor deposition process.
7. The integration method of claim 3, wherein the second dielectric layer is further subjected to a chemical mechanical polishing process prior to bonding.
8. The integration method of claim 3, wherein the N-type doped germanium layer is formed using epitaxy.
9. The integrated method of claim 3, wherein the back substrate is removed using at least one of lapping, wet etching, dry etching, and chemical mechanical polishing.
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