JP2012142366A - Semiconductor device manufacturing method end support substrate for epitaxial growth - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method and a support substrate for epitaxial growth, which allow a semiconductor device to be manufactured at excellent yield by addition of appropriate treatment to the support substrate even if the support substrate has an intermediate layer partially being exposed.SOLUTION: A present semiconductor device manufacturing method comprises: a step of forming a support substrate 2, which includes a base substrate 10 capable of achieving epitaxial growth of at least one layer of a group-III nitride semiconductor layer 40, an intermediate layer 20 arranged on an entire surface of the base substrate 10 and a GaN layer 30a arranged on a part of the intermediate layer 20, and in which the GaN layer 30a and a part of the intermediate layer 20 is exposed; a step of exposing a part of the base substrate 10 by selectively removing exposed portions 20p, 20q, 20r of the intermediate layer 20 of the support substrate 2; and a step of achieving epitaxial growth of the group-III nitride semiconductor layer on the GaN layer 30a.

Description

  The present invention relates to a method of manufacturing a semiconductor device using a support substrate in which a GaN layer is laminated with an intermediate layer interposed in a base substrate, and a support substrate for epitaxial growth.

  Semiconductor devices using group III nitride semiconductors are formed by various methods. One method is a method of epitaxially growing at least one group III nitride semiconductor layer on a group III nitride semiconductor substrate. However, in this method, since the group III nitride semiconductor substrate is very expensive, the resulting semiconductor device is also very expensive.

  For this reason, there is a method in which a group III nitride semiconductor layer is epitaxially grown on a group III nitride semiconductor layer of a support substrate in which a group III nitride semiconductor layer is stacked on a base substrate having a different chemical composition from that of a group III nitride semiconductor. It is preferably used.

  For example, Japanese Patent Laying-Open No. 2006-210660 (Patent Document 1) discloses a method of implanting ions in the vicinity of the surface of a first nitride semiconductor substrate as a method for manufacturing a stacked semiconductor substrate, and the first nitride. A step of superimposing the surface side of the semiconductor substrate on the second substrate, a step of heat-treating the two superposed substrates, and a majority of the first nitride semiconductor substrate with the ion-implanted layer as a boundary. A manufacturing method including a step of peeling off from the second nitride semiconductor substrate is disclosed.

Japanese Patent Laying-Open No. 2008-300562 (Patent Document 2) is a substrate in which a group III nitride semiconductor substrate and a base substrate are bonded to each other as a group III nitride semiconductor layer bonded substrate. The difference between the thermal expansion coefficient of the physical semiconductor layer and the thermal expansion coefficient of the base substrate is as small as 4.5 × 10 ⁻⁶ K ⁻¹ or less, and the thermal conductivity of the base substrate is 50 W · m ⁻¹ · K ⁻¹ or more. A high bonded substrate is disclosed. In addition, a semiconductor device including at least one group III nitride layer formed on the group III nitride semiconductor layer bonded substrate is disclosed.

  Japanese Patent Laying-Open No. 2010-165927 (Patent Document 3) discloses a transparent substrate that is transparent to light having a wavelength of 400 nm or more and 600 nm or less as a substrate for a light emitting element, and is bonded to one main surface of the transparent substrate. If the thermal expansion coefficient of the transparent substrate in the direction perpendicular to the main surface of the transparent substrate is α1, and the thermal expansion coefficient of the nitride compound semiconductor thin film is α2, then (α1 A substrate having a small value of −α2) / α2 of −0.5 or more and 1.0 or less is disclosed.

JP 2006-210660 A JP 2008-300562 A JP 2010-165927 A

  All of the supporting substrates disclosed in the above-mentioned JP-A-2006-210660 (Patent Document 1), JP-A-2008-300562 (Patent Document 2) and JP-A-2010-165927 (Patent Document 3) The base substrate and the group III nitride semiconductor layer are directly bonded together, and the bonding strength between the base substrate and the group III nitride semiconductor layer may not always be sufficient depending on the type of the base substrate.

  Therefore, in order to increase the bonding strength between the base substrate and the group III nitride semiconductor layer, a support substrate in which the base substrate and the group III nitride semiconductor layer are bonded with an intermediate layer interposed therebetween is being studied. is there.

  However, when a group III nitride semiconductor layer is epitaxially grown on a support substrate that is laminated with an intermediate layer interposed between a base substrate and a group III nitride semiconductor layer obtained in actual actual manufacturing, abnormal growth occurs. As a result, the yield of semiconductor devices is reduced.

  As a result of intensive investigation and research on the cause of the above problems, the present inventors have found that a part of the group III nitride semiconductor layer on the base substrate is covered and a part of the intermediate layer is exposed. It has been found that various abnormal growths are caused during the epitaxial growth of group nitride semiconductor layers. Based on the above knowledge, the present invention provides a semiconductor device manufacturing method that can manufacture a semiconductor device with a high yield by adding an appropriate treatment to the support substrate in which a part of the intermediate layer is exposed. It is an object to provide a method and a support substrate for epitaxial growth.

  The present invention provides a base substrate capable of epitaxially growing at least one group III nitride semiconductor layer, an intermediate layer disposed entirely on the base substrate, and a GaN layer partially disposed on the intermediate layer Forming a support substrate in which the GaN layer and a portion of the intermediate layer are exposed, and selectively removing the portion of the support substrate in which the intermediate layer is exposed, thereby And a step of epitaxially growing a group III nitride semiconductor layer on the GaN layer and on the portion where the underlying substrate is exposed.

In the method for manufacturing a semiconductor device according to the present invention, the method of selectively removing the portion where the intermediate layer is exposed can be at least one of wet etching and dry etching. Further, by using the GaN layer itself disposed on the intermediate layer as a mask for wet etching and dry etching, the increment of the manufacturing process is minimized, and the portion where the intermediate layer to be removed is exposed is excessive. Can be removed without shortage. Further, the base substrate can be any one selected from the group consisting of a GaN substrate, a sapphire substrate, a Si substrate, a SiC substrate, a GaAs substrate, and an InP substrate. Further, the intermediate layer can include any one selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Si and SiON. The intermediate layer can contain at least one selected from the group consisting of Sn, Zn, Ti, Cr, Ni, Ga, In, Sb, W, and Mo.

  The present invention also provides a base substrate capable of epitaxially growing at least one group III nitride semiconductor layer, an intermediate layer partially disposed on the base substrate, and an entire surface disposed on the intermediate layer. It is a support substrate for epitaxial growth including a GaN layer and exposing the GaN layer and a part of the base substrate.

  ADVANTAGE OF THE INVENTION According to this invention, even if it is a support substrate from which a part of intermediate | middle layer is exposed, the semiconductor device manufacturing method and epitaxial growth for which a semiconductor device can be manufactured with a sufficient yield by adding an appropriate process to it The supporting substrate can be provided.

It is a schematic sectional drawing which shows the ideal manufacturing method of a semiconductor device. Here, (A) shows the preparation process of the base substrate and the GaN substrate, the formation process of the intermediate layer and the ion implantation process, (B) shows the bonding process, and (C) shows the support substrate by separating the GaN substrate. (D) shows the growth process of a group III nitride semiconductor layer. It is a schematic sectional drawing which shows the problem at the time of manufacturing a support substrate in the manufacturing method of an actual semiconductor device. Here, (A) shows the preparation process of the base substrate and the GaN substrate, the formation process of the intermediate layer and the ion implantation process, (B) shows the bonding process, and (C) shows the support substrate by separating the GaN substrate. A formation process is shown. It is a schematic sectional drawing which shows the problem at the time of growing a group III nitride semiconductor layer on a support substrate in the manufacturing method of an actual semiconductor device. Here, (A) shows a supporting substrate, and (B) shows a growth process of a group III nitride semiconductor layer on the supporting substrate. It is a schematic sectional drawing which shows an example of the manufacturing method of the semiconductor device concerning this invention. Here, (A) shows the formation process of the support substrate, (B) shows the selective removal process of the portion where the intermediate layer of the support substrate is exposed, and (C) shows the group III nitride on the support substrate. The growth process of a semiconductor layer is shown, (D) shows the formation process of a semiconductor device. It is a schematic sectional drawing which shows an example of the semiconductor device obtained by the manufacturing method of the semiconductor device concerning this invention. It is a schematic sectional drawing which shows another example of the semiconductor device obtained by the manufacturing method of the semiconductor device concerning this invention.

[Embodiment 1]
Referring to FIG. 4, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes a base substrate 10 on which at least one group III nitride semiconductor layer 40 can be epitaxially grown, and an entire surface on the base substrate 10. The support substrate 2 is formed, which includes the intermediate layer 20 that is disposed on the substrate and the GaN layer 30a that is partially disposed on the intermediate layer 20, and the GaN layer 30a and a part of the intermediate layer 20 are exposed. The step (FIG. 4A) and the step of exposing part of the base substrate 10 by selectively removing the portions 20p, 20q, and 20r where the intermediate layer 20 of the support substrate 2 is exposed (FIG. 4). (B)) and a step (FIG. 4C) of epitaxially growing the group III nitride semiconductor layer 40 on the GaN layer 30a and the portions 10p, 10q, 10r where the base substrate 10 is exposed. . With this manufacturing method, the group III nitride semiconductor layer can be uniformly grown on the portion of the support substrate where the GaN layer and the base substrate are exposed, and semiconductor devices can be manufactured with high yield.

  Hereinafter, the background and significance of the present invention will be described in detail. For example, referring to FIG. 1, a semiconductor device manufacturing method using a support substrate in which a base substrate and a GaN layer are bonded with an intermediate layer interposed therebetween is ideally performed as follows.

  Referring to FIG. 1A, first, a base substrate 10 and a GaN substrate 30 as a donor substrate for forming a GaN layer are prepared (preparing step of the base substrate and the GaN substrate). Next, the intermediate layer 20a is formed on the base substrate 10, and the intermediate layer 20b is formed on the GaN substrate 30 (intermediate layer forming step). Next, ions are implanted from the side of the GaN substrate 30 where the intermediate layer 20b is formed (ion implantation step). Here, ions are implanted from the surface of the GaN substrate 30 into the ion implantation region 30 i which is a surface having a depth D.

  Referring to FIG. 1B, next, the intermediate layer 20a formed on the base substrate 10 and the intermediate layer 20b formed on the GaN substrate 30 are bonded together (bonding step). Here, the intermediate layer 20a and the intermediate layer 20b are preferably layers having the same or similar chemical properties, and more preferably layers having the same or similar chemical composition, from the viewpoint of increasing the bonding strength between them. When the intermediate layer 20a and the intermediate layer 20b have the same chemical composition, the intermediate layer 20 is integrated. Next, the ion implantation region 30i is embrittled by activating the implanted ions by applying heat to the base substrate 10, the intermediate layer 20, and the GaN substrate 30 to form voids.

Referring to FIG. 1C, next, stress is applied between base substrate 10 and GaN substrate 30 to separate GaN substrate 30 into GaN layer 30a and the remaining GaN substrate 30b in ion implantation region 30i. Accordingly, the base substrate 10, intermediate layer 20 and the thickness T supporting substrate 1 GaN layer are stacked in this order of _D are obtained (step of forming the support substrate due to the GaN substrate separation). Here, the thickness T _D of the GaN layer 30 a is substantially the same as the depth D of ion implantation in the GaN substrate 30.

  Referring to FIG. 1D, next, one or more group III nitride semiconductor layers 40 are epitaxially grown on the GaN layer 30a of the support substrate 1 (group III nitride semiconductor layer growth step). A semiconductor device is obtained by forming electrodes on the laminated wafer 4 thus obtained.

  However, it is actually very difficult to perform the ideal process as shown in FIGS. 1 (A) to 1 (D). 2 and 3, there are actually the following problems.

  Referring to FIG. 2A, through the preparation process of the base substrate 10 and the GaN substrate 30, the formation process of the intermediate layers 20a and 20b, the ion implantation process and before the bonding process, the base substrate 10 and In some cases, pits P derived from crystal defects and / or poor polishing may occur on at least one of the surfaces of the GaN substrate 30. Further, the intermediate layers 20a and 20b formed on the base substrate 10 and the GaN substrate 30 have non-uniform thicknesses, poor polishing of the intermediate layers 20a and 20b, and damage during ion implantation. A pit Q may occur. Further, foreign matter R such as dust may be mixed on the intermediate layers 20a and 20b.

Referring to FIG. 2B, when any of the pits P and Q and the foreign matter R is present in the intermediate layers 20a and 20b, the intermediate layer 20a formed on the base substrate 10 and the GaN substrate 30 are formed. When the intermediate layer 20b formed on the intermediate layer 20b is bonded together, the voids V _P and V derived from the pits P and Q and the foreign matter R are formed in the intermediate layer 20 formed by integrating the intermediate layer 20a and the intermediate layer 20b. _Q, V _R is generated. Such gap portion in the intermediate layer 20 V _P, V _Q, when V _R occurs, even if heat is applied to the base substrate 10 and the GaN substrate 30, the intermediate layer 20 of the ion implanted region 30i in the GaN substrate 30 Embrittlement of portions near the generated void portions V _P , V _Q , and V _R becomes insufficient. Here, the intermediate layer 20 used for bonding the base substrate 10 and the GaN substrate is not particularly limited, but generally, a layer in which the group III nitride semiconductor layer is difficult to epitaxially grow thereon is used. .

2 (B) and 2 (C) and FIG. 3 (A), when stress is applied between the base substrate 10 and the GaN substrate 30 to separate them, the ion implantation region 30i of the GaN substrate 30 is separated. Among these, in the vicinity 30ii of the voids V _P , V _Q , and V _R generated in the intermediate layer 20, the embrittlement is insufficient and the ion implantation region cannot be separated. In these parts, in the form of applied stress void portion V _P, a portion of the intermediate layer 20c by concentrating on the outer peripheral portion of the V _R remains in the remaining GaN substrate 30b side for the separation of the GaN substrate 30 Separation (see separation anomalous portions W _P and W _R in FIG. 2C), and separation at the interface between the intermediate layer 20 and the GaN substrate 30 is low (see FIG. 2 ( phenomena such as separation refers to the abnormal part W _Q) of C) occurs. In this way, the support substrate 2 having the portions 20p, 20q, and 20r where the intermediate layer 20 is exposed is obtained. Here, in the support substrate 2, a part of the intermediate layer 20 is exposed and a part where the intermediate layer 20 is exposed is a scanning electron combined with observation with an optical microscope and energy dispersive X-ray analysis. This can be confirmed by microscopic observation (hereinafter referred to as SEM-EDX), spectroscopic ellipsometry, or the like.

  Referring to FIG. 3B, a group III nitride semiconductor layer is epitaxially grown on the support substrate 2 where a part of the GaN layer 30a and the intermediate layer 20 obtained as described above are exposed. Then, the following problems occur. A group III nitride semiconductor layer 40 is epitaxially grown on the GaN layer 30a. At this time, the problem is that the intermediate layer 20 is not in a surface state suitable for epitaxial growth. A group III nitride semiconductor layer 40a having a desired thickness is obtained on a portion of the GaN layer 30a where the intermediate layer 20 is not exposed in the vicinity. On the other hand, the gas that has not been consumed on the intermediate layer 20 is diffused on the portion of the GaN layer 30a where the intermediate layer 20 is exposed in the vicinity, which is extremely smaller than the desired thickness. A thick group III nitride semiconductor layer 40b is formed. Further, in the portions 20p, 20q, and 20r where the intermediate layer 20 is exposed, the group III nitride semiconductor layer is not epitaxially grown. When the exposed portion of the intermediate layer 20 is small (see the portion 20q where the intermediate layer 20 is exposed shown in FIG. 3B), the group III nitride semiconductor layer is formed on the exposed portion 20q. Does not grow. When the exposed portion of the intermediate layer 20 is larger than a certain degree (see the portions 20p and 20r where the intermediate layer 20 is exposed shown in FIG. 3B), the intermediate layer 20 is deposited on the exposed portions 20p and 20r. A group III nitride polycrystal 44 grows with the group III nitride microcrystal as a nucleus. Here, the thickness of the group III nitride polycrystal 44 may reach twice or more the thickness of the group III nitride semiconductor layer 40 in some cases. That is, in the portions 20p, 20q, 20r where the intermediate layer 20 is exposed and the portions near the intermediate layer of the Ga layer 30a, the group III nitride semiconductor having the designed crystal orientation, thickness, and structure Since a layer cannot be obtained, a semiconductor device having desired characteristics cannot be manufactured. In addition, the above-described defective portion may cause unexpected conduction failure, light emission failure, and other problems in the manufacturing process (contact mask destruction and bonding inhibition). As a result, the yield of semiconductor devices decreases.

  In FIGS. 1 and 2 and FIG. 3 to be described later, for the convenience of explanation, the defect portion where the intermediate layer is exposed in the formation of the support substrate is emphasized. That is, even in the actual formation of the support substrate, the defect portion is few and the GaN layer is formed on the intermediate layer, and at least one group III nitride semiconductor layer is epitaxially grown on the semiconductor device. The portion that can be formed is sufficiently secured.

  The semiconductor device manufacturing method of this embodiment is for solving the above-mentioned problems in the conventional manufacturing method, and will be described in detail below with reference to FIG.

  Referring to FIG. 4A, in the semiconductor device manufacturing method of the present embodiment, at least one group III nitride semiconductor layer can be epitaxially grown, and the substrate 10 is entirely formed on the substrate 10. Forming a support substrate 2 including the disposed intermediate layer 20 and a GaN layer 30a partially disposed on the intermediate layer 20 and exposing the GaN layer 30a and a part of the intermediate layer 20; Prepare. The step of forming the support substrate 2 is specifically as described in FIGS. 2 (A) to 2 (C).

  Referring to FIG. 4A, base substrate 10 used in the step of forming support substrate 2 in the manufacturing method of the present embodiment is a substrate on which at least one group III nitride semiconductor layer can be epitaxially grown. is there. This is because the group III nitride semiconductor layer 40 is epitaxially grown on the base substrate 10 exposed in the support substrate 3 obtained in the subsequent process (FIGS. 4B to 4C), thereby forming the GaN layer 30a on the substrate. This is to prevent abnormal growth from occurring on other parts. Such a base substrate 10 is not particularly limited, but from the viewpoint of epitaxially growing a group III nitride semiconductor layer 40 with high crystal quality, a GaN substrate, a sapphire substrate, a Si substrate, a SiC substrate, a GaAs substrate, and an InP substrate. The base substrate 10 containing any one selected from the group consisting of

Further, the intermediate layer 20 used in the step of forming the support substrate 2 of the manufacturing method of the present embodiment is not particularly limited as long as the bonding strength between the base substrate 10 and the GaN layer 30a is high. In FIG. 4B, the portions 20p, 20q, and 20r where the intermediate layer 20 is exposed can be selectively removed by either wet etching or dry etching using the GaN layer as a mask. Is preferred. From such a viewpoint, the intermediate layer 20 preferably includes any one selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Si and SiON, and includes an SiO ₂ layer, an Si ₃ N ₄ layer, an Si layer, an SiON layer, and More preferably, it is one selected from the group consisting of these composite layers. From the same viewpoint, the intermediate layer 20 preferably includes at least one selected from the group consisting of Sn, Zn, Ti, Cr, Ni, Ga, In, Sb, W, and Mo. Metal layers of Ti, Cr, Ni, Ga, In, Sb, W and Mo, alloy layers of these metals, composite layers of these metals, oxide layers of these metals (for example, ITO (indium tin oxide)) Layer, IZO (indium zinc oxide) layer, ATO (antimony tin oxide) layer, NiO layer, etc.) and nitride layers (for example, TiN layer, etc.) of these metals. Is more preferable.

  Referring to FIG. 4B, in the method of manufacturing a semiconductor device of this embodiment, the base substrate is selectively removed by removing portions 20p, 20q, and 20r where the intermediate layer 20 of the support substrate 2 is exposed. A step of exposing a part of 10. Through this process, the portions 20p, 20q, and 20r where the intermediate layer 20 of the support substrate 2 is exposed are selectively removed, and the base substrate 10 and the intermediate layer 20 partially disposed on the base substrate 10 are provided. The epitaxial growth support substrate 3 is obtained, which includes the GaN layer 30a disposed on the entire surface of the intermediate layer 20 and in which the GaN layer 30a and a part of the base substrate 10 are exposed. Since the support substrate 3 for epitaxial growth thus obtained has no portion where the intermediate layer 20 is exposed, abnormal growth as shown in FIG. 3B occurs when the group III nitride semiconductor layer is grown. First, at least one group III nitride semiconductor layer 40 can be epitaxially grown on the GaN layer 30a of the support substrate 3 and the portions 10p, 10q, and 10r where the base substrate 10 is exposed. Here, in the support substrate 3 for epitaxial growth, it can be confirmed by an optical microscope, SEM-EDX, spectroscopic ellipsometry, and the like that the intermediate layer 20 is not exposed.

  Here, the method for selectively removing the portions 20p, 20q, and 20r where the intermediate layer 20 of the support substrate 2 is exposed is not particularly limited, but at least wet etching and dry etching using the GaN layer 30a as a mask. By setting it as either, a manufacturing process can be simplified very much. That is, it is preferable to use an etching method that selectively removes only the portions 20p, 20q, and 20r where the intermediate layer 20 is exposed without etching the GaN layer 30a.

For example, when an SiO ₂ layer, Si ₃ N ₄ layer, Si layer, SiON layer, Ti layer, TiN layer or the like is used as the intermediate layer 20, wet etching using BHF (buffered hydrofluoric acid), CF ₄ gas, etc. Dry etching such as RIE (Reactive Ion Etching) using is preferably used. Further, when a Cr layer, Ni layer, Ga layer, In layer, or the like is used as the intermediate layer 20, dry etching such as wet etching using hydrochloric acid or RIE using Cl ₂ gas or the like is preferably used. When an ITO layer or the like is used as the intermediate layer 20, dry etching such as wet etching using BHF or RIE using Cl ₂ gas is preferably used.

  Referring to FIG. 4C, in the semiconductor device manufacturing method of the present embodiment, on the GaN layer 30a of the support substrate 3 for epitaxial growth and on the portions 10p, 10q, and 10r where the base substrate 10 is exposed, A step of epitaxially growing the group III nitride semiconductor layer 40; Through this process, at least one group III nitride semiconductor layer 40 can be epitaxially grown on the GaN layer 30a of the support substrate 3 and the portions 10p, 10q, and 10r where the base substrate 10 is exposed. As a result, the above-described abnormal growth is suppressed by uniformly consuming the source gas for forming the group III nitride semiconductor layer on the GaN layer 30a of the support substrate 3 and the portion where the base substrate 10 is exposed. Therefore, a uniform group III nitride semiconductor layer 40 is obtained on the GaN layer 30a. In addition, since the portions 10p, 10q, and 10r where the base substrate 10 is exposed are surfaces suitable for epitaxial growth, the group III nitride semiconductor layer 40 is also epitaxially grown in a film shape on these portions. Formation of a polycrystal can be suppressed. As a result, the yield of semiconductor devices can be increased.

  The method for epitaxially growing at least one group III nitride semiconductor layer 40 is not particularly limited. For example, MOCVD (metal organic chemical vapor deposition) method, HVPE (hydride vapor phase epitaxy) method, MBE (molecular beam growth). ) Method, gas phase method such as sublimation method, liquid phase method such as flux method, high nitrogen pressure solution method and the like are used. From the viewpoint of easy control of the thickness of the group III nitride semiconductor layer 40, the MOCVD method is preferable.

There is no particular limitation on at least one group III nitride semiconductor layer 40 epitaxially grown on the GaN layer 30a of the support substrate 3 for epitaxial growth and on the portions 10p, 10q, 10r where the base substrate 10 is exposed. For example, the support substrate The n-type Al _0.05 Ga _0.95 N layer 40na, the n-type GaN layer 40ng, and the n-type In _0.05 Ga _0.95 N layer 40ni in this order from the three GaN layers 30a and the portions 10p, 10q, 10r where the base substrate 10 is exposed. An n-type group III nitride semiconductor layer 40n composed of, a light emitting layer 40e having a multiple quantum well structure composed of an In _0.18 Ga _0.82 N well layer and a GaN barrier layer, and a p-type Al _0.2 Ga _0.8 N layer 40pa And a p-type group III nitride semiconductor layer 40p composed of a p-type GaN layer 40pg.

  Referring to FIG. 4D, in the method of manufacturing a semiconductor device of this embodiment, an electrode (p) is formed on a laminated wafer 4 in which at least one group III nitride semiconductor layer 40 is formed on a support substrate 3 for epitaxial growth. A step of forming the side electrode 50p and the n-side electrode 50n) (electrode forming step) and a step of dividing the laminated wafer 4 on which the electrodes are formed to form chips (chip forming step) can be further provided. Thus, the semiconductor devices 5A and 5B are obtained (semiconductor device forming step).

Specifically, referring to FIGS. 4C and 4D, at least one group III nitride semiconductor layer 40 is sequentially formed on the GaN layer 30a of the support substrate 3 for epitaxial growth as an n-type Al _0.05. It is composed of an n-type group III nitride semiconductor layer 40n composed of a Ga _0.95 N layer 40na, an n-type GaN layer 40ng and an n-type In _0.05 Ga _0.95 N layer 40ni, an In _0.18 Ga _0.82 N well layer and a GaN barrier layer. In the laminated wafer portion 4t in which the light emitting layer 40e having a multiple quantum well structure and the p-type group III nitride semiconductor layer 40p composed of the p-type Al _0.2 Ga _0.8 N layer 40pa and the p-type GaN layer 40pg are formed. When at least one of the base substrate 10 and the intermediate layer 20 is insulative, the p-type GaN layer 4 of the group III nitride semiconductor layer 40 is obtained by mesa etching. Part of each of 0 pg, p-type Al _0.2 Ga _0.8 N layer 40pa, light emitting layer 40e, and n-type In _0.05 Ga _0.95 N layer 40ni is removed, and a part of n-type GaN layer 40ng is exposed to form p-type By forming the p-side electrode 50p on the GaN layer 40pg and forming the n-side electrode 50n on the portion where the n-type GaN layer 40ng is exposed, the semiconductor device 5A having a lateral structure can be formed. The method for forming the p-side electrode 50p and the n-side electrode 50n is not particularly limited, and a vacuum deposition method, an electron beam deposition method, a sputtering method, or the like is used depending on the material of the electrode.

  On the other hand, in the laminated wafer portion 4t, when the base substrate 10 and the intermediate layer 20 are conductive, the p-side electrode 50p is formed on the n-type GaN layer 40ng of the group III nitride semiconductor layer 40. By forming the n-side electrode 50n on the base substrate 10, the semiconductor device 5B having a vertical structure can be formed.

  In this way, according to the semiconductor device manufacturing method of the present embodiment, the semiconductor devices 5A and 5B can be obtained with a high yield.

[Embodiment 2]
Referring to FIG. 4B, a support substrate 3 for epitaxial growth which is another embodiment of the present invention includes a base substrate 10 capable of epitaxially growing at least one group III nitride semiconductor layer 40, and a base substrate The intermediate layer 20 partially disposed on the substrate 10 and the GaN layer 30a disposed on the entire surface of the intermediate layer 20 are included, and the GaN layer 30a and a part of the base substrate 10 are exposed.

  Since the support substrate 3 for epitaxial growth of this embodiment does not have a portion where the intermediate layer 20 is exposed, abnormal growth as shown in FIG. 3B occurs when the group III nitride semiconductor layer is grown. First, at least one group III nitride semiconductor layer 40 can be epitaxially grown on the GaN layer 30a of the support substrate 3 and the portions 10p, 10q, and 10r where the base substrate 10 is exposed. Here, in the support substrate 3 for epitaxial growth, it can be confirmed by an optical microscope, SEM-EDX, spectroscopic ellipsometry, and the like that the intermediate layer 20 is not exposed.

  In addition, the manufacturing method of the support substrate 3 for epitaxial growth of this embodiment is as having demonstrated using FIG. 4 (A) and (B) in Embodiment 1, and is not repeated here.

Example 1
1. Formation Process of Support Substrate A formation process of the support substrate shown in FIG. First, referring to FIG. 2A, a sapphire substrate having a diameter of 2 inches (5.08 cm) and a thickness of 350 μm was prepared as the base substrate 10. A GaN substrate 30 having a diameter of 2 inches and a thickness of 350 μm was prepared as a donor substrate for forming the GaN layer. Then, by sputtering, to form a SiO ₂ layer having a thickness of 300nm as an intermediate layer 20a on the sapphire substrate (underlying substrate 10) to form a SiO ₂ layer having a thickness of 300nm as an intermediate layer 20b on the GaN substrate 30. Next, H ⁺ ions (protons) were implanted into a surface having a depth D of 300 nm from the interface between the GaN substrate 30 and the SiO ₂ layer (intermediate layer 20b) into the GaN substrate 30. Thereafter, the surfaces of the SiO ₂ layers (intermediate layers 20a and 20b) of the respective substrates were polished to a depth of 50 nm from the surface by CMP (chemical mechanical polishing), thereby making the surfaces smoother mirror surfaces.

Next, referring to FIG. 2B, the surfaces of the respective SiO ₂ layers (intermediate layers 20a and 20b) of the sapphire substrate (underlying substrate 10) and the GaN substrate 30 are subjected to Ar (argon) plasma in a vacuum chamber. After cleaning, the surfaces of the respective SiO layers (intermediate layers 20a and 20b) were bonded together by pressure bonding with a pressure of 7 MPa (surface activation method). Thereafter, the bonded substrate is heated to 200 ° C. to 300 ° C. in the atmosphere to increase the bonding strength and activate the implanted H ⁺ ions to generate voids, thereby embrittlement of the ion implantation region 30i. .

Next, referring to FIG. 2C and FIG. 4A, the sapphire substrate (base substrate 10) and the GaN substrate were separated by applying stress. As a result, the SiO ₂ layer (intermediate layer 20) disposed entirely on the sapphire substrate (underlying substrate 10) and the GaN having a thickness of 300 nm partially disposed on the SiO ₂ layer (intermediate layer 20). The support substrate 2 including the layer 30a and exposing the GaN layer 30a and a part of the SiO ₂ layer (intermediate layer 20) was obtained. It was confirmed by SEM-EDX measurement that a part of the SiO ₂ layer (intermediate layer 20) was exposed in the support substrate 2. The reason why such a support substrate 2 is obtained is considered to be due to the reason described in FIGS. 2 (A) to 2 (C). The surface of the GaN layer 30a of the support substrate 2 was polished to a depth of 100 nm from the surface by CMP to make a mirror surface.

2. Step of selectively removing portions of supporting substrate where intermediate layer is exposed Next, referring to FIG. 4B, portions 20p, 20q of the supporting substrate 2 where the SiO ₂ layer (intermediate layer 20) is exposed. , 20r by dry etching with RIE using CF ₄ gas, a GaN substrate (underlying substrate 10) and a SiO ₂ layer (intermediate layer 20) partially disposed on the GaN substrate (underlying substrate 10) And a GaN layer 30a disposed over the entire surface of the SiO ₂ layer (intermediate layer 20), and the GaN layer 30a and a part of the GaN substrate (underlying substrate 10) are exposed. 3 was obtained. The RIE conditions were such that the RF power was 70 W, the chamber pressure was 20 Pa, the gas flow rate was 50 sccm (where 1 sccm represents a flow rate of 1 cm ³ per minute of the standard state gas), and the etching time was 10 minutes. Here, since GaN does not react with CF ₄ and its plasma active species, the GaN layer 30a is used as a kind of hard mask, and only the portion where the SiO ₂ layer (intermediate layer 20) is exposed is removed. I was able to. It was confirmed by SEM-EDX measurement that the SiO ₂ layer was not exposed in the support substrate 3 thus obtained.

3. Step of Growing Group III Nitride Semiconductor Layer on Support Substrate Next, referring to FIG. 4C, portions 10p and 10q on the GaN layer 30a of the support substrate 3 for epitaxial growth and the exposed substrate 10 are exposed. , 10r as a group III nitride semiconductor layer 40, a 0.05 μm thick n-type Al _0.05 Ga _0.95 N layer 40na, a 2 μm thick n-type GaN layer 40 ng, and a 0.05 μm thick n-type In _0.05. Ga _0.95 N layer 40ni, In _0.18 Ga _0.82 N well layer and hexagonal well structure composed of GaN barrier layer, 100 nm thick light emitting layer 40e, 20 nm thick p-type Al _0.2 Ga _0.8 N layer 40pa And 40 pg of a p-type GaN layer having a thickness of 0.15 μm was epitaxially grown. At this time, on the portions 10p, 10q, and 10r where the sapphire substrate (underlying substrate 10) of the support substrate 3 is exposed, the group III nitride semiconductor layer 40 is epitaxially grown in a film shape, and growth of polycrystalline group III nitride is performed. Was not seen.

4). Next, referring to FIG. 4D, a p-type GaN layer 40pg, a p-type Al _0.2 Ga _0.8 N layer 40pa, a light emitting layer 40e, and an n-type In _0.05 Ga _0.95 N layer are formed by mesa etching. A part of each 40 ni was removed to expose a part of the n-type GaN layer 40 ng. Next, the p-side electrode 50p is formed on the p-type GaN layer 40pg by the vacuum evaporation method or the electron beam evaporation method, and the n-side electrode 50n is formed on the portion where the n-type GaN layer 43 is exposed. A semiconductor device 5A having a lateral structure shown in FIG. In this way, the semiconductor device 5A could be obtained with a high yield.

  In Example 1, after the group III nitride semiconductor layer 40 is grown on the support substrate 3, the sapphire substrate (underlying substrate 10) is lifted off so that the group III nitride semiconductor layer 40 is separated from the other support substrate. You can also move to In addition, a GaN substrate can be used instead of the sapphire substrate used as the base substrate 10 in the first embodiment.

(Comparative Example 1)
1. Step of Forming Support Substrate With reference to FIG. 3A, in the same manner as in Example 1, the SiO ₂ layer (intermediate layer 20) disposed on the entire surface of the sapphire substrate (underlying substrate 10), and SiO ₂ A support substrate 2 including a GaN layer 30a having a thickness of 300 nm partially disposed on the layer (intermediate layer 20) and exposing the GaN layer 30a and a part of the SiO ₂ layer (intermediate layer 20). Obtained. Further, the surface of the GaN layer 30a of the obtained support substrate 2 was used as a mirror surface in the same manner as in Example 1.

2. Step of Growing Group III Nitride Semiconductor Layer on Support Substrate With reference to FIG. 3B, the portions 20p, 20q, and 20r of the support substrate 2 where the SiO ₂ layer (intermediate layer 20) is exposed are selectively removed. Except for the absence, the group III nitride semiconductor layer 40 was epitaxially grown on the support substrate 2 in the same manner as in Example 1 to obtain a laminated wafer. In the obtained laminated wafer, a group III nitride semiconductor layer 40a having a desired thickness was obtained on a portion of the GaN layer 30a where the intermediate layer 20 was not exposed in the vicinity. On the other hand, on the portion of the GaN layer 30a where the intermediate layer 20 is exposed in the vicinity, the group III nitride semiconductor layer 40b that is extremely thick compared to the desired thickness was formed. In addition, the group III nitride semiconductor layer 40 did not grow on the exposed portion 20q where the intermediate layer 20 is small (for example, the minimum diameter of the exposed portion is less than 200 μm). On the exposed portions 20p and 20r where the intermediate layer 20 is exposed to a certain size or more (for example, the minimum diameter of the exposed portion is 200 μm or more), the group III nitride microcrystals deposited thereon are used as the nucleus. Group nitride polycrystal 44 grew. Here, the thickness of the group III nitride polycrystal 44 reached more than twice the thickness of the group III nitride semiconductor layer 40.

  Group III nitride semiconductor layer 40 formed on GaN layer 30a of the laminated wafer (that is, group III nitride semiconductor layer 40a formed on a portion of intermediate layer 20 not exposed in the vicinity of GaN layer 30a and GaN) A portion of the group III nitride semiconductor layer 40b) formed on a portion of the layer 30a where the intermediate layer 20 is exposed in the vicinity is mesa-etched to form a group III nitride semiconductor layer 40 on the p-type GaN layer. A p-side electrode was formed, and an n-side electrode was formed on the n-type GaN layer 40 ng exposed by the mesa etching, thereby fabricating a lateral type semiconductor device.

  Here, the unevenness as described above in the laminated wafer prevents the uniform application of the resist, for example, in the photolithography process in the production of the electrode, and the uniform adhesion between the contact mask and the laminated wafer and the resist applied on the surface thereof. In the manufacture of semiconductor devices, various problems that lead to a decrease in the yield of the semiconductor devices have occurred. Also, even in the manufactured semiconductor device, the designed emission intensity, emission (center) wavelength, and voltage-current characteristics were not obtained in the semiconductor device including the group III nitride semiconductor layer 40b at least in part.

(Example 2)
1. Step of forming support substrate Referring to FIG. 4A, the same procedure as in Example 1 was performed except that a GaN substrate having a diameter of 2 inches and a thickness of 350 μm was used as base substrate 10 and an ITO layer was formed as intermediate layer 20. An ITO layer (intermediate layer 20) disposed on the entire surface of the GaN substrate (underlying substrate 10), and a GaN layer 30a having a thickness of 300 nm partially disposed on the ITO layer (intermediate layer 20), The support substrate 2 including the GaN layer 30a and a part of the ITO layer (intermediate layer 20) was obtained. Here, the formation method and thickness of the ITO layer (intermediate layers 20a, 20b, 20) were the same as those in Example 1. Further, the surface of the GaN layer 30a of the obtained support substrate 2 was mirror-finished in the same manner as in Example 1.

2. Next, referring to FIG. 4B, the portions 20p, 20q, 20p, 20q, where the ITO layer (intermediate layer 20) of the support substrate 2 is exposed. 20r was wet-etched at 40 ° C. for 20 minutes using a mixed solution of 30% by mass hydrochloric acid, 60% by mass nitric acid, and water at a mass ratio of 10: 1: 10, thereby obtaining a sapphire substrate (underlying substrate 10) and A GaN layer 30a including an ITO layer (intermediate layer 20) partially disposed on the sapphire substrate (underlying substrate 10) and a GaN layer 30a disposed entirely on the ITO layer (intermediate layer 20). As a result, a support substrate 3 for epitaxial growth in which a part of the sapphire substrate is exposed was obtained. It was confirmed in the same manner as in Example 1 that there was no portion where the ITO layer (intermediate layer 20) was exposed in the support substrate 3.

3. Step of Growing Group III Nitride Semiconductor Layer on Support Substrate Next, referring to FIG. 4C, portions 10p and 10q of the support substrate 3 where the GaN layer 30a and the GaN substrate (underlying substrate 10) are exposed. , 10r as a group III nitride semiconductor layer 40, a 0.05 μm thick n-type Al _0.05 Ga _0.95 N layer 40na, a 2 μm thick n-type GaN layer 40 ng, and a 0.05 μm thick n-type In _0.05. Ga _0.95 N layer 40ni, In _0.18 Ga _0.82 N well layer and hexagonal well structure composed of GaN barrier layer, 100 nm thick light emitting layer 40e, 20 nm thick p-type Al _0.2 Ga _0.8 N layer 40pa And 40 pg of a p-type GaN layer having a thickness of 0.15 μm was epitaxially grown. At this time, on the portions 10p, 10q, and 10r where the sapphire substrate (underlying substrate 10) of the support substrate 3 is exposed, the group III nitride semiconductor layer 40 is epitaxially grown in a film shape, and growth of polycrystalline group III nitride is performed. Was not seen.

4). Next, referring to FIG. 4D, a p-side electrode is formed on the p-type GaN layer 40pg which is the outermost layer of the group III nitride semiconductor layer 40 by vacuum vapor deposition or electron beam vapor deposition. 50p was formed, and an n-side electrode 50n was formed on the GaN substrate (underlying substrate 10) to obtain a semiconductor device 5B having a vertical structure shown in FIG. In this way, the semiconductor device 5B was obtained with a high yield.

(Comparative Example 2)
1. Step of Forming Support Substrate With reference to FIG. 3A, an ITO layer (intermediate layer 20) disposed over the entire surface of the GaN substrate (underlying substrate 10) and an ITO layer (in the same manner as in Example 2) A support substrate 2 including a GaN layer 30a having a thickness of 300 nm partially disposed on the intermediate layer 20) and having a part of the GaN layer 30a and the ITO layer (intermediate layer 20) exposed was obtained. Further, the surface of the GaN layer 30a of the obtained support substrate 2 was used as a mirror surface in the same manner as in Example 2.

2. Step of Growing Group III Nitride Semiconductor Layer on Support Substrate Referring to FIG. 3 (B), portions 20p, 20q and 20r where ITO layer (intermediate layer 20) of support substrate 2 is exposed are not selectively removed. Except for the above, a group III nitride semiconductor layer 40 was epitaxially grown on the support substrate 2 in the same manner as in Example 2 to obtain a laminated wafer. In the obtained laminated wafer, a group III nitride semiconductor layer 40a having a desired thickness was obtained on a portion of the GaN layer 30a where the intermediate layer 20 was not exposed in the vicinity. On the other hand, on the portion of the GaN layer 30a where the intermediate layer 20 is exposed in the vicinity, the group III nitride semiconductor layer 40b that is extremely thick compared to the desired thickness was formed. In addition, the group III nitride semiconductor layer 40 did not grow on the exposed portion 20q where the intermediate layer 20 is small (for example, the minimum diameter of the exposed portion is less than 200 μm). On the exposed portions 20p and 20r where the intermediate layer 20 is exposed to a certain size or more (for example, the minimum diameter of the exposed portion is 200 μm or more), the group III nitride microcrystals deposited thereon are used as the nucleus. Group nitride polycrystal 44 grew. Here, the thickness of the group III nitride polycrystal 44 reached more than twice the thickness of the group III nitride semiconductor layer 40.

  Group III nitride semiconductor layer 40 formed on GaN layer 30a of the laminated wafer (that is, group III nitride semiconductor layer 40a formed on a portion of intermediate layer 20 not exposed in the vicinity of GaN layer 30a and GaN) A portion of the group III nitride semiconductor layer 40b) formed on a portion of the layer 30a where the intermediate layer 20 is exposed in the vicinity is mesa-etched to form a group III nitride semiconductor layer 40 on the p-type GaN layer. A p-side electrode was formed, and an n-side electrode was formed on the n-type GaN layer 40ng exposed by the mesa etching, thereby fabricating a vertical structure semiconductor device.

  Here, the unevenness as described above in the laminated wafer prevents the uniform application of the resist, for example, in the photolithography process in the production of the electrode, and the uniform adhesion between the contact mask and the laminated wafer and the resist applied on the surface thereof. In the manufacture of semiconductor devices, various problems that lead to a decrease in the yield of the semiconductor devices have occurred. Also, even in the manufactured semiconductor device, the designed emission intensity, emission (center) wavelength, and voltage-current characteristics were not obtained in the semiconductor device including the group III nitride semiconductor layer 40b at least in part.

  Although the optical device has been described in the above embodiments, the present invention is not limited to various semiconductor devices such as a high electron mobility transistor (HEMT), a field effect transistor (FET), and a static induction transistor (SIT). The present invention can be applied to various electronic devices, optical semiconductor devices such as photodetectors, and the like.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1, 2, 3 Support substrate, 4 Laminated wafer, 4t Laminated wafer portion, 5A, 5B Semiconductor device, 10 Substrate substrate, 10p, 10q, 10r, 20p, 20q, 20r Exposed portion, 20, 20a, 20b, 20c Intermediate layer, 30, 30b GaN substrate, 30a GaN layer, 40 group III nitride semiconductor layer, 40e light emitting layer, 40nn type III nitride semiconductor layer, 40nan type Al _0.05 Ga _0.95 N layer, 40ng n type GaN Layer, 40 ni n-type In _0.05 Ga _0.95 N layer, 40 p p-type group III nitride semiconductor layer, 40 pa p-type Al _0.2 Ga _0.8 N layer, 40 pn p-type GaN layer, 44 group III nitride polycrystal, 50 n n-side electrode , 50pp side electrode.

Claims (7)

A base substrate capable of epitaxially growing at least one group III nitride semiconductor layer; an intermediate layer disposed entirely on the base substrate; and a GaN layer partially disposed on the intermediate layer. Including a step of forming a support substrate in which the GaN layer and a portion of the intermediate layer are exposed;
A step of exposing a part of the base substrate by selectively removing a portion of the support substrate where the intermediate layer is exposed;
And a step of epitaxially growing the group III nitride semiconductor layer on the GaN layer and the exposed portion of the base substrate.   The method for manufacturing a semiconductor device according to claim 1, wherein the method for selectively removing the portion where the intermediate layer is exposed is at least one of wet etching and dry etching.   The method of manufacturing a semiconductor device according to claim 2, wherein the GaN layer is used as a mask for the wet etching and dry etching.   The method for manufacturing a semiconductor device according to claim 1, wherein the base substrate includes any one selected from the group consisting of a GaN substrate, a sapphire substrate, a Si substrate, a SiC substrate, a GaAs substrate, and an InP substrate. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the intermediate layer includes any one selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Si, and SiON.   The semiconductor device according to claim 1, wherein the intermediate layer includes at least one selected from the group consisting of Sn, Zn, Ti, Cr, Ni, Ga, In, Sb, W, and Mo. Manufacturing method.   A base substrate capable of epitaxially growing at least one group III nitride semiconductor layer; an intermediate layer partially disposed on the base substrate; and a GaN layer disposed entirely on the intermediate layer. And a support substrate for epitaxial growth in which the GaN layer and a part of the base substrate are exposed.

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