JP4508021B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Manufacturing method of semiconductor light emitting device Download PDF

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JP4508021B2
JP4508021B2 JP2005208015A JP2005208015A JP4508021B2 JP 4508021 B2 JP4508021 B2 JP 4508021B2 JP 2005208015 A JP2005208015 A JP 2005208015A JP 2005208015 A JP2005208015 A JP 2005208015A JP 4508021 B2 JP4508021 B2 JP 4508021B2
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semiconductor layer
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nanocolumn
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JP2007027448A (en
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信之 高倉
隆好 高野
正治 安田
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Panasonic Corp
Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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本発明は、半導体内で電子と正孔とを結合させて発光させる半導体発光素子の製造方法に関し、特に前記半導体発光素子としては、ナノコラムと称される柱状結晶構造体を複数有して成るものに関する。 The present invention relates to a method of manufacturing a semiconductor light-emitting element to emit light coupled to form the electrons and holes in the semiconductor, and in particular examples of the semiconductor light emitting element has a plurality of nano-columns called columnar crystal structure About things.

近年、III−N化合物半導体(以下、ナイトライドと呼ぶ)または酸化物半導体を用いて、その中に量子井戸を形成し、外部から電流を流して、この量子井戸で電子と正孔とを結合させて発光させる固体発光素子の発展が目覚しい。しかしながら、これらの固体発光素子の作製においては、以下に述べる課題を有する。   In recent years, a quantum well is formed in a III-N compound semiconductor (hereinafter referred to as a nitride) or an oxide semiconductor, and a current is applied from outside to couple electrons and holes in the quantum well. The development of solid-state light-emitting elements that emit light by making them light is remarkable. However, the fabrication of these solid state light emitting devices has the following problems.

たとえば、ナイトライドに関して言及すると、結晶成長が抱える根本的な課題として、異種材料基板上への結晶成長が主であるということが挙げられる。ナイトライドのヘテロエピタキシャル成長に関する一般的な成長モデルとしては、先ず基板上に薄く堆積された低温バッファ層上に三次元核が形成され、さらに成長が進むと核が大きくなり、隣接する核と結合して平坦な面が形成される。以降、平坦な面を維持しながら2次元成長を継続する。しかしながら、隣接する核が結合する際、それぞれの核が独立して形成されているので、成長面が完全に一致せず、結合後、核界面に多くの欠陥を形成する。欠陥の多くは貫通転位として結晶表面にまで達する。この貫通転位は非発光再結合中心として作用し、固体発光素子の発光効率を著しく減少させる。   For example, when referring to nitride, a fundamental problem that crystal growth has is that crystal growth on a dissimilar material substrate is the main. As a general growth model for nitride heteroepitaxial growth, three-dimensional nuclei are first formed on a low-temperature buffer layer that is thinly deposited on the substrate, and as the growth proceeds further, the nuclei become larger and combine with adjacent nuclei. And a flat surface is formed. Thereafter, the two-dimensional growth is continued while maintaining a flat surface. However, when adjacent nuclei are bonded, the respective nuclei are formed independently, so that the growth planes do not coincide completely, and after bonding, many defects are formed at the nuclear interface. Many of the defects reach the crystal surface as threading dislocations. This threading dislocation acts as a non-radiative recombination center and significantly reduces the luminous efficiency of the solid state light emitting device.

このような課題に対して、従来から、貫通転位を減少させるための様々な取り組みがなされてきた。その結果、当初、ナイトライド結晶内に1010cm−2程度あった転位を、10cm−2程度まで減少させるに至っている。 Conventionally, various efforts have been made to reduce threading dislocations against such problems. As a result, the dislocation that was initially about 10 10 cm −2 in the nitride crystal has been reduced to about 10 5 cm −2 .

さらなる低転位化技術として、柱状結晶構造体(以下、ナノコラムと呼ぶ)が注目され始めている。ナノコラムは、100nm程度の直径を有し、隣接する核が結合することなく、独立して柱状の結晶を形成している。したがって、ナノコラムにはその結晶内にほとんど貫通転位を含まず、非常に高品質な結晶を得ることができる。また、ナノコラムは表面積が薄膜に比べて格段に大きく、円筒形状をしているので、通常の薄膜の発光素子に比べて、光取り出し効率の向上が期待されている。   As a further technique for lowering dislocations, columnar crystal structures (hereinafter referred to as nanocolumns) have begun to attract attention. The nanocolumn has a diameter of about 100 nm and forms columnar crystals independently without bonding adjacent nuclei. Therefore, the nanocolumn hardly contains threading dislocations in the crystal, and a very high quality crystal can be obtained. In addition, since the nanocolumn has a significantly larger surface area than a thin film and has a cylindrical shape, an improvement in light extraction efficiency is expected as compared with a normal thin film light emitting element.

そのようなナノコラムを用いた固体発光素子の製作が試みられた一例として、図5に非特許文献1の構造を示す。その従来技術によれば、RF−MBE(高周波分子線エピタキシー)装置によって、シリコン基板43上に、n型GaNナノコラム層44、発光層45を形成し、ナノコラム径を広げながらp型GaNコンタクト層46をエピタキシャル成長させた上に、半透明p型電極のNi(2nm)/Au(3nm)を形成させている。
菊池、野村、岸野「窒化物半導体ナノコラム結晶を用いた新しい機能性デバイス材料の開発」(応用物理学会2004年秋季大会予稿集第1分冊4P−W−1)
As an example of an attempt to manufacture a solid-state light emitting device using such a nanocolumn, FIG. According to the prior art, an n-type GaN nanocolumn layer 44 and a light emitting layer 45 are formed on a silicon substrate 43 by an RF-MBE (high frequency molecular beam epitaxy) apparatus, and the p-type GaN contact layer 46 is expanded while increasing the nanocolumn diameter. Is epitaxially grown, and Ni (2 nm) / Au (3 nm) of a translucent p-type electrode is formed.
Kikuchi, Nomura, Kishino “Development of New Functional Device Materials Using Nitride Semiconductor Nanocolumn Crystals” (Applied Physics Society 2004 Autumn Conference Proceedings Vol. 1 P-W-1)

しかしながら、上述の従来技術では、p型電極を形成するために面方位の異なる結晶が混在して成長し、たとえナノコラム内に貫通転位が無くとも、p型電極形成層(p型GaNコンタクト層46)に多数の貫通転位が発生してしまうという問題がある。その貫通転位で、発光層45で発生した光の多くが、基板43やp型電極領域に吸収されてしまい、光取り出し効率が、期待される程、向上できていないのが実情である。   However, in the above-described prior art, crystals having different plane orientations grow together to form a p-type electrode, and even if there are no threading dislocations in the nanocolumn, the p-type electrode formation layer (p-type GaN contact layer 46). ) Has a problem that many threading dislocations are generated. Due to the threading dislocation, most of the light generated in the light emitting layer 45 is absorbed by the substrate 43 and the p-type electrode region, and the light extraction efficiency is not improved as expected.

本発明の目的は、光取り出し効率を一層向上することができる半導体発光素子の製造方法を提供することである。 An object of the present invention is to provide a method of manufacturing a semiconductor light emitting element which can be further improved light extraction efficiency.

発明の半導体発光素子の製造方法は、単結晶基板上に、n型窒化物半導体層またはn型酸化物半導体層と、発光層と、p型窒化物半導体層またはp型酸化物半導体層とを順に積層した柱状結晶構造体を複数有して成る半導体発光素子の製造方法において、前記p型窒化物半導体層またはp型酸化物半導体層を平坦に研磨する工程と、研磨した前記p型窒化物半導体層またはp型酸化物半導体層上に導電性基板を積層し、加圧および加熱することでそれらを貼合わせ、前記導電性基板をp型電極に形成する工程と、前記導電性基板を貼合わせる工程の前に、該導電性基板および柱状結晶構造体の少なくとも一方の貼合わせ面側に、窒素原子を含むプラズマを照射する工程とを含むことを特徴とする。 A method for manufacturing a semiconductor light emitting device according to the present invention includes an n-type nitride semiconductor layer or an n-type oxide semiconductor layer, a light-emitting layer, a p-type nitride semiconductor layer or a p-type oxide semiconductor layer on a single crystal substrate. In the method for manufacturing a semiconductor light emitting device comprising a plurality of columnar crystal structures laminated in order, the step of polishing the p-type nitride semiconductor layer or the p-type oxide semiconductor layer flatly and the polished p-type nitride A step of laminating a conductive substrate on a physical semiconductor layer or a p-type oxide semiconductor layer, laminating them by applying pressure and heating, and forming the conductive substrate into a p-type electrode; and Before the bonding step , the method includes a step of irradiating at least one bonding surface side of the conductive substrate and the columnar crystal structure with a plasma containing nitrogen atoms .

上記の構成によれば、単結晶基板上に柱状構造を維持したまま、n型窒化物半導体層またはn型酸化物半導体層、発光層、およびp型窒化物半導体層またはp型酸化物半導体層を順に成長させることで、複数の柱状結晶構造体(ナノコラム)を有して成る半導体発光素子を製造するにあたって、そのナノコラムの先端側に設けるべきp型電極を、導電性基板の貼合わせで作成する。具体的には、その貼合わせにあたって、前記p型窒化物半導体層またはp型酸化物半導体層の先端を、化学的もしくは物理的に研磨して高さを揃えて平坦にし、その後、前記導電性基板を積層し、加圧および加熱して貼合わせる。   According to the above configuration, the n-type nitride semiconductor layer or the n-type oxide semiconductor layer, the light emitting layer, and the p-type nitride semiconductor layer or the p-type oxide semiconductor layer while maintaining the columnar structure on the single crystal substrate. In order to manufacture a semiconductor light emitting device having a plurality of columnar crystal structures (nanocolumns), a p-type electrode to be provided on the tip side of the nanocolumns is created by laminating conductive substrates. To do. Specifically, in the bonding, the tip of the p-type nitride semiconductor layer or the p-type oxide semiconductor layer is chemically or physically polished to make the height uniform and then flattened. Laminate the substrates and bond them by pressing and heating.

したがって、導電性基板から成るp型電極内には、前記p型窒化物半導体層またはp型酸化物半導体層を面方向に成長させてp型電極とした場合に生じるような貫通転位はなく、ナノコラムが内部に貫通転位を持たないという利点を活かした高効率な半導体発光素子を製造することができる。   Therefore, there is no threading dislocation that occurs when the p-type nitride semiconductor layer or the p-type oxide semiconductor layer is grown in the plane direction to form a p-type electrode in the p-type electrode made of a conductive substrate. A highly efficient semiconductor light emitting device can be manufactured taking advantage of the fact that the nanocolumn does not have threading dislocations inside.

また、前記導電性基板を貼合わせる工程の前に、該導電性基板および柱状結晶構造体の少なくとも一方の貼合わせ面側に、窒素原子を含むプラズマを照射する工程をさらに行、その貼合わせる面を活性化しておくで、表面原子同士の結合力を強固にすることができ、貼合わせ時の圧力や温度を低くして、素子へのダメージを低減することができる。 Further, before the prior Kishirube conductive substrate is laminated step, at least one of the cemented surface of the conductive substrate and the columnar crystal structures, it has further rows step of irradiating the plasma containing nitrogen atoms, bonded thereof the surface fit than previously activated, it is possible to strengthen the binding force between the surface atoms, to lower the pressure and temperature at the time of registration lamination, it is possible to reduce damage to the element.

さらにまた、本発明の半導体発光素子の製造方法は、前記導電性基板を貼合わせる工程を、10−6Pa以下の高真空中で行うことを特徴とする。 Furthermore, the method for manufacturing a semiconductor light emitting device of the present invention is characterized in that the step of bonding the conductive substrates is performed in a high vacuum of 10 −6 Pa or less.

上記の構成によれば、p型窒化物半導体層またはp型酸化物半導体層と導電性基板との貼合わせ面の清浄度を高め、表面原子同士の結合力を強固にすることができる。これによって、貼合わせ時の圧力や温度を低くすることができ、素子へのダメージを低減することができる。   According to said structure, the cleanliness of the bonding surface of a p-type nitride semiconductor layer or a p-type oxide semiconductor layer, and a conductive substrate can be improved, and the bonding force of surface atoms can be strengthened. Thereby, the pressure and temperature at the time of bonding can be lowered, and damage to the element can be reduced.

発明の半導体発光素子の製造方法は、以上のように、単結晶基板上に、n型窒化物半導体層またはn型酸化物半導体層と、発光層と、p型窒化物半導体層またはp型酸化物半導体層とを順に積層した柱状結晶構造体を複数有して成る半導体発光素子の製造方法において、前記p型窒化物半導体層またはp型酸化物半導体層を平坦に研磨した後、導電性基板を積層し、加圧および加熱することでそれらを貼合わせ、前記導電性基板をp型電極に形成する。 As described above, the method for manufacturing a semiconductor light emitting device of the present invention includes an n-type nitride semiconductor layer or an n-type oxide semiconductor layer, a light emitting layer, a p-type nitride semiconductor layer, or a p-type on a single crystal substrate. In the method for manufacturing a semiconductor light emitting device including a plurality of columnar crystal structures in which an oxide semiconductor layer is sequentially stacked, the p-type nitride semiconductor layer or the p-type oxide semiconductor layer is polished flatly, and then electrically conductive. Laminating the substrates, pressing and heating them together, the conductive substrate is formed on the p-type electrode.

それゆえ、導電性基板から成るp型電極内には、前記p型窒化物半導体層またはp型酸化物半導体層を面方向に成長させてp型電極とした場合に生じるような貫通転位はなく、ナノコラムが内部に貫通転位を持たないという利点を活かした高効率な半導体発光素子を製造することができる。   Therefore, there is no threading dislocation that occurs when the p-type nitride semiconductor layer or the p-type oxide semiconductor layer is grown in the plane direction to form a p-type electrode in the p-type electrode made of a conductive substrate. Thus, a highly efficient semiconductor light emitting device can be manufactured taking advantage of the fact that the nanocolumn does not have threading dislocations inside.

[実施の形態1]
図1は、本発明の実施の第1の形態に係る半導体発光素子である発光ダイオードD1の製造工程を模式的に示す断面図である。先ず、サファイア基板1上に、図示しない低温バッファ層を介して、n型基板層であるn型GaNエピ層2を形成し、このn型GaNエピ層2の表面には、将来n型電極とコンタクトを取るため、n型不純物Siを高濃度にドープしておく。このn型GaNエピ層2がn型の導電性基板となり、その上にナノコラム6を形成する。
[Embodiment 1]
FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a light-emitting diode D1 which is a semiconductor light-emitting element according to the first embodiment of the present invention. First, an n-type GaN epilayer 2 that is an n-type substrate layer is formed on a sapphire substrate 1 via a low-temperature buffer layer (not shown), and an n-type electrode and a future electrode are formed on the surface of the n-type GaN epilayer 2. In order to make contact, n-type impurity Si is doped at a high concentration. The n-type GaN epilayer 2 becomes an n-type conductive substrate, and a nanocolumn 6 is formed thereon.

本実施の形態および後述する他の実施の形態では、有機金属気相成長(MOCVD)によって作製を行うことを前提としているが、ナノコラムの成長方法はこれに限定されるものではなく、分子線エピタキシー(MBE)やハイドライド気相成長(HVPE)等の装置を用いてもナノコラムが作製可能であることは公知である。以下、特に断らない限り、MOCVD装置を用いるものとする。   In the present embodiment and other embodiments to be described later, it is assumed that fabrication is performed by metal organic chemical vapor deposition (MOCVD). However, the nanocolumn growth method is not limited to this, and molecular beam epitaxy is not limited thereto. It is well known that nanocolumns can be produced using an apparatus such as (MBE) or hydride vapor phase epitaxy (HVPE). Hereinafter, an MOCVD apparatus is used unless otherwise specified.

次に、前記n型GaNエピ層2の表面を、窒素プラズマで窒化し、成長温度を通常のGaN成長の温度より上げ、窒素過剰雰囲気下でGaNを成長させると、GaN結晶が柱状に成長する。この成長において、通常のエピ成長による発光ダイオードの作製のドーピング技術を用いると、n型GaNナノコラム3、多重量子井戸ナノコラム4(発光層を形成する。以下、MQWナノコラムと呼ぶ)、p型GaNナノコラム5を、順次積層成長させることができる。こうして、図1(a)に示すように、ナノコラム3〜5を成長させることができる。   Next, when the surface of the n-type GaN epilayer 2 is nitrided with nitrogen plasma, the growth temperature is raised from the normal GaN growth temperature, and GaN is grown in a nitrogen-excess atmosphere, a GaN crystal grows in a columnar shape. . In this growth, if a doping technique for producing a light emitting diode by normal epi growth is used, an n-type GaN nanocolumn 3, a multiple quantum well nanocolumn 4 (light emitting layer is formed; hereinafter referred to as MQW nanocolumn), a p-type GaN nanocolumn 5 can be sequentially stacked and grown. Thus, as shown in FIG. 1A, the nanocolumns 3 to 5 can be grown.

注目すべきは、本発明では、p型GaNナノコラム5上に、図1(c)に示すように、p型GaN基板7を貼合わせることである。しかしながら、前記図1(a)に示すように、ナノコラム3〜5は成長させた状態では高さは揃っていないので、貼合わせを行うことができない。そこで、多層半導体を作製する際に広く用いられるシリコンCMP技術を用い、前記ナノコラム3〜5の全体をダイヤモンドペーストを用いて回転研磨を行い、図1(b)に示すような均一な高さのナノコラム6を形成する。研磨には、他の手法が用いられてもよい。   It should be noted that in the present invention, a p-type GaN substrate 7 is bonded onto the p-type GaN nanocolumn 5 as shown in FIG. However, as shown in FIG. 1A, the nanocolumns 3 to 5 are not aligned in height in the grown state, and therefore cannot be bonded. Therefore, by using a silicon CMP technique widely used in the production of a multilayer semiconductor, the entire nanocolumns 3 to 5 are rotationally polished using a diamond paste to obtain a uniform height as shown in FIG. A nanocolumn 6 is formed. Other techniques may be used for polishing.

このナノコラムの6の先端部に、同様に研磨によって表面を平坦にした前記p型GaN基板7を積層し、貼合せ用のグラファイトの治具を用いて、8MPa程度の圧力を貼合わせ面に垂直に加え、その状態で炉に入れ、窒素雰囲気で1時間程度、適度な温度を加えると、前記図1(c)に示すように、p型GaN基板7とナノコラム6とを貼合わせることができる。   Similarly, the p-type GaN substrate 7 having a flat surface by polishing is laminated on the tip of the nanocolumn 6, and a pressure of about 8 MPa is perpendicular to the bonding surface using a bonding graphite jig. In addition, when put in a furnace in that state and an appropriate temperature is applied for about 1 hour in a nitrogen atmosphere, the p-type GaN substrate 7 and the nanocolumn 6 can be bonded together as shown in FIG. .

この貼合わせを行う前に、p型GaN基板7およびナノコラム6の少なくとも一方に窒素プラズマを照射して貼合わせ面を活性化したり、貼合わせを10−6Pa以下の超高真空で行うことで、さらに良好な貼合わせを行うことができる。前者は表面の活性化によって、後者は貼合わせ面の清浄度を高めることによって、いずれも表面原子同士の結合力を強固にする。これによって、貼合わせ時の圧力や温度を低くすることができ、素子へのダメージを低減することができる。 Before this bonding, at least one of the p-type GaN substrate 7 and the nanocolumn 6 is irradiated with nitrogen plasma to activate the bonding surface, or the bonding is performed in an ultrahigh vacuum of 10 −6 Pa or less. Further, better bonding can be performed. The former strengthens the bonding force between surface atoms by activating the surface and the latter by increasing the cleanliness of the bonded surface. Thereby, the pressure and temperature at the time of bonding can be lowered, and damage to the element can be reduced.

続いて、上記と同様に、ダイヤモンドペーストを用いた回転研磨によってp型GaN基板7を薄膜化して、図1(d)で示すように、p型GaN電極形成領域8とする。薄膜化の理由は、p型GaNはn型GaNに比べて極めて高抵抗であり、薄膜化しないと電流経路が高抵抗化し、発光ダイオードの発光効率を劣化させるためである。   Subsequently, similarly to the above, the p-type GaN substrate 7 is thinned by rotational polishing using a diamond paste to form a p-type GaN electrode formation region 8 as shown in FIG. The reason for thinning the film is that p-type GaN has an extremely high resistance compared to n-type GaN, and if the film is not thinned, the current path becomes highly resistive and the light emission efficiency of the light emitting diode is degraded.

その後、通常の発光ダイオードの作製と同じ技術を用いて電極形成を行う。すなわち、薄膜化したp型GaN電極形成領域8上にAu/Niの透明導電膜10を形成し、さらにフォトリソグラフィ技術、ドライエッチング技術によって、将来、n型電極形成部分となる領域をエッチングして、前記透明導電膜10、p型GaN電極形成領域8およびナノコラム6を取り除く。その後、p型電極11を、蒸着、リソグラフィ、ドライエッチングを用いて形成し、同様にしてn型電極12を形成し、図1(e)で示すような本実施の形態の発光ダイオードD1の構造を完成する。   Thereafter, electrodes are formed using the same technique as that for manufacturing a normal light emitting diode. That is, an Au / Ni transparent conductive film 10 is formed on the thinned p-type GaN electrode formation region 8, and a region that will become an n-type electrode formation portion in the future is etched by photolithography technology and dry etching technology. The transparent conductive film 10, the p-type GaN electrode formation region 8, and the nanocolumn 6 are removed. Thereafter, the p-type electrode 11 is formed using vapor deposition, lithography, and dry etching, the n-type electrode 12 is formed in the same manner, and the structure of the light-emitting diode D1 of the present embodiment as shown in FIG. To complete.

このようにナノコラム6の先端側に設けるべきp型電極を、p型GaN基板7の貼合わせで作成することで、該p型GaN基板7内には、前記p型GaNナノコラム5を面方向に成長させてp型電極とした場合に生じるような貫通転位はなく、ナノコラムが内部に貫通転位を持たないという利点を活かした高効率な発光ダイオードを製造することができる。   In this way, by forming a p-type electrode to be provided on the tip side of the nanocolumn 6 by bonding the p-type GaN substrate 7, the p-type GaN nanocolumn 5 is arranged in the plane direction in the p-type GaN substrate 7. There is no threading dislocation that would occur when grown into a p-type electrode, and a highly efficient light-emitting diode can be manufactured taking advantage of the fact that the nanocolumn has no threading dislocation inside.

[実施の形態2]
図2は、本発明の実施の第2の形態に係る半導体発光素子である発光ダイオードD2の製造工程を模式的に示す断面図である。この発光ダイオードD2の構造において、前述の発光ダイオードD1の構造に類似し、対応する部分には同一の参照符号を付して示し、その説明を省略する。図2(a)は前述の図1(c)と同様に、ナノコラム6の先端にp型GaN基板7を貼合せた状態を示し、注目すべきは、本実施の形態では、前記サファイア基板1が除去されて、n型GaNエピ層2と同じ型の不純物をドープして作成されたn型導電性基板19に交換されることである。
[Embodiment 2]
FIG. 2 is a cross-sectional view schematically showing a manufacturing process of the light-emitting diode D2, which is a semiconductor light-emitting element according to the second embodiment of the present invention. The structure of the light-emitting diode D2 is similar to the structure of the light-emitting diode D1 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. FIG. 2A shows a state in which a p-type GaN substrate 7 is bonded to the tip of the nanocolumn 6 in the same manner as FIG. 1C described above. It should be noted that in the present embodiment, the sapphire substrate 1 Is removed and replaced with an n-type conductive substrate 19 formed by doping impurities of the same type as the n-type GaN epilayer 2.

詳しくは、ナノコラム6の先端にp型GaN基板7を貼合せた後、サファイア基板1側からYAGレーザを照射することによって、図2(b)で示すように、該サファイア基板1を除去する。このようなサファイアのレーザリフトオフ技術は、当業者においては周知の技術であるので、詳細は省略する。   Specifically, after the p-type GaN substrate 7 is bonded to the tip of the nanocolumn 6, the sapphire substrate 1 is removed by irradiating a YAG laser from the sapphire substrate 1 side as shown in FIG. Such a sapphire laser lift-off technique is well-known to those skilled in the art, and the details are omitted.

そして、前記n型GaNエピ層2とpn接合とならない同じ極性の前記n型導電性基板19の表面に窒素プラズマを照射し、貼合わせ面の表面原子を活性化したものを前記n型GaNエピ層2の表面に積層する。この際、n型GaNエピ層2は、事前に前述のダイヤモンドペーストを用いた回転研磨によって、表面を十分平坦にしておく。その後、前記グラファイトの治具を用いて、8MPa程度の圧力を貼合わせ面に垂直に加え、その状態で炉に入れ、窒素雰囲気で1時間、適度な温度を加えると、図2(c)に示すように、n型GaNエピ層2とn型導電性基板19とが貼合わせされる。この際、前述のように超高真空中で貼合せを行うことで、より良好な貼合わせが実現されることは言うまでもない。このn型導電性基板19が本実施の形態の発光ダイオードD2でのn型電極となる。   Then, the surface of the n-type conductive substrate 19 having the same polarity that does not form a pn junction with the n-type GaN epilayer 2 is irradiated with nitrogen plasma to activate the surface atoms of the bonded surface, and the n-type GaN epilayer is activated. Laminate on the surface of layer 2. At this time, the surface of the n-type GaN epilayer 2 is made sufficiently flat in advance by rotary polishing using the aforementioned diamond paste. Then, using the graphite jig, a pressure of about 8 MPa was applied perpendicularly to the bonding surface, put in the furnace in that state, and an appropriate temperature was applied for 1 hour in a nitrogen atmosphere. As shown, the n-type GaN epilayer 2 and the n-type conductive substrate 19 are bonded together. At this time, it goes without saying that better bonding is realized by performing bonding in an ultra-high vacuum as described above. This n-type conductive substrate 19 becomes an n-type electrode in the light-emitting diode D2 of the present embodiment.

そして、第1の実施の形態と同様に、ダイヤモンドペーストを用いた回転研磨によって、図2(d)で示すようにp型GaN基板7を薄膜化して、p型GaN電極形成領域8とする。薄膜化の理由は、前述のとおりである。その後、p型GaN電極形成領域8の上に透明導電膜10を蒸着し、通常の蒸着、リソグラフィ、ドライエッチングを用いて、前記p型電極11を形成して、図2(e)で示すような本実施の形態の発光ダイオードD2の構造を完成する。   Then, as in the first embodiment, the p-type GaN substrate 7 is thinned to form the p-type GaN electrode formation region 8 by rotational polishing using a diamond paste as shown in FIG. The reason for thinning is as described above. Thereafter, a transparent conductive film 10 is deposited on the p-type GaN electrode formation region 8, and the p-type electrode 11 is formed by using normal deposition, lithography, and dry etching, as shown in FIG. Thus, the structure of the light emitting diode D2 of this embodiment is completed.

このようにナノコラム6を成長させたサファイア基板1を除去し、代わってn型GaNエピ層2と同じ極性のn型導電性基板19を貼合せることによって、n型電極からp型電極11まで、素子の厚み方向に電流を流すことができ、より一層高輝度の発光ダイオードを実現することができる。また、安価ではあるけれども、ナノコラム6の発光波長において光を吸収してしまうSi基板などの基板も、吸収を伴わないn型導電性基板19に置換えることで、ナノコラム6を成長させる基板として使用することができる。   In this way, by removing the sapphire substrate 1 on which the nanocolumns 6 are grown, and laminating an n-type conductive substrate 19 having the same polarity as that of the n-type GaN epilayer 2 instead, the n-type electrode to the p-type electrode 11 A current can flow in the thickness direction of the element, and a light-emitting diode with even higher luminance can be realized. In addition, a substrate such as a Si substrate that absorbs light at the emission wavelength of the nanocolumn 6 although it is inexpensive can be used as a substrate for growing the nanocolumn 6 by substituting the n-type conductive substrate 19 without absorption. can do.

この発光ダイオードD2は、p型GaN基板7側から光を取出すので、前記n型導電性基板19は、発光層(多重量子井戸ナノコラム4)で発生する光の反射率が80%以上であることが望ましい。前記n型導電性基板19に代えて、たとえばCuW合金などから成り、前記n型GaNエピ層2とオーミックコンタクトすることができる金属基板が用いられてもよい。   Since this light emitting diode D2 extracts light from the p-type GaN substrate 7 side, the n-type conductive substrate 19 has a reflectance of 80% or more of light generated in the light emitting layer (multiple quantum well nanocolumn 4). Is desirable. Instead of the n-type conductive substrate 19, a metal substrate made of, for example, a CuW alloy and capable of making ohmic contact with the n-type GaN epi layer 2 may be used.

[実施の形態3]
図3は、本発明の実施の第3の形態に係る半導体発光素子である発光ダイオードD3の製造工程を模式的に示す断面図である。この発光ダイオードD3の構造において、前述の発光ダイオードD2の構造に類似し、対応する部分には同一の参照符号を付して示し、その説明を省略する。注目すべきは、本実施の形態では、前述の図1(c)がナノコラム6の先端にp型GaN基板7を貼合せているのに対して、図3(a)で示すように、透明導電材料基板28を貼合せていることである。
[Embodiment 3]
FIG. 3 is a cross-sectional view schematically showing a manufacturing process of a light-emitting diode D3 which is a semiconductor light-emitting element according to the third embodiment of the present invention. The structure of the light emitting diode D3 is similar to the structure of the light emitting diode D2 described above, and corresponding portions are denoted by the same reference numerals and description thereof is omitted. It should be noted that in the present embodiment, the above-described FIG. 1C has the p-type GaN substrate 7 bonded to the tip of the nanocolumn 6, whereas, as shown in FIG. That is, the conductive material substrate 28 is bonded.

前記透明導電材料基板28の貼合わせは、前記p型GaN基板7の貼合せと条件が多少変わるだけで、ほぼ同じ工程で作製することができる。すなわち、前記ナノコラム6の先端部に、同様に研磨によって表面を平坦にした導電性材料基板28を積層し、グラファイトの治具を用いて、8MPa程度の圧力を貼合わせ面に垂直に加え、その状態で炉に入れ、窒素雰囲気で1時間、適度な温度を加えると、前記図3(a)に示すように、透明導電性材料基板28をナノコラム6の先端に貼合わせることができる。   The bonding of the transparent conductive material substrate 28 can be made in substantially the same process, with the conditions slightly different from those of the bonding of the p-type GaN substrate 7. That is, a conductive material substrate 28 whose surface is similarly flattened by polishing is laminated on the tip of the nanocolumn 6, and a pressure of about 8 MPa is applied perpendicularly to the bonding surface using a graphite jig. When placed in a furnace in a state and an appropriate temperature is applied for 1 hour in a nitrogen atmosphere, the transparent conductive material substrate 28 can be bonded to the tip of the nanocolumn 6 as shown in FIG.

この後の作製プロセスは全く第2の実施の形態と同様であり、図3(b)〜図3(e)の各工程は、図2(b)〜図2(e)の各工程にそれぞれ対応している。ただし、p型GaN基板7と異なり、透明導電材料基板28は、それ自体でp型電極となり得るので、前記透明導電膜10を形成する必要はない。したがって、サファイア基板1を除去し、n型導電性基板19を貼合せ、該透明導電材料基板28を薄膜化することで透明電極層30となり、その後、p型電極11が直接形成される。   The subsequent manufacturing process is completely the same as that of the second embodiment, and each step of FIGS. 3B to 3E is respectively replaced with each step of FIGS. 2B to 2E. It corresponds. However, unlike the p-type GaN substrate 7, the transparent conductive material substrate 28 can itself be a p-type electrode, and thus it is not necessary to form the transparent conductive film 10. Therefore, the sapphire substrate 1 is removed, the n-type conductive substrate 19 is bonded, and the transparent conductive material substrate 28 is thinned to form the transparent electrode layer 30. Thereafter, the p-type electrode 11 is directly formed.

したがって、前記透明導電膜10の形成工程を省略することができる。   Therefore, the step of forming the transparent conductive film 10 can be omitted.

[実施の形態4]
図4は、本発明の実施の第4の形態に係る半導体発光素子である発光ダイオードD4の製造工程を模式的に示す断面図である。この発光ダイオードD4の構造は、前述の発光ダイオードD1の構造に類似し、対応する部分には同一の参照符号を付して示し、その説明を省略する。注目すべきは、本実施の形態では、前述の図1(c)がナノコラム6の先端にp型GaN基板7を貼合せているのに対して、図4(a)で示すように、ブラッグ反射多層膜(以下、DBRミラー層と呼ぶ)37を積層した透明導電材料基板38を貼合せていることである。
[Embodiment 4]
FIG. 4 is a cross-sectional view schematically showing a manufacturing process of a light-emitting diode D4 which is a semiconductor light-emitting element according to the fourth embodiment of the present invention. The structure of the light-emitting diode D4 is similar to the structure of the light-emitting diode D1 described above, and corresponding portions are denoted by the same reference numerals, and description thereof is omitted. It should be noted that in the present embodiment, the p-type GaN substrate 7 is bonded to the tip of the nanocolumn 6 in FIG. 1C described above, but as shown in FIG. That is, a transparent conductive material substrate 38 on which a reflective multilayer film (hereinafter referred to as a DBR mirror layer) 37 is laminated is bonded.

前記透明導電材料基板38は、たとえばp型GaAsから成り、前記DBRミラー層37は、II−VI族の分布型ブラッグ反射多層膜を形成した導電性基板である。このII−VI族のDBRミラー層は、高い反射率(90%以上)を持つとともに、導電性であることは周知の事実である(たとえば文献1:A.Murai, L.McCarthey, U.Mishra, S.P.Denbaars, C.Kruse, S.Figge and D.Hommel J.J.Appl. Phys. Vol.43, No.10A,1275(2004))。   The transparent conductive material substrate 38 is made of, for example, p-type GaAs, and the DBR mirror layer 37 is a conductive substrate on which a II-VI group distributed Bragg reflective multilayer film is formed. It is a well-known fact that this II-VI group DBR mirror layer has high reflectivity (90% or more) and is conductive (for example, reference 1: A. Murai, L. McCarthey, U. Mishra). , SPDenbaars, C. Kruse, S. Figge and D. Hommel JJAppl. Phys. Vol. 43, No. 10A, 1275 (2004)).

本実施の形態では、貼合わせる基板がp型GaN基板7の代わりにDBRミラー層37を有する透明導電材料基板38である点を除けば、図4(a)〜図4(d)は、図1(c)〜図1(e)までの工程と全く同じであるので、詳細は省略する。   In this embodiment, except that the substrate to be bonded is a transparent conductive material substrate 38 having a DBR mirror layer 37 instead of the p-type GaN substrate 7, FIGS. Since it is exactly the same as the process from 1 (c) to FIG. 1 (e), the details are omitted.

最終的には、図4(d)に示すように、サファイア基板1上のn型GaNエピ層2上に形成されたn型電極12と、ナノコラム6上に形成されたDBRミラー層37を有する透明導電材料基板38を薄膜化したp型電極形成層40上に形成されたp型電極41とを電極とする発光ダイオードとなる。   Finally, as shown in FIG. 4D, the n-type electrode 12 formed on the n-type GaN epilayer 2 on the sapphire substrate 1 and the DBR mirror layer 37 formed on the nanocolumn 6 are provided. A light-emitting diode is obtained using the p-type electrode 41 formed on the p-type electrode formation layer 40 obtained by thinning the transparent conductive material substrate 38 as an electrode.

この発光ダイオードD4の特徴は、電流は前記p型電極41からn型電極12に流れ、途中MQWナノコラム4において電子・正孔の再結合によって光を発生するが、発生した光はDBRミラー層37でほぼすべて反射され、サファイア基板1側から取出されることである。したがって、透明導電材料基板38のGaAs層のバンドギャップが、MQWナノコラム4を形成するInGaN層のバンドギャップより小さくても問題にならず、該透明導電材料基板38での光吸収ロスをなくして、全体の発光効率を向上させることができる。   A feature of the light-emitting diode D4 is that current flows from the p-type electrode 41 to the n-type electrode 12, and light is generated by recombination of electrons and holes in the MQW nanocolumn 4, and the generated light is generated by the DBR mirror layer 37. Almost all of the light is reflected and taken out from the sapphire substrate 1 side. Therefore, there is no problem even if the band gap of the GaAs layer of the transparent conductive material substrate 38 is smaller than the band gap of the InGaN layer forming the MQW nanocolumn 4, and the light absorption loss in the transparent conductive material substrate 38 is eliminated. Overall luminous efficiency can be improved.

通常、高反射率のDBRミラーは、III−V族で形成するのは極めて困難である。これは、III族材料の層とV族材料の層との間の屈折率の差が小さいので、前記高反射率のDBRミラーを作成するためには、多くの層を積層しなければならないからである。したがって、図5で示す従来技術では、p型電極形成層(p型GaNコンタクト層)46にDBRミラー層を形成するには、前記III−V族の材料を使用しなければならないのに対して、本発明のように別の透明導電材料基板38を貼合せることで、屈折率差の大きいII−VI族のDBRミラー層37を使用することができ、所望の反射率を得るにあたって、層数を少なくすることができる。   Usually, high reflectivity DBR mirrors are very difficult to form in the III-V group. This is because the difference in refractive index between the group III material layer and the group V material layer is small, so that a large number of layers must be stacked in order to produce the high reflectivity DBR mirror. It is. Therefore, in the prior art shown in FIG. 5, in order to form a DBR mirror layer in the p-type electrode formation layer (p-type GaN contact layer) 46, the III-V group material must be used. By attaching another transparent conductive material substrate 38 as in the present invention, the II-VI group DBR mirror layer 37 having a large refractive index difference can be used. Can be reduced.

さらに、貼合わせる透明導電性基板38について、前もって形成するのは、前記DBRミラー層37に限らず、発光波長に対して高反射率の金属層などでも、同様に光取出し面への光の供給効率を向上することができる。また、透明導電性基板38として、熱伝導率の高い金属基板を用いることで、放熱特性を向上させることができ、発光効率の更なる向上が可能になる。   Further, the transparent conductive substrate 38 to be bonded is not limited to the DBR mirror layer 37 but is formed in advance, and even in the case of a metal layer having a high reflectance with respect to the emission wavelength, the light supply to the light extraction surface is similarly performed. Efficiency can be improved. Further, by using a metal substrate having a high thermal conductivity as the transparent conductive substrate 38, the heat dissipation characteristics can be improved, and the luminous efficiency can be further improved.

[実施の形態5]
以下に、本発明の実施の第5の形態に係る半導体発光素子である発光ダイオードについて説明するが、素子構造は、上述の発光ダイオードD1〜D4のいずれの構造であってもよい。注目すべきは、上述の発光ダイオードD1〜D4では、ナノコラム3〜5は窒化物半導体層から成るのに対して、本実施の形態では、酸化物半導体層から成ることである。
[Embodiment 5]
Hereinafter, a light-emitting diode that is a semiconductor light-emitting element according to the fifth embodiment of the present invention will be described. The element structure may be any of the above-described light-emitting diodes D1 to D4. It should be noted that in the above-described light emitting diodes D1 to D4, the nanocolumns 3 to 5 are made of a nitride semiconductor layer, whereas in this embodiment, the nanocolumns 3 to 5 are made of an oxide semiconductor layer.

酸化物半導体であるZnOは、発光素子として非常に優れた特性を有している。励起子の結合エネルギが60meVと、GaNの2〜3倍であり、内部量子効率がGaNに比べて高くなる可能性がある上、屈折率は約2であり、GaNの屈折率2.5に比べて小さく、光取出しの点で圧倒的に有利である。また材料自身が安価であることも商業ベースで考えると魅力的である。   ZnO which is an oxide semiconductor has extremely excellent characteristics as a light-emitting element. The exciton binding energy is 60 meV, 2 to 3 times that of GaN, the internal quantum efficiency may be higher than that of GaN, and the refractive index is about 2. It is small compared to the above, and is overwhelmingly advantageous in terms of light extraction. It is also attractive from a commercial basis that the materials themselves are inexpensive.

そこで、上述の実施の形態1〜4は、窒化物半導体であるGaN系ナノコラムについて述べているが、結晶構造上、よく似ている酸化物半導体であるZnOについても、全く同じ構造の半導体発光素子を、同様に作製することができる。このことに関して、以下に説明する。   Therefore, although the above-described first to fourth embodiments describe a GaN-based nanocolumn that is a nitride semiconductor, a semiconductor light emitting device having exactly the same structure is also used for ZnO that is an oxide semiconductor that is similar in crystal structure. Can be produced similarly. This will be described below.

GaNとZnOとは、共に六方晶系の結晶構造を持ち、結晶の格子定数も近い。バンドギャップも、GaNの3.4に対して、ZnOは3.3と、これもまた近い。両方とも直接遷移型半導体である。したがってGaNでナノコラムが形成されるのであれば、ZnOでもナノコラムが形成できる。実際、文献2では、MOCVD法を用いて、サファイア基板上にZnOのナノコラム(同文献ではナノロッドと呼んでいる)を形成している(文献2:W.I.Park, Y.H.Jun, S.W.Jung and Gyu-Chul Yi Appl.Phys.Lett. 964(2003))。   Both GaN and ZnO have a hexagonal crystal structure, and the lattice constants of the crystals are close. The band gap is also close to 3.4 for GaN and 3.3 for ZnO. Both are direct transition semiconductors. Therefore, if a nanocolumn is formed of GaN, a nanocolumn can be formed of ZnO. In fact, in Document 2, ZnO nanocolumns (called nanorods in this document) are formed on a sapphire substrate using MOCVD (Reference 2: WIPark, YHJun, SWJung and Gyu-Chul). Yi Appl. Phys. Lett. 964 (2003)).

もうひとつの本発明の重要な技術である貼合わせについてであるが、貼合せ技術で重要なことは、平坦化および加熱・加圧である。重要な物性としては熱膨張率であるが、GaNが5.6x10−6/Kなのに対して、ZnOは2.9x10−6/K(c軸に平行)、4.7x10−6/K(c軸に垂直)と、やはりGaNに近い数値を有している。したがって基本的にGaNで貼合せが可能な物質は、ZnOでも貼り合せ可能と考えられる。
以上から、実施の形態1〜4で述べた発光ダイオードD1〜D4は、ZnOでも実現可能と考えられる。
Regarding bonding, which is another important technique of the present invention, what is important in the bonding technique is flattening and heating / pressing. An important physical property is the coefficient of thermal expansion, whereas GaN is 5.6 × 10 −6 / K, whereas ZnO is 2.9 × 10 −6 / K (parallel to the c-axis), 4.7 × 10 −6 / K (c (Perpendicular to the axis) and a value close to GaN. Therefore, it is considered that a substance that can be bonded with GaN can be bonded with ZnO.
From the above, it is considered that the light-emitting diodes D1 to D4 described in the first to fourth embodiments can also be realized with ZnO.

上述のように構成される発光ダイオードD1〜D4を照明装置に用いることで、同じ光束(輝度、照度)を得るにも、小型で低消費電力な照明装置を実現することができる。   By using the light emitting diodes D1 to D4 configured as described above for the lighting device, it is possible to realize a small lighting device with low power consumption in order to obtain the same luminous flux (luminance, illuminance).

本発明の実施の第1の形態に係る半導体発光素子である発光ダイオードの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the light emitting diode which is a semiconductor light-emitting device concerning the 1st Embodiment of this invention. 本発明の実施の第2の形態に係る半導体発光素子である発光ダイオードの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the light emitting diode which is a semiconductor light-emitting device based on the 2nd Embodiment of this invention. 本発明の実施の第3の形態に係る半導体発光素子である発光ダイオードの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the light emitting diode which is a semiconductor light-emitting device concerning the 3rd Embodiment of this invention. 本発明の実施の第4の形態に係る半導体発光素子である発光ダイオードの製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the light emitting diode which is a semiconductor light-emitting device based on the 4th Embodiment of this invention. 典型的な従来技術の半導体発光素子の製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the typical prior art semiconductor light-emitting device.

1 サファイア基板
2 n型GaNエピ層
3 n型GaNナノコラム
4 多重量子井戸ナノコラム
5 p型GaNナノコラム
6 ナノコラム
7 p型Gan基板
8 p型GaN電極形成領域
10 透明導電膜
11,41 p型電極
12 n型電極
19 n型導電性基板
28 透明導電材料基板
30 透明電極層
37 ブラッグ反射多層膜
38 透明導電材料基板
D1〜D4 発光ダイオード
DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 n-type GaN epilayer 3 n-type GaN nanocolumn 4 multiple quantum well nanocolumn 5 p-type GaN nanocolumn 6 nanocolumn 7 p-type gan substrate 8 p-type GaN electrode formation region 10 transparent conductive film 11, 41 p-type electrode 12 n Type electrode 19 n-type conductive substrate 28 transparent conductive material substrate 30 transparent electrode layer 37 Bragg reflective multilayer film 38 transparent conductive material substrates D1 to D4 Light emitting diode

Claims (2)

単結晶基板上に、n型窒化物半導体層またはn型酸化物半導体層と、発光層と、p型窒化物半導体層またはp型酸化物半導体層とを順に積層した柱状結晶構造体を複数有して成る半導体発光素子の製造方法において、
前記p型窒化物半導体層またはp型酸化物半導体層を平坦に研磨する工程と
研磨した前記p型窒化物半導体層またはp型酸化物半導体層上に導電性基板を積層し、加圧および加熱することでそれらを貼合わせ、前記導電性基板をp型電極に形成する工程と、
前記導電性基板を貼合わせる工程の前に、該導電性基板および柱状結晶構造体の少なくとも一方の貼合わせ面側に、窒素原子を含むプラズマを照射する工程とを含むことを特徴とする半導体発光素子の製造方法
A plurality of columnar crystal structures in which an n-type nitride semiconductor layer or an n-type oxide semiconductor layer, a light emitting layer, and a p-type nitride semiconductor layer or a p-type oxide semiconductor layer are sequentially stacked on a single crystal substrate are provided. In the method for manufacturing a semiconductor light emitting device,
Polishing the p-type nitride semiconductor layer or the p-type oxide semiconductor layer flatly ;
Laminating a conductive substrate on the polished p-type nitride semiconductor layer or p-type oxide semiconductor layer , laminating them by applying pressure and heating, and forming the conductive substrate on a p-type electrode; ,
A step of irradiating at least one bonding surface of the conductive substrate and the columnar crystal structure with a plasma containing nitrogen atoms before the step of bonding the conductive substrate. Device manufacturing method .
前記導電性基板を貼合わせる工程を、10−6Pa以下の高真空中で行うことを特徴とする請求項記載の半導体発光素子の製造方法。 The method for manufacturing a semiconductor light emitting element according to claim 1 , wherein the step of bonding the conductive substrate is performed in a high vacuum of 10 −6 Pa or less.
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JPH06244457A (en) * 1993-02-16 1994-09-02 Nisshin Steel Co Ltd Manufacture of light emitting diode
JPH10335616A (en) * 1997-05-29 1998-12-18 Mitsubishi Materials Shilicon Corp Manufacture of soi substrate
JP2004119807A (en) * 2002-09-27 2004-04-15 Nichia Chem Ind Ltd Method for growing nitride semiconductor crystal and element using the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06244457A (en) * 1993-02-16 1994-09-02 Nisshin Steel Co Ltd Manufacture of light emitting diode
JPH10335616A (en) * 1997-05-29 1998-12-18 Mitsubishi Materials Shilicon Corp Manufacture of soi substrate
JP2004119807A (en) * 2002-09-27 2004-04-15 Nichia Chem Ind Ltd Method for growing nitride semiconductor crystal and element using the same

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