JPH10335616A - Manufacture of soi substrate - Google Patents

Manufacture of soi substrate

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Publication number
JPH10335616A
JPH10335616A JP13903197A JP13903197A JPH10335616A JP H10335616 A JPH10335616 A JP H10335616A JP 13903197 A JP13903197 A JP 13903197A JP 13903197 A JP13903197 A JP 13903197A JP H10335616 A JPH10335616 A JP H10335616A
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thin film
semiconductor substrate
substrate
surface
laminate
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JP13903197A
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JP3412449B2 (en
Inventor
Ryoko Takada
Kazunari Takaishi
Kenji Tomizawa
憲治 富澤
涼子 高田
和成 高石
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Mitsubishi Materials Shilicon Corp
三菱マテリアルシリコン株式会社
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Publication of JPH10335616A publication Critical patent/JPH10335616A/en
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Abstract

PROBLEM TO BE SOLVED: To obtain a thin film which is made uniform in thickness and excellent in surface roughness dispensing with touch polishing performed onto its surface even if its is very small in thickness.
SOLUTION: Hydrogen ions are implanted into a semiconductor substrate 11 where an insulating layer 11a is formed on its surface of the formation of a damaged region 11b in parallel with the insulating layer 1a in the semiconductor substrate 11, and the semiconductor substrate 11 is joined to a support substrate 12 to form a laminate 13. The laminate 13 is subjected to a thermal treatment under a pressure of 1×10-6 to 1×10-11Torr at a temperature of 400 to 500°C to divide the semiconductor substrate 11 in two separating the damaged region 11b into a thick-walled part 11c and a thin film 11d. Furthermore, the laminate 13 is cooled down to a prescribed temperature, the thick- walled part 11c is removed, then the laminate 13 is subjected to a thermal treatment under a pressure of 1×10-6 to 1×10-11Torr at a temperature 900 to 1200°C to make the surface of the thin film 11d flat, and the thin film 11d is stuck on the support substrate 12.
COPYRIGHT: (C)1998,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、単結晶の薄膜を支持基板上に有するSOI基板の製造方法に関するものである。 The present invention relates to relates to a manufacturing method of an SOI substrate having a thin film of single crystal on the support substrate.

【0002】 [0002]

【従来の技術】この種のSOI基板は将来の超高集積回路(ULSI)基板として注目されてきている。 BACKGROUND ART SOI substrate of this type has been noticed as a future ULSI (ULSI) substrate. このS The S
OI基板の製造方法には、シリコン基板同士を絶縁膜を介して貼り合わせる方法、絶縁性基板又は絶縁性薄膜を表面に有する基板の上にシリコン薄膜を堆積させる方法、シリコン基板の内部に高濃度の酸素イオンを注入した後、高温でアニール処理してこのシリコン基板表面から所定の深さの領域に埋込みシリコン酸化層を形成し、その表面側のSi層を活性領域とするSIMOX法などがある。 The manufacturing method of the OI substrate, a method of bonding the silicon substrate to each other through an insulating film, a high density method, within the silicon substrate to deposit a silicon thin film on a substrate having an insulating substrate or an insulating thin film surface after the implanting oxygen ions and annealed at elevated temperature to form a buried silicon oxide layer in a region of the silicon substrate surface having a predetermined depth, and the like SIMOX method in which an active region of the Si layer of the surface side .

【0003】また最近、半導体基板に水素イオン注入を行った後に、この半導体基板をイオン注入面を重ね合せ面として支持基板に重ね合せ、この積層体を500℃を越える温度に昇温して上記半導体基板を水素イオン注入部分で支持基板から分離し、支持基板の表面に薄膜を有する薄い半導体材料フィルムの製造方法が提案されている(特開平5−211128)。 [0003] Recently, after the hydrogen ion implantation into the semiconductor substrate, overlapping the semiconductor substrate to a supporting substrate as mating surface overlapping ion implantation surface, the temperature was raised to the laminate to a temperature exceeding 500 ° C. It separated from the support substrate a semiconductor substrate with hydrogen ion implantation portion, the manufacturing method of a thin semiconductor material film having a thin film has been proposed on the surface of the supporting substrate (JP-a 5-211128). この方法では、イオンを半導体基板の内部に表面から均一に注入できれば、均一な厚さの薄膜を有する半導体基板が得られる。 In this way, if uniformly injected from the surface ions in the semiconductor substrate, a semiconductor substrate having a thin film of uniform thickness is obtained. また支持基板の表面に予め酸化層を設けておけば、この方法によりSOI基板を製造することができる。 Also if provided pre-oxidized layer on the surface of the supporting substrate, it is possible to manufacture an SOI substrate by this method. なお、半導体基板を水素イオン注入部分で支持基板から分離するときの雰囲気は、通常大気圧と同一の窒素雰囲気中で行われる。 Incidentally, the atmosphere at the time of separating the semiconductor substrate from the supporting substrate with hydrogen ion implantation section is usually carried out in atmospheric pressure and in the same nitrogen atmosphere.

【0004】一方、近年マイクロエレクトロニクスデバイスの高集積化、デバイス最小寸法の縮小に伴い、ウェーハ表面の清浄度とともにウェーハ表面の微視的ラフネス、即ちマイクロラフネス(micro-roughness)が重要視されてきている。 On the other hand, in recent years high integration of microelectronic devices, with the reduction of the device minimum dimension, microscopic roughness of the wafer surface with cleanliness of the wafer surface, i.e. microroughness (micro-roughness) is becoming as important there. 特にマイクロラフネスはデバイスの酸化膜耐圧などの電気特性に大きな影響を与えることが認識されている((M.Morita, et al.,"Effect of Si wa Particularly microroughness has been recognized that a significant effect on the electrical properties such as oxide dielectric breakdown voltage of the device ((M.Morita, et al., "Effect of Si wa
fer surface micro-roughness on electrical properti fer surface micro-roughness on electrical properti
es of very-thin gate oxide films", ULSI Science an es of very-thin gate oxide films ", ULSI Science an
d Technology/1991,pp.400-408, Electrochem, Society d Technology / 1991, pp.400-408, Electrochem, Society
(1991))。 (1991)). なお、ここでマイクロラフネスは1μm以下数nmのオーダの表面粗さをいう。 Here, micro-roughness refers to a surface roughness of several nm order or less 1 [mu] m.

【0005】上記特開平5−211128号公報に示された方法で半導体基板を分離した直後の支持基板の表面に存する薄膜の表面の平均粗さは、分離前の半導体基板表面の平均粗さの10倍以上であり、マイクロラフネスが比較的大きく、上述した酸化膜耐圧などの電気特性に悪影響を及ぼすおそれがある。 [0005] The average surface roughness of the thin film existing in the surface of the support substrate immediately after separation of the semiconductor substrate in the manner shown in JP-A Hei 5-211128 has the average roughness of the pre-separation of the semiconductor substrate surface is 10 times or more, microroughness is relatively large, it may adversely affect the electrical properties, such as oxide dielectric breakdown voltage mentioned above. 特にこの方法では、半導体基板の分離により形成された薄膜の表面は、熱処理に伴う微小気泡の形状が残っているためにマイクロラフネスが大きく、デバイスの作製には適さない。 Particularly in this method, the surface of a thin film formed by the separation of the semiconductor substrate, the micro-roughness greatly to remain the shape of microbubbles due to heat treatment is not suitable for fabrication of the device.

【0006】この点を解決するため、半導体基板を分離した後の支持基板上の薄膜表面をタッチポリッシュ(to [0006] To solve this problem, touch polishing the support film surface on the substrate after separating the semiconductor substrate (to
uch polishing)と呼ばれる、軽い研磨を施すことにより、この薄膜の表面を平坦化している(M.Bruel et a uch Polishing) and called lighter polished by the applying, the surface of the thin film is planarized (M.Bruel et a
l.,"A Promising New SOI Material Technology" IEEE l., "A Promising New SOI Material Technology" IEEE
International SOI Conference proceedings,pp.178-17 International SOI Conference proceedings, pp.178-17
9 (1995))。 9 (1995)).

【0007】 [0007]

【発明が解決しようとする課題】しかしながら、現状のタッチポリッシュの技術を、上記方法で作製した厚さ数百nm以下の極めて薄い薄膜に適用した場合には、薄膜表面を平坦化することはできるが、面内で研磨量のばらつきがあるため、薄膜の厚さ分布が大きくなる不具合があった。 [SUMMARY OF THE INVENTION However, the technology of the current touch polishing, when applied to a very thin film of thickness less than several hundred nm produced above method can be planarized thin film surface but because of the variation in the polishing amount in the plane, there is a problem that the thickness distribution of the thin film increases. この薄膜の厚さ分布が大きいため、研磨後の薄膜半導体基板を用いてデバイスを作製した場合に、デバイスの特性がばらつく問題点があった。 Therefore the thickness distribution of the thin film is large, the case of manufacturing a device using a thin film semiconductor substrate after polishing, a problem that device characteristics vary.

【0008】本発明の目的は、薄膜表面のタッチポリッシュによる研磨を極力低減若しくは不要にでき、しかも厚さが極めて薄い薄膜であっても、膜厚が均一で表面粗さが良好な薄膜を得ることができるSOI基板の製造方法を提供することにある。 An object of the present invention can polishing by touch polishing of the thin film surface minimized or unnecessary, yet even extremely thin film thickness, the film thickness is uniform and the surface roughness to obtain a good film it is to provide a method for manufacturing an SOI substrate that can. 本発明の別の目的は、薄膜表面の平坦化と薄膜の支持基板への貼合せを同時に行うことにより製造工程の負荷を低減できるSOI基板の製造方法を提供することにある。 Another object of the present invention is to provide a method for manufacturing an SOI substrate that can reduce the load on the production process by performing the lamination to the support substrate planarization and thin film surface at the same time.

【0009】 [0009]

【課題を解決するための手段】請求項1に係る発明は、 Means for Solving the Problems The invention according to claim 1,
図1及び図2に示すように、表面に絶縁層11aが形成された半導体基板11に水素イオンを注入して半導体基板11内部に絶縁層11aに平行な損傷領域11bを形成する工程と、半導体基板11を支持基板12に重ね合せて積層体13を形成する工程と、積層体13を1×1 As shown in FIGS. 1 and 2, forming a parallel damaged region 11b in the insulating layer 11a in the semiconductor substrate 11 by implanting hydrogen ions into the semiconductor substrate 11 where the insulating layer 11a is formed on the surface, the semiconductor forming a laminated body 13 by superposing substrate 11 on the supporting substrate 12, the laminate 13 1 × 1
-6 〜1×10 -11 torrの真空中で400〜500℃の範囲に昇温して半導体基板11を損傷領域11bで厚肉部11c及び薄膜11dに分離する工程とを含むSOI 0 -6 SOI and a step of separating the thick portion 11c and the thin film 11d of the semiconductor substrate 11 by heating to a range of 400 to 500 ° C. in to 1 × 10 -11 in torr of vacuum in the damaged region 11b
基板の製造方法である。 It is a method of manufacturing a substrate. この請求項1に記載されたSO SO that described in claim 1
I基板の製造方法では、半導体基板11が厚肉部11c The I substrate manufacturing method, the semiconductor substrate 11 is thick-walled portion 11c
と薄膜11dとに分離されるのは、半導体基板11に注入した水素イオンを起因とする微小気泡の内圧と半導体基板11外部の圧力との差が十分に大きくなることにより起こると考えられる。 As being separated into a thin film 11d is believed to occur by the difference between the internal pressure and the semiconductor substrate 11 outside the pressure of the microbubbles and caused the hydrogen ions implanted into the semiconductor substrate 11 is sufficiently large. この結果、半導体基板11外部の圧力が小さい方が薄膜11d分離に必要な微小気泡の内圧が小さくて済むため、1×10 -6 〜1×10 -11 tor As a result, the person semiconductor substrate 11 outside of the pressure is small only a small internal pressure of the microbubbles necessary for the thin film 11d separation, 1 × 10 -6 ~1 × 10 -11 tor
rと極めて真空度の高い雰囲気中で加熱すると、微小気泡の成長が比較的少ない状態で薄膜11dを分離できる。 When heated in extremely high vacuum and r atmosphere, it can be separated thin film 11d with a relatively small state growth of microbubbles. 従って、薄膜11dの分離面の表面粗さが小さくなると考えられる。 Therefore, it is considered that the surface roughness of the separation surface of the thin film 11d is reduced.

【0010】請求項2に係る発明は、請求項1に係る発明であって、更に図1及び図2に示すように、積層体1 [0010] The invention according to claim 2, an invention according to claim 1, as further shown in FIGS. 1 and 2, the laminate 1
3の温度を所定の温度まで下げて半導体基板11の厚肉部11cを除去した後に、積層体13を1×10 -6 〜1 The third temperature after removing the thick portion 11c of the semiconductor substrate 11 is lowered to a predetermined temperature, the laminate 13 1 × 10 -6 ~1
×10 -11 torrの真空中で900〜1200℃の範囲に昇温して薄膜11d表面を平坦化しかつ薄膜11dを支持基板12に貼合せることを特徴とする。 By heating to a range of 900 to 1200 ° C. in a vacuum of × 10 -11 torr to planarize the thin film 11d surface and is characterized in that it is laminated a thin film 11d on the supporting substrate 12. この請求項2 The claim 2
に記載されたSOI基板の製造方法では、1×10 -6 The method for manufacturing an SOI substrate according to, 1 × 10 -6 ~
1×10 -11 torrと極めて真空度の高い雰囲気中で70 70 in extremely high vacuum atmosphere 1 × 10 -11 torr
0℃まで昇温すると、半導体基板11に注入された水素イオンの薄膜11dからの脱離が完了し、これに伴って薄膜11dの表面粗さが小さくなる。 When the temperature is raised to 0 ° C., the desorption is completed from the thin film 11d of implanted hydrogen ions into the semiconductor substrate 11, the surface roughness of the thin film 11d is reduced accordingly. 一方、薄膜11d On the other hand, thin film 11d
と支持基板12との貼合せ熱処理は通常900〜120 The combined heat treatment bonded with the supporting substrate 12 typically 900-120
0℃の範囲で行われる。 It is carried out in the range of 0 ℃. この結果、上記熱処理は薄膜1 As a result, the heat treatment films 1
1d表面の平坦化熱処理と薄膜11dの貼合せ熱処理とを兼ねるので、SOI基板14の製造工数を低減できる。 Also serves as a lamination heat treatment of flattening heat treatment and thin film 11d of 1d surface, it reduces the manufacturing steps of the SOI substrate 14.

【0011】請求項3に係る発明は、請求項1に係る発明であって、更に損傷領域で分離した厚肉部を薄膜に重ねたまま積層体を1×10 -6 〜1×10 -11 torrの真空中で900〜1200℃の範囲に更に昇温して、薄膜表面を平坦化しかつ薄膜を支持基板に貼合せた後に、降温して厚肉部を除去することを特徴とする。 [0011] claimed invention according to claim 3, wherein an invention according to item 1, further damaged region while the separated thick portions superimposed on the thin-film laminate 1 × 10 -6 ~1 × 10 -11 torr further raising the temperature to a range of 900 to 1200 ° C. in a vacuum of, the thin film surface after the lamination of the flattened and thin film support substrate, and removing the thick portion temperature was lowered. この請求項3 This claim 3
に記載されたSOI基板の製造方法では、半導体基板の薄膜の分離後に降温せずに、更に900〜1200℃の範囲まで昇温するので、上記請求項2に係るSOI基板の製造方法より熱処理の工数及び熱エネルギの損失を低減できる。 In the manufacturing method of an SOI substrate according, without cooling after the separation of the thin film of the semiconductor substrate, further because the temperature is raised to the range of 900 to 1200 ° C., the thermal treatment from the method for manufacturing an SOI substrate according to the claim 2 It can reduce the loss of man-hours and thermal energy.

【0012】 [0012]

【発明の実施の形態】次に本発明の実施の形態を図面に基づいて説明する。 It will be described with reference DETAILED DESCRIPTION OF THE INVENTION Next embodiment of the present invention with reference to the drawings. 図1及び図2(a)に示すように、 As shown in FIGS. 1 and 2 (a),
本発明のSOI基板を製造するには、先ずシリコンウェーハからなる半導体基板11を熱酸化により基板11表面に絶縁層である酸化層11a(SiO 2層)を形成した後、この基板11に水素イオンを3.5×10 16 H/ In order to manufacture the SOI substrate of the present invention, first after the semiconductor substrate 11 made of silicon wafers to form an oxide layer 11a is an insulating layer on the substrate 11 surface by thermal oxidation (SiO 2 layer), the hydrogen ions on the substrate 11 the 3.5 × 10 16 H /
cm 2 〜1×10 17 H/cm 2のドーズ量でイオン注入する(図1(a))。 cm 2 ~1 × 10 17 ions are implanted at a dose of H / cm 2 (Figure 1 (a)). 符号11bは水素イオン注入により半導体基板11内部に形成された損傷領域であり、この損傷領域11bは酸化層11aに平行に形成される。 Numeral 11b is a damaged region formed in the semiconductor substrate 11 by hydrogen ion implantation, the damaged region 11b are formed in parallel with the oxide layer 11a. 次いで上記と同一のシリコンウェーハからなる支持基板1 Then the support substrate 1 made of the same silicon wafer and the
2を用意し(図1(b))、両基板11,12をRCA 2 was prepared (FIG. 1 (b)), the two substrates 11, 12 RCA
法により洗浄した後、支持基板12上に半導体基板11 After washing by law, the semiconductor substrate 11 to the supporting substrate 12
を室温で重ね合せて積層体13を形成する(図1 To form a laminated body 13 overlapped at room temperature (Fig. 1
(c))。 (C)). 次に上記積層体13を1×10 -6 〜1×10 Then the laminated body 13 1 × 10 -6 ~1 × 10
-11 torr、好ましくは1×10 -7 〜1×10 -9の真空中で400〜500℃(図2)、好ましくは400〜45 -11 torr, 400 to 500 ° C. preferably in a vacuum of 1 × 10 -7 ~1 × 10 -9 ( Figure 2), preferably from 400 to 45
0℃の範囲に昇温し、この温度範囲に0〜10分間(図2)、好ましくは1〜2分間保持して薄膜分離熱処理を行う。 The temperature was raised to the range of 0 ° C., 0 minutes in this temperature range (Fig. 2), preferably held a thin film is separated heat treatment for 1-2 minutes. これにより半導体基板11が損傷領域11bのところで割れて上部の厚肉部11cと下部の薄膜11dに分離する(図1(d))。 Thus, a semiconductor substrate 11 is broken at the damaged region 11b separates the upper portion of the thick portion 11c and the lower thin film 11d (FIG. 1 (d)).

【0013】ここで、上記薄膜分離熱処理の雰囲気を1 [0013] In this case, the atmosphere of the thin film separation heat-treated for 1
×10 -6 〜1×10 -11 torrの真空に限定したのは、1 × 10 -6 to 1 was limited to a vacuum of × 10 -11 torr is 1
×10 -6 torr未満では分離面の平坦化が不十分となる不具合があり、1×10 -11 torrを越えると装置の設計上の実現が難しいからである。 × is less than 10 -6 torr there is a problem that flattening of the separation surface is insufficient, because the realization of the design of more than a device 1 × 10 -11 torr difficult. また上記熱処理の温度を4 Also 4 the temperature of the heat treatment
00〜500℃に限定したのは、400℃未満では水素による気泡内圧の上昇が十分でない不具合があり、50 00-500 was limited to ° C., in less than 400 ° C. is defective increase in bubble internal pressure caused by hydrogen is not sufficient, 50
0℃を越えると気泡の成長が進んで表面粗さが増大する不具合があるからである。 Exceeds 0 ℃ If there is a disadvantage that growth proceeds in the surface roughness of the bubbles increases.

【0014】更に上記半導体基板11が損傷領域11b Furthermore the semiconductor substrate 11 is damaged region 11b
で割れた積層体13の温度を200〜300℃まで下げて半導体基板11の厚肉部11cを除去し、支持基板1 The in cracking temperature of the stack 13 the thick portion 11c of the semiconductor substrate 11 is removed down to 200 to 300 [° C., the supporting substrate 1
2の上面に単結晶シリコンの薄膜11dを積層した状態で(図1(e))、1×10 -6 〜1×10 -11 torr、好ましくは1×10 -7 〜1×10 -9 torrの真空中で900 2 of the upper surface while laminating thin films 11d of the single-crystal silicon (FIG. 1 (e)), 1 × 10 -6 ~1 × 10 -11 torr, preferably 1 × 10 -7 ~1 × 10 -9 torr in the vacuum 900
〜1200℃(図2(a))、好ましくは1000〜1 To 1200 ° C. (FIG. 2 (a)), preferably 1,000 to
100℃の範囲に昇温しこの温度範囲に30〜120分間、好ましくは40〜60分間保持する熱処理を行う。 In the range of 100 ° C. raised the temperature range 30 to 120 minutes, preferably subjected to heat treatment of holding 40 to 60 minutes.
この熱処理は薄膜11d表面の平坦化熱処理と薄膜11 Flattening heat treatment in the heat treatment film 11d surface and the thin film 11
dの支持基板12への貼合せ熱処理とを兼ねる熱処理である。 A heat treatment which also serves as a lamination heat treatment to d the support substrate 12.

【0015】即ち、1×10 -6 〜1×10 -11 torrと極めて真空度の高い雰囲気中で700℃まで昇温すると、 [0015] That is, when the temperature is raised to 700 ° C. in a very high vacuum atmosphere 1 × 10 -6 ~1 × 10 -11 torr,
半導体基板11に注入された水素イオンの薄膜11dからの脱離が完了し、これに伴って薄膜11dの表面粗さが小さくなる。 Desorption is completed from the thin film 11d of implanted hydrogen ions into the semiconductor substrate 11, the surface roughness of the thin film 11d is reduced accordingly. これは昇温脱離ガス分析装置(TDS) This thermal desorption analyzer (TDS)
を用いて測定して判明した。 It was found as measured using. 一方、薄膜11dと支持基板12との貼合せ熱処理は通常900〜1200℃の範囲で行われる。 On the other hand, combined heat treatment lamination of the thin film 11d and the supporting substrate 12 is carried out usually in the range of 900 to 1200 ° C.. この結果、上記真空中で900〜120 As a result, in the vacuum 900-120
0℃の範囲に昇温することにより、薄膜11d表面を平坦化し、同時に薄膜11dを支持基板12に貼合せることができるので、SOI基板14の製造工数を低減できる。 By increasing the temperature in the range of 0 ° C., the thin film 11d surface planarized, it is possible is laminated a thin film 11d on the supporting substrate 12 at the same time, can reduce the number of steps for manufacturing the SOI substrate 14. また上記平坦化熱処理及び貼合せ熱処理を行う前に積層体13の温度を200〜300℃まで下げて厚肉部11cを除去したのは、枚葉処理ではなく、バッチ処理により生産したときに、その生産効率を向上するためである。 Also the removal of the thick portion 11c down to 200 to 300 [° C. The temperature of the laminate 13 before the above flattening heat treatment and lamination heat treatment is not a single wafer processing, when produced by a batch process, this is to improve the production efficiency.

【0016】なお、上記実施の形態では、半導体基板の表面に熱酸化により絶縁層である酸化層(SiO 2層) [0016] In the above embodiment, oxide layer as an insulating layer by thermal oxidation on the surface of the semiconductor substrate (SiO 2 layer)
を形成したが、半導体基板の表面に窒化処理等により絶縁層を形成してもよい。 It was formed, an insulating layer may be formed by such nitriding process on a surface of the semiconductor substrate. また、上記実施の形態では、積層体の温度を所定の温度まで下げて半導体基板の厚肉部を除去した後に、積層体を1×10 -6 〜1×10 -11 tor In the above embodiment, after removing the thick portion of the semiconductor substrate by lowering the temperature of the laminate to a predetermined temperature, the laminate 1 × 10 -6 ~1 × 10 -11 tor
rの真空中で900〜1200℃の範囲に昇温して、薄膜表面を平坦化しかつ薄膜を支持基板に貼合せたが、これに限らず、損傷領域で分離した厚肉部を薄膜に重ねたまま積層体を1×10 -6 〜1×10 -11 torr、好ましくは1×10 -7 〜1×10 -9 torrの真空中で900〜12 By heating to a range of 900 to 1200 ° C. in a vacuum of r, although the thin film surface was laminated a flattened and thin film support substrate, not limited to this, overlapping the thick portion separated at the damaged region to the thin film 1 × 10 -6 ~1 × 10 -11 torr laminate while, preferably in a vacuum of 1 × 10 -7 ~1 × 10 -9 torr 900~12
00℃(図2(b))、好ましくは1000〜1100 00 ° C. (FIG. 2 (b)), preferably 1000 to 1100
℃の範囲に更に昇温してこの温度範囲に30〜120分間、好ましくは40〜60分間保持することにより、薄膜表面を平坦化しかつ薄膜を支持基板に貼合せ、その後に降温して厚肉部を除去してもよい。 ℃ range further was heated 30-120 minutes in this temperature range, preferably by holding 40 to 60 minutes to planarize the thin film surface and laminating the film to the supporting substrate, thick and then cooled part may be removed. この場合、半導体基板の薄膜の分離後に降温せずに、更に900〜120 In this case, without lowering after separation of the thin film of the semiconductor substrate, further 900 to 120
0℃の範囲まで昇温するので、上記実施の形態に係るS Since the temperature is raised to the range of 0 ° C., S according to the above embodiment
OI基板の製造方法より熱処理の工数及び熱エネルギの損失を低減できる。 Loss of man-hours and thermal energy of the heat treatment than the manufacturing method of the OI substrate can be reduced.

【0017】 [0017]

【実施例】次に本発明の実施例を図面に基づいて詳しく説明する。 EXAMPLES Next will be described in detail with reference to embodiments of the present invention with reference to the drawings. <実施例1>厚さ625μmのシリコンウェーハからなる半導体基板を熱酸化して表面に厚さ400nmの熱酸化膜を形成した。 A semiconductor substrate of silicon wafer of <Example 1> thickness 625μm to form a thermal oxide film having a thickness of 400nm on the surface by thermal oxidation. この半導体基板に100keV、ドーズ量5×10 16 H/cm 2で水素イオンを注入した。 100keV on the semiconductor substrate, hydrogen ions were implanted at a dose of 5 × 10 16 H / cm 2 . 熱酸化前の上記と同一のシリコンウェーハからなる支持基板に上記半導体基板を重ね合せて積層体を形成した。 A support substrate of silicon wafer of the same before the thermal oxidation to form a laminate superposing the semiconductor substrate. 重ね合せる前にRCA法により両基板を洗浄した。 Washing the both substrates by RCA method before superposing. この積層体を1×10 -8 torrの真空中で400℃まで昇温して薄膜分離の熱処理を行った(図3(a))。 This laminate was heated to 400 ° C. in a vacuum of 1 × 10 -8 torr was subjected to a heat treatment of the thin film separation (Figure 3 (a)). この熱処理により半導体基板中の結晶の再配列及び微小気泡の圧力作用にて、半導体基板内部のイオン注入した箇所で半導体基板が割れて分離し、支持基板上に厚さ120nmの単結晶シリコンの薄膜を有するSOI基板が得られた。 At a pressure effect of rearrangement and microbubbles crystals in the semiconductor substrate by the heat treatment, separated cracked semiconductor substrate at the point where the ion-implanted in the semiconductor substrate, a thin film of single crystal silicon having a thickness of 120nm on a support substrate SOI substrate having is obtained.
このときの薄膜の厚さのばらつきは±4nmであった。 Variations in the thickness of the thin film at this time was ± 4 nm.
また薄膜表面の平均粗さRaを、測定領域を10μm角及び2μm角として、原子間力顕微鏡(以下、AFMという)によりそれぞれ測定した。 The average roughness Ra of the film surface, the measuring region of 10μm square and 2μm square, atomic force microscope (hereinafter, referred to as AFM) were measured by. この結果、測定領域が10μm角及び2μm角のときの薄膜表面の平均粗さR As a result, the average roughness R of the thin film surface when the measurement area is 10μm square and 2μm angle
aはそれぞれ6.26nm(図4(a))及び5.11n Each a 6.26nm (FIG. 4 (a)) and 5.11n
m(図4(b))であった。 Was m (Figure 4 (b)).

【0018】<実施例2>実施例1と同様にして作製した単結晶シリコンの薄膜付きの支持基板を厚肉部薄膜上に重ねたまま、実施例1と同一の真空中、即ち1×10 [0018] <Example 2> while the thin-film support substrate of single crystal silicon produced in the same manner as in Example 1 was superimposed thick portion on a thin film, in the same vacuum as in Example 1, i.e., 1 × 10
-8 torrの真空中で850℃まで昇温して、薄膜の平坦化熱処理を行った(図3(b))。 -8 torr was heated to 850 ° C. in a vacuum of, subjected to flattening heat treatment of the thin film (Figure 3 (b)). このときの薄膜の厚さは120±4nmと実施例1と殆ど変らなかった。 The thickness of the thin film at this time did not change almost a 120 ± 4 nm as in Example 1. また測定領域が10μm角及び2μm角のときの薄膜表面の平均粗さRaはAFMで測定した結果、それぞれ1.1 The measurement result region average roughness Ra of the film surface when the 10μm square and 2μm angle measured by AFM, respectively 1.1
6nm(図5(a))及び0.38nm(図5(b))であった。 Was 6 nm (FIG. 5 (a)) and 0.38 nm (Figure 5 (b)). この結果、薄膜表面の平均粗さRaは実施例1の約1/5(測定領域10μm角)及び約1/13(測定領域2μm角)となり、実施例1と比べて極めて小さくなった。 As a result, the average roughness Ra of the film surface was extremely small as compared to about one-fifth (measurement area 10μm square) and about 1/13 (measurement area 2μm square) and of Example 1, Example 1.

【0019】<比較例1>実施例1と同様にして作製した半導体基板及び支持基板の積層体を大気圧の窒素雰囲気中で450℃まで昇温して薄膜分離熱処理を行った。 [0019] <Comparative Example 1> Example 1 and then heated to up to 450 ° C. in a nitrogen atmosphere at atmospheric pressure a laminate of the semiconductor substrate and the supporting substrate prepared in the same manner was subjected to thin film separation heat treatment.
この熱処理により半導体基板内部のイオン注入した箇所で半導体基板が割れて分離し、支持基板上に厚さ120 The heat treatment by separated semiconductor substrate is cracked at a place where it has ion-implanted in the semiconductor substrate, the thickness of 120 on a support substrate
nmの単結晶シリコンの薄膜を有するSOI基板が得られた。 SOI substrate having a thin film of nm of the single crystal silicon was obtained. このときの薄膜の厚さは120±4nmと実施例1と殆ど変らなかった。 The thickness of the thin film at this time did not change almost a 120 ± 4 nm as in Example 1. また測定領域が10μm角及び2μm角のときの薄膜表面の平均粗さRaはAFMで測定した結果、それぞれ12.7nm(図6(a))及び1 The measurement result region average roughness Ra of the film surface when the 10μm square and 2μm angle measured by AFM, respectively 12.7 nm (FIG. 6 (a)) and 1
0.3nm(図6(b))であった。 Was 0.3 nm (Figure 6 (b)). この結果、薄膜表面の平均粗さRaは、測定領域が10μm角及び2μm角のいずれの場合にも、実施例1の約2倍と大きくなった。 As a result, the average roughness Ra of the film surface, measuring area is in each case a 10μm square and 2μm square and as large as about twice of Example 1.

【0020】<比較例2>比較例1と同様にして作製した単結晶シリコンの薄膜付きの支持基板を厚肉部薄膜上に重ねたまま大気圧の窒素雰囲気中で更に昇温して10 [0020] <Comparative Example 2> Comparative Example 1 and further heating in a nitrogen atmosphere at atmospheric pressure while superposed on the thin-film support substrate of single crystal silicon produced by the thick portion on a thin film similarly 10
00℃に60分間保持し、薄膜の支持基板への貼合せ熱処理を行った。 Hold 00 ° C. for 60 minutes, was subjected to lamination heat treatment to the support substrate of the thin film. このときの薄膜の厚さは120±4nm The thickness of the thin film at this time is 120 ± 4 nm
と実施例2と殆ど変らなかった。 It did not change almost as in Example 2. また測定領域が10μ 10μ The measurement area is
m角及び2μm角のときの薄膜表面の平均粗さRaはA The average roughness Ra of the film surface when the m angles and 2μm angle A
FMで測定した結果、それぞれ10.2nm(図7 Result of measurement by FM, respectively 10.2 nm (FIG. 7
(a))及び9.69nm(図7(b))であった。 (A)) and 9.69nm was (FIG. 7 (b)). この結果、薄膜表面の平均粗さRaは比較例1より僅かに改善されたが、実施例2のそれぞれ約9倍(測定領域10μ As a result, although the average roughness Ra of the film surface was slightly improved compared with Comparative Example 1, about 9-fold, respectively in Example 2 (measurement area 10μ
m角)及び約25倍(測定領域2μm角)となり、実施例2と比べて極めて大きくなった。 m square) and about 25 times (measurement area 2μm square), and was extremely large as compared with Example 2.

【0021】 [0021]

【発明の効果】以上述べたように、本発明によれば、表面に絶縁層が形成された半導体基板に水素イオンを注入して半導体基板内部に絶縁層に平行な損傷領域を形成し、半導体基板を支持基板に重ね合せて積層体を形成し、更に積層体を1×10 -6 〜1×10 -11 torrの真空中で400〜500℃の範囲に昇温して半導体基板を損傷領域で厚肉部及び薄膜に分離したので、表面粗さが良好な薄膜を得ることができる。 As described above, according to the present invention, according to the present invention, to form a damaged region parallel to the insulating layer into the semiconductor substrate by implanting hydrogen ions into a semiconductor substrate with an insulating layer formed on the surface, the semiconductor by superposing the substrate on the supporting substrate to form a laminate, the damaged region of the semiconductor substrate is heated to a range of 400 to 500 ° C. further the laminate in a vacuum of 1 × 10 -6 ~1 × 10 -11 torr in so separated the thick portion and the thin film, it is possible to surface roughness obtain good film. これは半導体基板外部の圧力を小さくできれば、薄膜分離に必要な水素イオンの微小気泡の内圧が小さて済むので、微小気泡の成長が比較的少ない状態で薄膜を分離でき、この結果、薄膜の分離面の表面粗さを小さくできるためである。 This if reduced pressure of the semiconductor substrate outside, since requires the internal pressure of the microbubbles of hydrogen ions necessary to the thin film separation is small, can separate thin film growth is relatively small state of microbubbles, as a result, separation of the thin film This is because that can reduce the surface roughness of the surface. またタッチポリッシュにより薄膜表面を研磨する必要が極めて少ないので、厚さが極めて薄い薄膜であっても薄膜の厚さ分布が大きくなることはなく、本発明のSOI基板を用いてデバイスを作製しても、デバイスの特性はばらつかない。 Since very few necessary to polish the thin film surface by touch polishing, a very thin film thickness never thickness distribution of the thin film becomes greater, and making a device using the SOI substrate of the present invention also, the characteristics of the device does not vary.

【0022】また積層体の温度を所定の温度まで下げて半導体基板の厚肉部を除去した後に、積層体を1×10 [0022] After removing the thick portion of the semiconductor substrate by lowering the temperature of the laminate to a predetermined temperature, the laminate 1 × 10
-6 〜1×10 -11 torrの真空中で900〜1200℃の範囲に昇温する熱処理を行えば、薄膜表面の平坦化と薄膜の支持基板への貼合せを同時に行うことができるので、SOI基板の製造工程への負荷を低減できる。 By performing the -6 ~1 × 10 -11 torr heat treatment temperature is raised to a range of 900 to 1200 ° C. in a vacuum of, it is possible to perform lamination of the supporting substrate planarization and thin film surface at the same time, It can reduce the load on the manufacturing process of the SOI substrate. これは極めて真空度の高い雰囲気中で700℃まで昇温すると、半導体基板に注入された水素イオンの薄膜からの脱離が完了して薄膜の表面粗さが小さくなり、薄膜と支持基板との貼合せ熱処理は通常900〜1200℃の範囲で行われるためである。 When this is heated to 700 ° C. at a very in high vacuum atmosphere, the implanted hydrogen ions into the semiconductor substrate detachment from thin is complete becomes small surface roughness of the thin film, thin film and the supporting substrate and the combined heat treatment lamination is because usually carried out in the range of 900 to 1200 ° C.. 更に損傷領域で分離した厚肉部を薄膜に重ねたまま積層体を1×10 -6 〜1×10 -11 t Further 1 × 10 -6 laminate while overlapping thick portions separated at the damaged region to the thin film to 1 × 10 -11 t
orrの真空中で900〜1200℃の範囲に更に昇温して、薄膜表面を平坦化しかつ薄膜を支持基板に貼合せた後に、降温して厚肉部を除去すれば、薄膜分離熱処理後に一旦降温する上記SOI基板の製造方法より熱処理の工数及び熱エネルギの損失を低減できる。 Further raising the temperature to a range of 900 to 1200 ° C. in a vacuum of orr, the thin film surface after the lamination of the flattened and thin film support substrate, by removing the thick portion was lowered, once after the thin film separation thermal treatment It can reduce the loss of man-hours and thermal energy of the heat treatment than the manufacturing method of the SOI substrate to be cooled.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明実施形態のSOI基板の製造方法を工程順に示す図。 It shows a manufacturing method in process order of the SOI substrate of the present invention; FIG embodiment.

【図2】(a)はそのSOI基板の熱処理温度条件を示す図。 Figure 2 (a) is a diagram showing a heat treatment temperature of the SOI substrate. (b)は別の実施形態のSOI基板の熱処理温度条件を示す図。 (B) is a diagram showing a heat treatment temperature of the SOI substrate of another embodiment.

【図3】(a)は本発明の実施例1のSOI基板の熱処理温度条件を示す図。 3 (a) is a diagram showing a heat treatment temperature of the SOI substrate of Example 1 of the present invention. (b)は本発明の実施例2のSOI基板の熱処理温度条件を示す図。 (B) is a diagram showing a heat treatment temperature of the SOI substrate of Example 2 of the present invention.

【図4】(a)は本発明の実施例1を示し、400℃に加熱して半導体基板を損傷領域で分離した直後の薄膜表面を、AFMにより測定領域を10μm角として示す図。 4 (a) shows a first embodiment of the present invention, showing a thin film surface immediately after separating the semiconductor substrate at the damaged region by heating to 400 ° C., the measuring region of 10μm square by AFM.
(b)は本発明の実施例1を示し、400℃に加熱して半導体基板を損傷領域で分離した直後の薄膜表面を、AF (B) shows a first embodiment of the present invention, the thin film surface immediately after separating the semiconductor substrate at the damaged region by heating to 400 ° C., AF
Mにより測定領域を2μm角として示す図。 It shows a measuring region of 2μm square by M.

【図5】(a)は本発明の実施例2を示し、400℃に加熱して半導体基板を損傷領域で分離し更に850℃まで加熱した直後の薄膜表面を、AFMにより測定領域を1 5 (a) shows a second embodiment of the present invention, the thin film surface immediately after heating to separate further 850 ° C. The semiconductor substrate at the damaged region by heating to 400 ° C., a measurement region by AFM 1
0μm角として示す図。 It shows as 0μm angle. (b)は本発明の実施例2を示し、400℃に加熱して半導体基板を損傷領域で分離し更に850℃まで加熱した直後の薄膜表面を、AFMにより測定領域を2μm角として示す図。 (B) shows a second embodiment of the present invention, showing a thin film surface immediately after heating to separate further 850 ° C. in the damaged region of the semiconductor substrate is heated to 400 ° C., the measuring region of 2μm square by AFM.

【図6】(a)は比較例1を示し、450℃に加熱して半導体基板を損傷領域で分離した直後の薄膜表面を、AF [6] The (a) shows a comparative example 1, a thin film surface immediately after separating the semiconductor substrate at the damaged region by heating to 450 ° C., AF
Mにより測定領域を10μm角として示す図。 It shows a measuring region of 10μm square by M. (b)は比較例1を示し、450℃に加熱して半導体基板を損傷領域で分離した直後の薄膜表面を、AFMにより測定領域を2μm角として示す図。 (B) shows a comparative example 1, shows a thin film surface immediately after separating the semiconductor substrate at the damaged region by heating to 450 ° C., the measuring region of 2μm square by AFM.

【図7】(a)は比較例2を示し、450℃に加熱して半導体基板を損傷領域で分離し更に1000℃まで加熱した直後の薄膜表面を、AFMにより測定領域を10μm 7 (a) shows a comparative example 2, the thin film surface immediately after heating to separate further 1000 ° C. the semiconductor substrate at the damaged region by heating to 450 ° C., 10 [mu] m measurement region by AFM
角として示す図。 It shows as a corner. (b)は比較例2を示し、450℃に加熱して半導体基板を損傷領域で分離し更に1000℃まで加熱した直後の薄膜表面を、AFMにより測定領域を2μm角として示す図。 (B) shows a comparative example 2, it shows a thin film surface immediately after heating to separate further 1000 ° C. in the damaged region of the semiconductor substrate is heated to 450 ° C., the measuring region of 2μm square by AFM.

【符号の説明】 DESCRIPTION OF SYMBOLS

11 半導体基板 11a 酸化層(絶縁層) 11b 損傷領域 11c 厚肉部 11d 薄膜 12 支持基板 13 積層体 14 SOI基板 11 semiconductor substrate 11a oxide layer (insulating layer) 11b damaged region 11c thick portion 11d thin film 12 supporting substrate 13 laminate 14 SOI substrate

【手続補正書】 [Procedure amendment]

【提出日】平成9年5月29日 [Filing date] 1997 May 29,

【手続補正1】 [Amendment 1]

【補正対象書類名】図面 [Correction target document name] drawings

【補正対象項目名】図4 [Correction target item name] FIG. 4

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【図4】 [Figure 4]

【手続補正2】 [Amendment 2]

【補正対象書類名】図面 [Correction target document name] drawings

【補正対象項目名】図5 [Correction target item name] FIG. 5

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【図5】 [Figure 5]

【手続補正3】 [Amendment 3]

【補正対象書類名】図面 [Correction target document name] drawings

【補正対象項目名】図6 [Correction target item name] FIG. 6

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【図6】 [Figure 6]

【手続補正4】 [Amendment 4]

【補正対象書類名】図面 [Correction target document name] drawings

【補正対象項目名】図7 [Correction target item name] FIG. 7

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【図7】 [7]

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 表面に絶縁層(11a)が形成された半導体基板(11)に水素イオンを注入して前記半導体基板(11)内部に前記絶縁層(11a)に平行な損傷領域(11b)を形成する工程と、 前記半導体基板(11)を支持基板(12)に重ね合せて積層体 1. A dielectric surface layer (11a) above with hydrogen ions are implanted into the semiconductor substrate (11) formed in the semiconductor substrate (11) said insulating layer inside (11a) parallel to damaged areas (11b) forming a said superposition and laminate semiconductor substrate (11) a supporting substrate (12)
    (13)を形成する工程と、 前記積層体(13)を1×10 -6 〜1×10 -11 torrの真空中で400〜500℃の範囲に昇温して前記半導体基板 Forming a (13), the temperature was raised to a range of 400 to 500 ° C. in a vacuum of the laminate (13) was 1 × 10 -6 ~1 × 10 -11 torr semiconductor substrate
    (11)を前記損傷領域(11b)で厚肉部(11c)及び薄膜(11d) Thick portion in the damaged region (11) (11b) (11c) and the thin film (11d)
    に分離する工程とを含むSOI基板の製造方法。 The method for manufacturing an SOI substrate and a step of separating the.
  2. 【請求項2】 積層体(13)の温度を所定の温度まで下げて半導体基板(11)の厚肉部(11c)を除去した後に、前記積層体(13)を1×10 -6 〜1×10 -11 torrの真空中で900〜1200℃の範囲に昇温して薄膜(11d)表面を平坦化しかつ前記薄膜(11d)を支持基板(12)に貼合せる請求項1記載のSOI基板の製造方法。 2. After removing the thick portion of the semiconductor substrate (11) and (11c) to lower the temperature to a predetermined temperature of the stack (13), the laminate (13) was 1 × 10 -6 to 1 × 10 -11 torr SOI substrate by heating to a range of 900 to 1200 ° C. in a vacuum thin film (11d) the surface was flattened and is laminated to the thin film (11d) to the supporting substrate (12) according to claim 1 the method of production.
  3. 【請求項3】 損傷領域で分離した厚肉部を薄膜に重ねたまま積層体を1×10 -6 〜1×10 -11 torrの真空中で900〜1200℃の範囲に更に昇温して、前記薄膜表面を平坦化しかつ前記薄膜を支持基板に貼合せた後に、降温して前記厚肉部を除去する請求項1記載のSO 3. A further raising the temperature to a range of 900 to 1200 ° C. The separated thick portion remains laminate was overlaid on the thin film in a vacuum of 1 × 10 -6 ~1 × 10 -11 torr in the damaged region and planarizing the film surface and after laminated with the thin film to the supporting substrate, SO of claim 1, wherein the cooling is removed by the thick portion
    I基板の製造方法。 Manufacturing method of I board.
JP13903197A 1997-05-29 1997-05-29 Soi substrate manufacturing method of Expired - Fee Related JP3412449B2 (en)

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EP0977255A2 (en) * 1998-07-07 2000-02-02 Shin-Etsu Handotai Company Limited A method of fabricating an SOI wafer and SOI wafer fabricated by the method
EP1085562A2 (en) * 1999-09-17 2001-03-21 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
WO2001028000A1 (en) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Method for manufacturing soi wafer, and soi wafer
WO2001073848A1 (en) * 2000-03-27 2001-10-04 Shin-Etsu Handotai Co., Ltd. Production method for bonding wafer and bonding wafer produced by this method
JP2005072043A (en) * 2003-08-26 2005-03-17 Shin Etsu Handotai Co Ltd Method for manufacturing laminated wafer, and soi wafer
JP2007027448A (en) * 2005-07-19 2007-02-01 Matsushita Electric Works Ltd Semiconductor light emitting device, lighting device using same, and method of manufacturing same
KR100730806B1 (en) 1999-10-14 2007-06-20 신에쯔 한도타이 가부시키가이샤 Method for manufacturing soi wafer, and soi wafer
JP2008028415A (en) * 1999-10-14 2008-02-07 Shin Etsu Handotai Co Ltd Method for manufacturing soi wafer, and soi wafer
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US6306730B2 (en) 1998-07-07 2001-10-23 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer and SOI wafer fabricated by the method
EP0977255A3 (en) * 1998-07-07 2001-02-07 Shin-Etsu Handotai Company Limited A method of fabricating an SOI wafer and SOI wafer fabricated by the method
EP0977255A2 (en) * 1998-07-07 2000-02-02 Shin-Etsu Handotai Company Limited A method of fabricating an SOI wafer and SOI wafer fabricated by the method
US6245645B1 (en) 1998-07-07 2001-06-12 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer
EP1085562A2 (en) * 1999-09-17 2001-03-21 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
EP1085562A3 (en) * 1999-09-17 2004-06-09 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
JP2008028415A (en) * 1999-10-14 2008-02-07 Shin Etsu Handotai Co Ltd Method for manufacturing soi wafer, and soi wafer
KR100730806B1 (en) 1999-10-14 2007-06-20 신에쯔 한도타이 가부시키가이샤 Method for manufacturing soi wafer, and soi wafer
US6846718B1 (en) 1999-10-14 2005-01-25 Shin-Etsu Handotai Co., Ltd. Method for producing SOI wafer and SOI wafer
US7176102B2 (en) 1999-10-14 2007-02-13 Shin-Etsu Handotai Co., Ltd. Method for producing SOI wafer and SOI wafer
WO2001028000A1 (en) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Method for manufacturing soi wafer, and soi wafer
WO2001073848A1 (en) * 2000-03-27 2001-10-04 Shin-Etsu Handotai Co., Ltd. Production method for bonding wafer and bonding wafer produced by this method
JP2005072043A (en) * 2003-08-26 2005-03-17 Shin Etsu Handotai Co Ltd Method for manufacturing laminated wafer, and soi wafer
JP4581348B2 (en) * 2003-08-26 2010-11-17 信越半導体株式会社 Method for manufacturing bonded wafer and SOI wafer
JP2007027448A (en) * 2005-07-19 2007-02-01 Matsushita Electric Works Ltd Semiconductor light emitting device, lighting device using same, and method of manufacturing same
JP4508021B2 (en) * 2005-07-19 2010-07-21 パナソニック電工株式会社 Manufacturing method of semiconductor light emitting device
JP2010522980A (en) * 2007-03-29 2010-07-08 エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ Improvement of thin layer quality by high temperature thermal annealing.
KR101423078B1 (en) * 2007-03-29 2014-07-25 소이텍 Improving the quality of a thin layer through high-temperature thermal annealing
JP2009283582A (en) * 2008-05-21 2009-12-03 Nagano Electronics Industrial Co Ltd Bonded wafer manufacturing method and bonded wafer
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