CN114975096A - Bonding material and preparation method thereof, and semiconductor device - Google Patents
Bonding material and preparation method thereof, and semiconductor device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60015—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using plate connectors, e.g. layer, film
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Abstract
The invention discloses a bonding material, a preparation method and a semiconductor device. The method comprises the following steps: implanting H-containing ions at one side of a first substrate, wherein the first substrate is formed by non-silicon crystal materials; forming a bonding enhancement layer at least one of the first substrate and the second substrate surface; bonding the first substrate and the second substrate, and enabling the bonding enhancement layer to be located at a bonding interface to form a first bonding structure; and carrying out first annealing treatment on the first bonding structure to enable the first bonding structure to be stripped from the inside of the first substrate so as to obtain the bonding material with the second substrate. Thus, the method can easily obtain a bonding material, can obtain high bonding strength without a long-time high-temperature treatment, and is particularly suitable for forming a bonding material of SiC-SiC or other materials.
Description
Technical Field
The invention relates to the field of semiconductor technology and semiconductor manufacturing, in particular to a bonding material, a preparation method and a semiconductor device.
Background
In recent years, with the development of semiconductor technology, semiconductor devices based on semiconductor substrates of silicon (Si) materials and silicon carbide (SiC), gallium arsenide, indium phosphide, and the like have been rapidly developed. Taking SiC material as an example, SiC has a wider band gap, a higher breakdown electric field, a faster carrier saturation rate, a higher thermal conductivity, and other advantages compared with Si material, and for example, these excellent characteristics of SiC can make a semiconductor device smaller in volume, lower in loss, higher in operating temperature, higher in frequency, and simpler in heat dissipation. While 6 inch single crystal 4H type silicon carbide wafers and many types of silicon carbide devices such as schottky diodes, Bipolar Junction Transistors (BJTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs) are currently available on the market, the preparation of high quality SiC substrate materials remains challenging:
the SiC material has no fixed melting point, and a commonly used method for preparing SiC single crystals is Physical Vapor Transport (PVT). When the SiC single crystal is grown by the PVT method, the process window is narrow, the obtained SiC crystal has high defect density and low yield. Especially for large-size SiC crystals, the larger the size is, the narrower the process window is, the lower the yield is, and the more difficult the defect density is to control; in addition, the hardness of the silicon carbide material is high, the wafer processing is difficult, and the processing cost is high. Therefore, high quality silicon carbide wafers of large diameter (6 inches and above in diameter), low defect density are not readily available and are expensive.
Direct bonding of SiC wafers is also very difficult. Since the reaction of Si and C to form Si-C bonds requires very high temperatures, the Si-C bonds are very stable, so that the surface activity of SiC crystals is very poor. When the SiC wafer is directly bonded, the bonding interface is not easy to directly form Si-C bonds, and the bonding strength is low. Meanwhile, the SiC material has high hardness and poor plasticity, and a bonding interface is not easy to attach even if the SiC material is directly bonded under high pressure, so that a cavity is easily formed on the bonding interface. There are technical difficulties in preparing SiC wafers by direct bonding.
Therefore, the current bonding materials and preparation methods still need to be improved.
Disclosure of Invention
The present invention is made based on the discovery and recognition by the inventors of the following facts and problems:
as mentioned above, the preparation of the substrate materials such as high quality SiC crystal and the like has certain process difficulty at present. Taking SiC materials as an example, mass production is very important for high efficiency and low cost, however, large size, low cost, high crystal quality SiC crystal materials are difficult to obtain. Under the same breakdown voltage, the silicon carbide device can be 10 times thinner than a corresponding silicon device, in a conventional silicon carbide device, the thickness of an electrical control effective layer is in the range of more than ten microns and even a few microns, the part of the electrical effective layer requires silicon carbide with high crystal quality, most of the thickness of a silicon carbide substrate with the thickness of hundreds of microns mainly plays the roles of mechanical support and electrical conduction, and the part of the mechanically supported silicon carbide does not have the requirement on the crystal quality. Sometimes, in order to improve the electrical performance, the mechanically supported silicon carbide needs to be thinned, and the thinner the silicon carbide, the better the electrical performance of the device. Based on this, bonding high quality silicon carbide wafers to low cost substrates may be a viable solution to reduce the cost of silicon carbide wafers. In order to withstand the high temperature processes during device processing and avoid contamination, it is preferable to bond high quality silicon carbide wafers directly to low cost silicon carbide substrates. However, SiC direct bonding has the disadvantages of low bonding strength, poor interface quality, and the like, and SiC-SiC direct bonding methods commonly used in the related art are all operated at high vacuum and high temperature, and a large thermal stress is generated during the bonding process, and the poor bonding interface also affects the performance of devices (mainly power devices such as MOSFETs, Insulated Gate Bipolar Transistors (IGBTs), Schottky Barrier Diodes (SBDs), and the like having a vertical structure) manufactured by using the SiC-SiC direct bonding method. Therefore, if a bonding process with a lower temperature and a simple process can be adopted to obtain a bonding material with high quality, the development of devices based on the semiconductor material is facilitated.
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
In one aspect of the invention, a method of preparing a bonding material is provided. The method comprises the following steps: implanting H-containing ions at one side of a first substrate, wherein the first substrate is formed by non-silicon crystal materials; forming a bonding enhancement layer at least one of the first substrate surface and the second substrate surface; bonding the first substrate and the second substrate, and enabling the bonding enhancement layer to be located at a bonding interface to form a first bonding structure; and carrying out first annealing treatment on the first bonding structure to enable the first bonding structure to be stripped from the inside of the first substrate so as to obtain the bonding material with the second substrate. Therefore, the method can simply obtain the bonding material, does not need long-time high-temperature treatment, obtains high bonding strength with the help of the bonding enhancement layer, and is particularly suitable for forming the bonding material of SiC-SiC and other materials.
According to the embodiment of the present invention, the bonding enhancement layer is formed at least on the first substrate, and the bonding enhancement layer is formed on the surface of the side of the first substrate where the H-containing ions are implanted, or the H-containing ions are implanted into the surface after the bonding enhancement layer is formed on the surface of the side of the first substrate.
According to an embodiment of the present invention, the first substrate is a SiC single crystal material satisfying a basal plane dislocation density of not higher than 1500/cm 2 . Thereby, a high-quality SiC single crystal surface layer of high crystal quality can be provided for the bonding material.
According to an embodiment of the invention, the second substrate is a SiC material and the crystalline quality of the SiC material of the first substrate is better than the crystalline quality of the SiC material of the second substrate. Thus, by using a low-cost second substrate material, it is advantageous to reduce the cost of the bonding material.
According to an embodiment of the present invention, the bonding enhancement layer is an amorphous layer. The surface of the amorphous layer has strong chemical activity and is easy to bond, so that the bonding strength of the first substrate and the second substrate is improved.
According to the embodiment of the invention, the amorphous layer is obtained by one or two methods of magnetron sputtering and ion implantation. Magnetron sputtering and ion implantation are inexpensive, and thus, an amorphous bonding enhancement layer can be obtained simply.
According to an embodiment of the invention, the magnetron sputtered material is silicon carbide. Thus, an amorphous bonding enhancement layer can be obtained easily.
According to an embodiment of the invention, the ion implantation comprises at least one of plasma source ion implantation and plasma immersion ion implantation. Therefore, high injection dosage can be easily obtained, so that the surface is easy to amorphize, and the bonding strength is favorably improved.
According to an embodiment of the invention, the ion implanted elements comprise one or more of Si, C, Al, B, Ga, N, P, As, Sb. Si and C are elements of silicon carbide per se, and do not introduce additional pollution, while Al, B, Ga, N, P, As and Sb are semiconductor dopants of SiC materials, and can be beneficial to forming a P-type or N-type semiconductor conducting layer.
According to an embodiment of the invention, the bonding enhancing layer is electrically conductive. Therefore, the purpose of reducing the bonding difficulty of the first substrate and the second substrate is achieved, and meanwhile, the obtained bonding material is favorable for preparing devices with vertical structures, such as MOSFETs, IGBTs and SBDs with the vertical structures.
According to an embodiment of the invention, the bonding enhancement layer comprises a metal silicide. The metal silicide has good conductivity, and the performance of the bonding material can be further improved.
According to an embodiment of the present invention, the metal silicide is one or more of nickel silicide, tungsten silicide, molybdenum silicide, titanium silicide, and tantalum silicide. The silicide is high temperature resistant, and can realize conductivity without introducing excessive contamination to cause device performance reduction.
According to an embodiment of the present invention, performing the H-containing ion implantation on the first substrate having the side of the bonding enhancement layer after forming the bonding enhancement layer comprises: and forming metal layers on one side surface of the first substrate and one side surface of the second substrate, and performing second annealing treatment on the first substrate and the second substrate with the metal layers on the surfaces to form metal silicide. Thereby, the bonding strength of the formed bonding enhancement layer and the substrate is advantageously improved.
According to the embodiment of the invention, the metal silicide is deposited and formed on one side surface of the first substrate and one side surface of the second substrate. Thereby, the properties of the bonding material obtained by the method can be further improved.
According to an embodiment of the invention, the metal silicide is formed by magnetron sputtering, ion beam assisted deposition or pulsed laser deposition. Thus, a metal silicide can be obtained easily.
According to an embodiment of the present invention, forming the bonding enhancement layer further comprises further including a metallic conductive sub-layer on the surface of the metal silicide. The bonding between the metal conductive sublayers is easy to obtain a good bonding interface and high bonding strength after high-temperature treatment, so that the bonding strength of the bonding material can be further improved.
According to an embodiment of the invention, the bonding enhancing layer is an n-type conductive layer. The n-type conducting layer is beneficial to preparing devices with vertical structures such as n-MOSFET, SBD and IGBT by using the bonding material, so that the performance of the bonding material obtained by the method can be further improved.
According to an embodiment of the invention, the implantation dose of the H-containing ion implantation is not less than 5 ANGSTROM 10 15 cm -2 . Therefore, the method can be used for realizing clean and complete stripping at the position corresponding to the implantation depth of the H-containing ion implantation.
According to an embodiment of the present invention, the first bonding structure is subjected to a third annealing treatment before the first annealing treatment, the third annealing treatment being at a lower temperature than the first annealing treatment. Therefore, the bonding strength can be further enhanced, the interface quality is improved, and the bonding interface is prevented from being split due to insufficient bonding strength in the first annealing treatment process.
In another aspect of the invention, a bonding material is provided. The bonding material is obtained by the method described above. The bonding material thus has all the features and advantages of the bonding material obtained by the method described above, which are not described in detail herein. For example, the bonding material has at least one of the advantages of low production cost, short production period, high bonding strength, good interface performance, suitability for preparing high-performance semiconductor devices and the like.
In another aspect of the present invention, a semiconductor device is presented. The semiconductor device includes the aforementioned bonding material. Thus, the semiconductor has all the features and advantages of the bonding material described above, and will not be described herein again.
According to an embodiment of the present invention, the semiconductor device is an IGBT, a MOSFET, or an SBD having a vertical structure.
Drawings
FIG. 1 is a schematic flow diagram of a method of fabricating a bonded structure according to one embodiment of the invention;
FIG. 2 is a schematic flow diagram of a portion of a method of fabricating a bonded structure according to one embodiment of the invention;
FIG. 3 is a schematic flow diagram of a method of fabricating a bonded structure according to another embodiment of the invention;
fig. 4 is a flow chart illustrating a method of fabricating a bonded structure according to yet another embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In one aspect of the invention, a method of preparing a bonding material is provided. According to the method, the bonding enhancement layer is arranged on the surface of the substrate, so that the bonding material can be simply and conveniently obtained based on an intelligent-cut (smart-cut) process. The method is particularly suitable for the structural preparation of non-silicon crystal materials, such as SiC, GaN, InP, diamond, AlN and other semiconductor substrate materials with higher wafer cost, higher hardness or difficult bonding, and can simply, conveniently and quickly obtain bonding materials with high-quality interfaces (no interface cavity and high bonding strength). According to some aspects of the present invention, the substrate may be formed of gallium arsenide, indium phosphide, Si, SiC, or the like, and according to still other embodiments of the present invention, the first and second substrates may be formed of a material having a hardness higher than that of a silicon crystal material.
The inventors have found that although a bonding structure such as SOI (semiconductor on insulator) can be obtained by using a smart-cut process in conventional semiconductor substrate bonding, the above bonding structure requires the use of an insulator as an interface before bonding, such as silicon dioxide and silicon bonding. Silicon and oxygen have larger electronegativity difference, the interface is easy to bond, silicon and oxygen are combined at lower temperature to form Si-O bond, the direct bonding difficulty of silicon-silicon is larger, and the direct bonding of silicon carbide and silicon carbide crystal is also difficult. Then, when a bonding structure based on SiC or other materials for manufacturing a high-performance semiconductor device is to be formed, silicon dioxide as a bonding interface brings some unavoidable defects: the silicon dioxide material is non-conductive and has certain influence on the subsequent semiconductor structure and performance; meanwhile, silicon dioxide begins to soften at 1200 ℃, which is unacceptable for device processing technologies such as SiC devices which require 1600-1800 ℃. Therefore, one aspect of the present invention is to form a bond enhancing layer and achieve high performance bond material based on H-containing ion implantation and subsequent annealing process stripping.
The inventors have conducted extensive studies and extensive experiments to find that Surface Activated Bonding (SAB) is an advantageous method for achieving bonding at room temperature. The principle of SAB is that the bonded surfaces are activated by argon (Ar) atom or ion beam bombardment in a high voltage environment, clearing surface contaminants for the subsequent bonding of two substrates, after which the substrate surfaces to be bonded become active and they spontaneously form chemical bonds with each other even at room temperature. This approach has been successfully applied to room temperature bonding of metals, silicon and some III-V semiconductors. However, the method (SAB) still has the difficulties in obtaining SiC-SiC bonding, and has the disadvantages of harsh bonding conditions and insufficient bonding strength. In order to realize the application of the low-cost SiC power device (for example, SBD based on a SiC substrate, MOSFET, IGBT device, etc., hereinafter all take IGBT as an example), the invention finds that the SiC-SiC bonding interface is inserted with a middle high-temperature resistant conductive material in situ or generates an amorphous SiC interface through surface activation treatment to improve the activity of the bonding interface layer in consideration of the conductivity of the SiC-SiC bonding interface, thereby realizing the SiC-SiC bonding under a mild environment. And the inventors have found that the method according to embodiments of the invention can also effectively remove SiC surface particle contamination and surface oxides while maintaining stringent cleanliness, surface roughness and process uniformity requirements so that the resulting bonded structure can be tailored to the requirements of high quality semiconductor devices. Finally, a bonding interface with sufficient bonding strength and minimal void area can be obtained at lower bonding temperatures.
The above-described method is described in detail below with reference to specific examples of the present invention. Referring to fig. 1, the method may include:
s100: implanting H-containing ions on one side of the first substrate
According to an embodiment of the invention, an H-containing ion implantation is performed at one side of the first substrate in this step. In the present invention, the first and second substrates are only used to distinguish the two substrates forming the bonding material, and the materials of the two substrates may be the same or different. In some embodiments of the invention, the first substrate may have a better crystal quality than the second substrate. Therefore, the first substrate can be used for providing a surface layer with excellent crystal quality for the bonding material, and the second substrate can be formed by adopting a material with lower cost, so that the production cost can be reduced on the premise of not influencing the performance of the bonding material.
For example, according to some embodiments of the present invention, the first substrate may be a SiC single crystal material. Thereby, a high-quality single crystal surface layer can be provided for the bonding material. According to some specific embodiments of the present invention, the SiC single crystal material satisfies a basal plane dislocation (EPD) density of not higher than 1500/cm 2 . Alternatively, at least one of the following conditions is satisfied: the density of the micro-tube is not higher than 0.5/cm 2 Screw Dislocation (TSD) density:<1000/cm 2 edge Dislocation (TED) density:<8000/cm 2 。
it should be noted that, the aforementioned "first substrate may have a better crystal quality than the second substrate", and particularly, the second substrate is lower than the aforementioned first substrate in the crystal parameter. For example, according to some embodiments of the invention, the second substrate may be amorphous or polycrystalline.
According to the embodiment of the present invention, the implantation dose for performing the H-containing ion implantation in this step is not particularly limited, and may be, for example, not less than 5 ANGSTROM 10 15 cm -2 . Therefore, the method can be used for realizing clean and complete stripping at the corresponding position of the implantation depth of the H-containing ion implantation in the subsequent first annealing treatment process. For example, according to some specific examples of the invention, room temperature or high temperature (≦ 600 degrees Celsius) H may be performed on a single crystal n/p type SiC substrate + Or contain H + Implanting at an implant dose of 1 ﹡ 10 16 ～1﹡10 17 cm -2 Left and right, specifically 2 ﹡ 10 16 The injection angle may be 0 degrees. The injection energy in the step can be dozens of keV to several MeV, and can be selected according to the required stripping depth, different injection energies can finally obtain different thicknesses of the high-quality SiC film, and the injection depth can be in the range of dozens of nanometers to dozens of micrometers.
S200: forming a bonding enhancement layer at least one of the first and second substrate surfaces
According to an embodiment of the invention, a bonding enhancement layer is formed in this step. According to some preferred embodiments of the present invention, a bonding enhancement layer may be formed on both substrate surfaces. For example, referring to fig. 3, a first bonding enhancement layer 110 may be formed on the side of the first substrate 100 implanted with H ions, and a second bonding enhancement layer 210 may be formed on a side surface of the second substrate 200. Thereby, it is advantageous to enhance the bonding strength of the two substrates in the subsequent step.
According to some embodiments of the invention, the bonding enhancing layer may be a conductive layer. This makes it possible, on the one hand, to increase the bonding activity of the first and second substrates and, on the other hand, to not affect the properties of the finally formed bonding material, for example, for SiC substrates, without introducing, for example, SiO 2 Etc. insulating material. That is, the conductive bonding enhancement layer can achieve the purpose of reducing the bonding difficulty of the first substrate and the second substrate, and is beneficial to maintaining the quality of the surface interface of the first substrate, and meanwhile, is beneficial to preparing devices with vertical structures, such as a MOSFET, an IGBT and an SBD with vertical structures, by using the obtained bonding material.
According to further embodiments of the present invention, the bond enhancing layer may be an amorphous layer. The amorphous layer has strong surface chemical activity and is easy to bond, and bonding at low temperature (lower than 600 ℃) is particularly facilitated, so that the bonding strength of the first substrate and the second substrate is improved. For example, the bonding enhancement layer may be an amorphous layer, and the first and second bonding enhancement layers may be conductive amorphous layers. The thickness of the amorphous layer is not particularly limited and may be in the range of 1 to 1000 nm. Specifically, the amorphous layer may be obtained by one or both of magnetron sputtering and ion implantation. Thus, an amorphous bonding enhancement layer can be obtained easily.
According to the embodiment of the invention, the bonding enhancement layer can be formed by utilizing magnetron sputtering, for example, the material of the magnetron sputtering can be silicon carbide, and therefore, the amorphous bonding enhancement layer can be simply obtained. For another example, the material for magnetron sputtering may be silicon carbide having a low resistivity, and thus a conductive amorphous bonding enhancement layer can be easily obtained.
Ion implantation may also be used to form the bond enhancing layer according to some preferred embodiments of the present invention. For example, the ion implantation may be performed by conventional ion implantation, or may be performed by plasma source ion implantation, plasma immersion ion implantation, or the like. Therefore, high implantation dosage can be easily obtained, so that the surface is easy to amorphize, and the bonding strength is favorably improved. According to an embodiment of the present invention, the ion-implanted element is not particularly limited and may be selected according to the material of the bonding enhancing layer to be formed. Specifically, one or more of Si, C, Al, B, Ga, N, P, As, Sb may be included. Si and C are elements of silicon carbide per se, and do not introduce additional pollution, while Al, B, Ga, N, P, As and Sb are semiconductor dopants of SiC materials, and can be beneficial to forming a P-type or N-type semiconductor conducting layer. Thereby, the quality of the bonding material obtained by the method can be further improved.
According to an embodiment of the present invention, the material forming the bonding enhancement layer may include a metal silicide. Specifically, the metal silicide may be one or more of nickel silicide, tungsten silicide, molybdenum silicide, titanium silicide, and tantalum silicide. The metal silicide has good conductivity, meets the conductivity requirement on one hand, and can better enhance the bonding strength of the substrates on two sides without reducing the interface quality of the substrates on the other hand. The thickness of the metal silicide is not particularly limited and may be in the range of 1 to 100 nm.
According to an embodiment of the present invention, forming the bonding enhancement layer may further include an operation of further including a metal conductive sub-layer on the surface of the metal silicide. The bonding between the metal conductive sublayers is easy to obtain a good bonding interface and high bonding strength after subsequent annealing treatment, and compared with silicide, the metal is easier to enable the interface to be bonded, so that the bonding strength can be further improved. In order to be compatible with subsequent epitaxy and device processing technologies and improve the performance of a semiconductor device prepared by the bonding structure, high-temperature-resistant metals such as lanthanum (La), tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), rhodium (Rh) and the like can be selected. The melting point of the conductive layer materials is above 1800 ℃, the conductive layer materials can resist high temperature, the thickness is ultrathin, the thickness is only within 10nm, and the thinner the conductive layer materials are, the better the conductive layer materials are. The ultra-thin metal can not cause serious diffusion and contamination in the silicon carbide, and can meet the requirement of subsequent device processing.
The bonding enhancement layer may include metal and metal silicide conductive layers, and may be n-type or p-type semiconductor conductive materials, depending on the method of formation. The amorphous layer can be formed into N-or p-type semiconductor conductive material simply by implanting ions differently. For example, according to some preferred embodiments of the present invention, the bonding enhancement layer formed by the amorphous layer may be an n-type conductive amorphous layer. On one hand, the n-type conductive structure is more applied, such as a schottky diode can be formed, and the n-type conductive structure can also be used as a field stop layer in an IGBT or a MOSFET, particularly, the n-type conductive layer with low resistivity is very suitable for forming the field stop layer, and the lower the resistivity is, the more the device performance is improved. Thus, the bonding enhancement layer of the n-type conductive amorphous layer may on the one hand provide good bonding conditions for the method and on the other hand the structure itself may also function well when the bonding material is used for the preparation of semiconductor devices.
According to some embodiments of the present invention, a metal silicide may be deposited directly on one side surface of the first substrate and one side surface of the second substrate as a bonding enhancement layer. Thereby, the properties of the bonding material obtained by the method can be further improved. In particular, the metal silicide may be formed by magnetron sputtering, ion beam assisted deposition, or pulsed laser deposition. Thus, a metal silicide can be obtained easily.
According to other embodiments of the present invention, the order of the operations of forming the bonding enhancement layer on the first substrate and performing the H-containing ion implantation may be interchanged. Referring to fig. 2 and 4, the H-containing ion implantation may be performed on the substrate (first substrate) having one side of the bonding enhancement layer after the bonding enhancement layer (e.g., the first bonding enhancement layer 110 shown in fig. 4) is formed. For example, when a metal material is formed and then a metal silicide is obtained by the second annealing as the bonding enhancement layer, since the temperature of forming the metal silicide by the second annealing is higher than the temperature of the first annealing and the peeling of the first substrate in the subsequent steps, it is necessary to complete the bonding enhancement layer before the implantation of the H-containing ions.
Specifically, for example, a metal layer may be formed on both of one side surface of the first substrate and one side surface of the second substrate (S1 step shown in fig. 2), followed by second annealing of the first substrate and the second substrate having the metal layer on the surface thereof to form a metal silicide (S2 step shown in fig. 2). Subsequently, the first substrate with the bonding enhancement layer is subjected to an H-containing ion implantation. According to some specific embodiments of the present invention, a Ni metal layer may be formed on the surfaces of the first and second silicon carbide substrates by magnetron sputtering, then a second annealing treatment is performed at 1100 degrees celsius to form a nickel-silicon compound, then a surface Ar ion sputtering is performed to remove a carbon deposition layer formed on the surface during the second annealing treatment, and then hydrogen-containing ion implantation is performed on the first substrate having the nickel-silicon compound as a bonding enhancement layer. Thereby, the bonding strength of the formed bonding enhancement layer and the substrate is advantageously improved. The inventor finds that the bonding strength of the metal silicide formed by the second annealing and the substrate is higher, and the subsequent preparation of the semiconductor device is facilitated.
S300: bonding the first substrate and the second substrate to form a first bonded structure
According to an embodiment of the present invention, the operation of the bonding process is performed in this step. For example, referring to fig. 3 and 4, a first bond structure 300 may be formed in this step. According to some specific embodiments of the present invention, two SiC substrates sputtered with the bonding enhancement layer may be directly bonded in a vacuum chamber at normal temperature, and the vacuum degree of the chamber may be < 5 × 10 -8 mbar。
Since the bonding enhancement layer is advantageously formed in the above step, the bonding process in this step can be performed under mild conditions at room temperature or at a relatively low temperature (less than 600 degrees celsius). Thus, a bonded body of a SiC-SiC material which is difficult to bond can be obtained easily.
According to some embodiments of the present invention, a surface activation treatment may be performed before bonding in this step, so as to further improve the quality of bonding. For example, the first and second substrates with the bond enhancing layer may be bombarded with an inert gas ion beam or plasma. For example, according to some specific examples of the present invention, the aforementioned single crystal or polycrystalline substrate with a bonding enhancement layer (i.e., the second substrate) and the n/p type single crystal SiC base (i.e., the first substrate) subjected to the H-containing ion implantation may be simultaneously fed into the high vacuum bonding apparatus cavity at this step, with the implantation surface of the first substrate as the bonding surface; the vacuum degree of the bonding cavity can be controlled to be less than 5 x 10 -8 mbar, turning on Ar ion beams to activate the bonding surface so as to remove particle pollutants and oxides on the surface and keep the strict cleanness of the surface; then, after the surface activation, the bonding treatment can be performed. S400: performing a first anneal on the first bonded structure
According to an embodiment of the present invention, a first annealing treatment is performed in this step, which causes the first bonded structure to be peeled off from the inside of the first substrate to obtain the bonding material with the second substrate. As shown in fig. 3 and 4, the peeled first bonded structure may be divided into a portion of the remaining first substrate 100 'B and a bonding material 400 containing a high-quality single crystal thin film 100' a (derived from the first substrate). Thus, the method can easily obtain a bonding material without a long-time and high-temperature treatment, and is particularly suitable for forming a bonding material of SiC-SiC or the like.
According to some embodiments of the present invention, the temperature of the first annealing treatment is above 600 degrees celsius, and the temperature of the first annealing treatment can be adjusted according to the implantation energy of the H-containing ions in the previous step, so that the portion of the first substrate that has been previously formed and that has been subjected to the H-containing ion implantation can be stripped. And the damaged layer in the substrate can be repaired at the first annealing temperature at which the stripping can occur, finally, the bonding of the monocrystal n/p type SiC thin film (from the first substrate) with the thickness of tens of nanometers to tens of micrometers and the polycrystal or monocrystal SiC substrate (namely, the second substrate) can be realized, and the stripped part of the monocrystal n/p type SiC which is not subjected to the H-containing ion implantation can be reused so as to reduce the cost.
According to some embodiments of the invention, the first bonding structure is subjected to a third annealing treatment prior to the first annealing treatment, the third annealing treatment being at a lower temperature than the first annealing treatment. For example, room temperature bonding is adopted during bonding, the bonding strength needs to be further enhanced, and after bonding, a third annealing treatment is performed, wherein the third annealing treatment temperature is 600 ℃ and the treatment time is 2 hours. By adopting the temperature lower than the first annealing, the first bonding structure is not peeled off in the third annealing treatment process, the bonding strength can be further enhanced, the interface quality is improved, and the bonding interface is prevented from being split due to insufficient bonding strength in the first annealing treatment process.
Generally speaking, the bonding of materials such as SiC-SiC and the like can be realized by utilizing the process flow of the invention, and the interface layer generated by the bonding is a high-temperature resistant conducting layer, a metal layer and a conducting amorphous SiC layer (namely the bonding enhancement layer), so that the process flow can be suitable for the subsequent application of SiC power devices. The bonding of the method is carried out under a higher vacuum degree, the high vacuum degree can prevent the formation of oxidation in the surface activation and bonding processes, in addition, the surface activation cleaning technology can not only realize extremely low surface roughness, but also can almost completely and uniformly remove surface particle pollutants and surface oxides, for example, the SiC surface roughness after Ar ion treatment is less than 0.13nm (root-mean-square), so that the bonding material obtained by the method has better performance and is suitable for preparing a semiconductor device with high performance requirements. According to some embodiments of the invention, the method can obtain the amorphous SiC bonding enhancement layer with the thickness of only 2nm, so that a smaller bonding interface layer can be realized, which is beneficial to subsequent application and can be compatible with the application of low-cost vertical power devices such as IGBT and the like. And it was also confirmed from the TEM test that the presence of oxygen atoms was not introduced at the interface in the final bonding process due to the high degree of bonding vacuum according to the method of the embodiment of the present invention.
In another aspect of the invention, a bonding material is provided. The bonding material is obtained by the method described above. The bonding material thus has all the features and advantages of the bonding material obtained by the method described above, which are not described in detail herein. For example, the bonding material has at least one of the advantages of low production cost, short production period, good interface performance, suitability for preparing high-performance semiconductor devices and the like.
In another aspect of the invention, a semiconductor device is provided. The semiconductor device includes the aforementioned bonding material. Thus, the semiconductor has all the features and advantages of the bonding material described above, and thus, the description thereof is omitted.
According to an embodiment of the present invention, the semiconductor device is an IGBT, a MOSFET, or an SBD having a vertical structure.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, in the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (21)
1. A method of preparing a bonding material, comprising:
implanting H-containing ions at one side of a first substrate, wherein the first substrate is formed by non-silicon crystal materials;
forming a bonding enhancement layer at least one of the first substrate and the second substrate surface;
bonding the first substrate and the second substrate, and enabling the bonding enhancement layer to be located at a bonding interface to form a first bonding structure;
and carrying out first annealing treatment on the first bonding structure to enable the first bonding structure to be stripped from the inside of the first substrate so as to obtain the bonding material with the second substrate.
2. The method of claim 1, wherein the bonding enhancement layer is formed at least on the first substrate,
forming the bonding enhancement layer on the surface of the side of the first substrate implanted with the H ions,
or, after the bonding enhancement layer is formed on the surface of one side of the first substrate, the H-containing ion implantation is carried out on the surface.
3. The method according to claim 1 or 2, wherein the first substrate is a SiC single crystal material that satisfies a basal plane dislocation density of not higher than 1500/cm 2 。
4. The method of claim 3, wherein the second substrate is a SiC material and the crystal quality of the SiC material of the first substrate is better than the crystal quality of the SiC material of the second substrate.
5. The method of claim 1 or 2, wherein the bond enhancing layer is an amorphous layer.
6. The method of claim 5, wherein the amorphous layer is obtained by one or both of magnetron sputtering and ion implantation.
7. The method of claim 6, wherein the magnetron sputtered material is silicon carbide.
8. The method of claim 6, wherein the ion implantation comprises at least one of plasma source ion implantation and plasma immersion ion implantation.
9. The method of claim 6, wherein the ion implanted elements comprise one or more of Si, C, Al, B, Ga, N, P, As, Sb.
10. The method of claim 1 or 2, wherein the bonding enhancing layer is electrically conductive.
11. The method of claim 10, wherein the bonding enhancement layer comprises a metal silicide.
12. The method of claim 11, wherein the metal silicide comprises one or more of nickel silicide, tungsten silicide, molybdenum silicide, titanium silicide, tantalum silicide.
13. The method of claim 11, wherein forming the bonding enhancement layer is followed by performing the H-containing ion implantation on the first substrate having the side of the bonding enhancement layer, the forming the bonding enhancement layer comprising:
forming a metal layer on one side surface of the first substrate and one side surface of the second substrate,
and carrying out second annealing treatment on the first substrate and the second substrate with the metal layer on the surfaces to form the metal silicide.
14. The method of claim 11, wherein the metal silicide is deposited on a side surface of the first substrate and a side surface of a second substrate;
optionally, the metal silicide is formed by magnetron sputtering, ion beam assisted deposition, or pulsed laser deposition.
15. The method of claim 11, wherein forming the bonding enhancement layer further comprises further forming a metallic conductive sub-layer on the metal silicide surface.
16. The method of claim 10, wherein the bonding enhancement layer is an n-type conductive layer.
17. The method of claim 1 or 2 wherein said H-containing ion implant is performed at a dose of not less than 5 x 10 15 cm -2 。
18. The method according to claim 1 or 2, characterized in that the first bonding structure is subjected to a third annealing treatment prior to the first annealing treatment, the third annealing treatment being at a lower temperature than the first annealing treatment.
19. A bonding material, characterized in that it is obtained by means of a method according to any one of claims 1-18.
20. A semiconductor device comprising the bonding material of claim 19.
21. The semiconductor device according to claim 20, wherein the semiconductor device is an IGBT, a MOSFET, or an SBD having a vertical structure.
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