TW201742126A - Gate-all-around complementary nanowire device with III-V quantum well transistor, germanium junctionless transistor and method for making the same - Google Patents

Abstract

Techniques are disclosed for a gate-all-around complementary nanowire device with III-V quantum well transistor, a germanium junctionless transistor and method for making the same. The gate-all-around complementary nanowire device with III-V quantum well transistor comprises a first Ge nanowire, a N<SP>-</SP>-InGaAs and a N<SP>+</SP>-InGaAs, in which a first trench, a semiconductor barrier layer, a first high-K dielectric layer and a first metal gate electrode are formed in the N<SP>+</SP>-InGaAs. The germanium junctionless transistor comprises a second Ge nanowire and a P<SP>+</SP>-Ge layer, in which a second trench, a second high-K dielectric layer and a second metal gate electrode are formed in the P<SP>+</SP>-Ge layer.

Description

Ring gate III-V family quantum well transistor and tantalum junctionless crystal and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a ring gate III-V quantum well transistor and a germanium junctionless transistor and a method of fabricating the same.

Nowadays, most integrated circuits are based on 矽. However, as the feature size of integrated circuits is gradually reduced, existing Bulk silicon materials and processes are close to their physical limits, and severe challenges are encountered. . Below 32 nanometer technology nodes, especially below 22 nm, the structure and materials of the transistor will face more challenges. New technologies must be adopted to improve performance (new materials, new structures, and new processes). Among them, the introduction of new channel materials is the main innovative approach. Studies have shown that Ge has a high hole mobility, and III-V semiconductor materials (such as GaAs, InP, InGaAs, InAs, and GaSb) have high electron mobility, so after a 15 nm node, a new type of The bismuth-based high mobility materials will gradually transition from strained bismuth materials to new semiconductor materials such as high mobility Ge/III-V/graphene.

Paper (M.Radosavljevic et al., Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Ultra-Scaled Gate-to-Drain/Gate-to-Source Separation for Low Power Logic Applications, IEDM 2010, pp. 126-129) discloses a non-planar multi-gate structure InGaAs quantum well field transistor, the main disclosure of which is to fabricate an InGaAs fin structure on a germanium substrate, and then use high-k (dielectric) Constant) Gate dielectric to achieve low-power logic for gate-drain separation/gate-source separation. This InGaAs quantum well field effect transistor has a high electron transfer rate and can increase the speed of the logic circuit. How to further strengthen the component gate control capability, enhance the drive current and increase the component integration density are technical problems that need to be further solved in the industry.

Patent No. US8884363B2 discloses a nanowire transistor with a ring gate structure, which is mainly formed by patterning a top layer of a SOI substrate and a buried oxide layer to form a nanowire, and then removing the support. The partial buried oxygen layer of the nanowire line makes the position of the gate to form a suspended structure, and finally the ring gate structure is formed based on the suspended structure. However, the nanowire based on the tantalum material is still affected by the physical limit of the tantalum itself. It is difficult to further improve the performance of components at lower technology nodes. In addition, the source germanium doping of the transistor fabricated in this patent is opposite to the channel doping, and the element channel is formed in the surface region of the gate oxide layer, and the carrier is scattered due to the incompleteness of the interface between the gate oxide layer and the semiconductor channel. Impact, resulting in reduced mobility and reduced reliability.

In the publication of the patent publication No. US20100164102A1, a method for fabricating a Ge nanobelt on a skeletal structure is disclosed, which mainly forms a Ge nanobelt by an oxidative concentration process after growing GeSi on top of the skeg structure. This process is coated with GeSi material on the outside of the Si material, the concentration of Ge is relatively low, the oxidation concentration process is long, and the quality of the formed Ge nanobelt is difficult to guarantee.

In view of the above, the present invention provides a III-V quantum well transistor and a device capable of effectively improving the control range of the gate region, reducing parasitic resistance, and having high electron mobility. A method for efficient integration of tantalum-free transistors with high hole mobility.

In view of the above disadvantages of the prior art, an object of the present invention is to provide a ring-gate III-V quantum well transistor and a 锗-free junction transistor and a method of fabricating the same, and to provide an improved control region of a gate region, A method of reducing parasitic resistance and efficiently integrating a III-V quantum well transistor having high electron mobility and a tantalum junctionless transistor having high hole mobility.

To achieve the above and other related objects, the present invention provides a method for fabricating a ring-gate III-V quantum well transistor and a tantalum-free transistor, comprising the steps of: step 1), providing a substrate, Forming a SiGe layer on the surface of the germanium substrate; step 2), forming a shallow trench isolation structure in the SiGe layer and the germanium substrate, removing the shallow trench isolation structure on the surface of the germanium substrate, and obtaining a SiGe bump structure on the surface of the germanium substrate Step 3), epitaxial SiGe is formed on the surface of the SiGe bump structure to form a SiGe strip structure; and step 4), an oxidative concentration process is performed on each SiGe strip structure to form a Ge strip structure surrounded by an oxide layer, and the oxide layer is removed. And oxidizing the surface of the germanium substrate to form a surface oxide layer; step 5) sequentially forming a surrounding N ⁻ -type InGaAs layer and an N ⁺ -type InGaAs layer on the surface of the first Ge strip structure to form a surface on the second Ge strip structure a surrounding P ⁺ -type Ge layer; step 6), removing an N ⁺ -type InGaAs layer corresponding to the first gate region, exposing the N ⁻ -type InGaAs layer, forming a first annular trench, and removing the second gate region corresponding to the P ⁺ type Ge layer, exposing the second belt structure Ge Forming a second annular trench; step 7) sequentially forming a semiconductor barrier layer, a first high K (dielectric constant) dielectric layer, and a first metal gate on the first annular trench surface, and the second annular trench The surface sequentially forms a second high-k dielectric layer and a second metal gate.

A preferred embodiment of the method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor of the present invention further includes the steps of: step 8): fabricating sidewall structures on both sides of the gate region structure; Step 9) fabricating source metal and drain metal of the III-V quantum well transistor on the N ⁺ -type InGaAs source region and the N ⁺ -type InGaAs drain region on both sides of the first gate region, respectively The P ⁺ -type Ge source region and the P ⁺ -type Ge drain region on both sides of the second gate region respectively form a source metal and a drain metal of the junctionless transistor.

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, in step 4), after removing the oxide layer, it is also included in the H ₂ environment. The step of annealing the Ge band structure, the Ge band structure having a diameter ranging from 10 to 100 nm.

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, in step 5), molecular beam epitaxy, atomic layer deposition, and metal organic One of the chemical vapor deposition methods of the compound sequentially forms an N ⁻ -type InGaAs layer and an N ⁺ -type InGaAs layer surrounding the first Ge band structure on the surface of the first Ge band structure.

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, the concentration of the N ^- type InGaAs layer ranges from 10 to 100 nm, and the doping concentration is 10 ¹⁷ /cm ³ order of magnitude.

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, the concentration of the N ⁺ -type InGaAs layer ranges from 10 to 200 nm, and the doping concentration is 10 ¹⁹ /cm ³ order of magnitude.

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, in step 5), molecular beam epitaxy, atomic layer deposition, and metal organic One of the chemical vapor deposition methods of the compound forms a P ⁺ -type Ge layer surrounding the second Ge band structure on the surface of the second Ge band structure.

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, the concentration of the P ⁺ -type Ge layer ranges from 10 to 200 nm, and the doping concentration is 10 ¹⁹ /cm ³ order of magnitude.

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, in the step 7), the semiconductor barrier layer is selected as an N ^- type InP layer. The preparation method includes one of molecular beam epitaxy, atomic layer deposition, and metal organic compound chemical vapor deposition, and the concentration thereof ranges from 50 to 100 nm, and the concentration of doped Si is on the order of 10 ¹⁸ /cm ³ .

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, in step 7), atomic layer deposition, metal organic compound chemical vapor deposition And preparing the first high-k dielectric layer and the second high-k dielectric layer in a low-pressure chemical vapor deposition method, wherein the first high-k dielectric layer and the second high-k dielectric layer have a concentration range of 1 to 5 nm, the material includes one of Al ₂ O ₃ and TiSiO _x .

As a preferred embodiment of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, in step 7), physical vapor deposition, atomic layer deposition, and metal organic The first metal gate and the second metal gate are prepared by a compound chemical vapor deposition method, and the material of the first metal gate and the second metal gate includes one of TiN, NiAu and CrAu.

The invention also provides a ring gate III-V quantum well transistor and a tantalum junctionless crystal, comprising a III-V quantum well transistor and a tantalum junctionless crystal; the III-V quantum well electric The crystal includes: a first Ge band structure; an N ⁻ -type InGaAs layer surrounding the first Ge band structure surface; and an N ⁺ -type InGaAs layer surrounding the surface of the N ⁻ -type InGaAs layer and the first gate region Corresponding N ⁺ -type InGaAs layer is removed to expose the N ⁻ -type InGaAs layer to form a first annular trench; the first gate region includes a semiconductor barrier layer sequentially formed on the surface of the first annular trench, a high K dielectric layer and a first metal gate; the germanium junctionless transistor comprising: a second Ge band structure; a P ⁺ type Ge layer surrounding the second Ge band structure surface, and the second a P ⁺ -type Ge layer corresponding to the gate region is removed to expose the second Ge band structure to form a second annular trench; and a second gate region includes a second high-k layer sequentially formed on the surface of the second annular trench The electrical layer and the second metal gate.

A preferred embodiment of the ring-gate III-V quantum well transistor and the 锗-free junction transistor of the present invention further includes: a sidewall structure formed on both sides of the gate region structure; III-V quantum well The source metal and the drain metal of the transistor are respectively formed on the N ⁺ -type InGaAs source region and the N ⁺ -type InGaAs drain region on both sides of the first gate region; and the source metal of the germanium-free junction transistor And the drain metal are respectively formed on the P ⁺ -type Ge source region and the P ⁺ -type Ge drain region on both sides of the second gate region.

As a preferred embodiment of the ring gate III-V quantum well transistor and the tantalum junction transistor of the present invention, the first Ge band structure and the second Ge band structure have a diameter ranging from 10 to 100 nm.

As a preferred embodiment of the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, the concentration of the N ^- type InGaAs layer ranges from 10 to 100 nm, and the doping concentration is 10 ¹⁷ / Cm ³ orders of magnitude.

As a preferred embodiment of the ring gate III-V quantum well transistor and the tantalum junction transistor of the present invention, the concentration of the N ⁺ -type InGaAs layer ranges from 10 to 200 nm, and the doping concentration is 10 ¹⁹ / Cm ³ orders of magnitude.

As a preferred embodiment of the ring gate III-V quantum well transistor and the tantalum junction transistor of the present invention, the P ⁺ -type Ge layer has a concentration ranging from 10 to 200 nm and a doping concentration of 10 ¹⁹ / Cm ³ orders of magnitude.

As a preferred embodiment of the ring gate III-V quantum well transistor and the tantalum junction transistor of the present invention, the semiconductor barrier layer is selected as an N ⁻ -type InP layer, and its concentration ranges from 50 to 100 nm. The concentration of doped Si is on the order of 10 ¹⁸ /cm ³ .

As a preferred embodiment of the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention, the first high-k dielectric layer and the second high-k dielectric layer have a concentration range of 1 ~5nm, the material includes one of Al ₂ O ₃ and TiSiO _x .

As a preferred embodiment of the ring gate III-V quantum well transistor and the tantalum junction transistor of the present invention, the materials of the first metal gate and the second metal gate include TiN, NiAu and CrAu. One kind.

As described above, the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention and the method for fabricating the same have the following beneficial effects:

First, the present invention produces a suspended and high-quality Ge nanobelt by an oxidation and concentration process, and provides a good base material for the subsequent III-V quantum well transistor and the tantalum-free transistor;

Secondly, the present invention provides a method for effectively integrating a ring-gate III-V quantum well transistor and a tantalum-free transistor, and the ring-gate III-V quantum well of the present invention is compared to a planar structure. The transistor and the 锗-free transistor can greatly improve the control ability of the gate and improve the driving capability of the component;

Third, the present invention uses a junctionless type of transistor to reduce the parasitic current of the component. Because the channel avoids the interface between the incomplete gate oxide layer and the semiconductor channel, the carrier is limited by the interface scattering, which greatly improves the carrier mobility.

Fourth, the structure and the process of the invention are simple, and have wide application prospects in the field of integrated circuit manufacturing.

101‧‧‧矽Base

102‧‧‧SiGe layer

103‧‧‧Shallow trench isolation structure

104‧‧‧SiGe raised structure

105‧‧‧SiGe belt structure

106‧‧‧Ge belt structure

106'‧‧‧First Ge band structure

106"‧‧‧Second Ge band structure

106a‧‧‧Oxide layer

107‧‧‧Surface oxide layer

108‧‧‧N ^- type InGaAs layer

109‧‧‧N ⁺ type InGaAs layer

110‧‧‧P ⁺ type Ge layer

111‧‧‧Semiconductor barrier

112‧‧‧First high-k dielectric layer

113‧‧‧First metal gate

114‧‧‧Second high K dielectric layer

115‧‧‧Second metal gate

116‧‧‧ sidewall structure

109a‧‧‧N ⁺ type InGaAs source region

109b‧‧‧N ⁺ type InGaAs bungee region

Source metal of 117‧‧‧III-V quantum well transistor

118‧‧‧III-V family of quantum well dielectrics

110a‧‧‧P ⁺ type Ge bungee

110b‧‧‧P ⁺ type Ge source region

119‧‧‧锗 Bungee metal without junction transistor

120‧‧‧锗 source metal without junction transistor

109c‧‧‧ first annular groove

110c‧‧‧second annular groove

G1‧‧‧First Gate Area

G2‧‧‧second gate area

1 to 16c are schematic views showing the structures of the steps of the method for fabricating the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention.

Figure 8b is a schematic view of the longitudinal section along the first Ge strip structure 106 in Figure 8a.

Figure 9b is a schematic view of the longitudinal section along the second Ge strip structure 106 in Figure 9a.

Figure 10b is a schematic view of the longitudinal section along the first Ge strip structure 106 in Figure 10a.

Figure 11b is a schematic view of the longitudinal section along the second Ge strip structure 106 in Figure 11a.

Figure 12b is a schematic view of the longitudinal section along the first Ge strip structure 106 in Figure 12a.

Figure 13b is a schematic view of the longitudinal section along the first Ge strip structure 106 in Figure 13a.

Figure 14b is a schematic view of the longitudinal section along the first Ge strip structure 106 in Figure 14a.

Figure 15b is a schematic view of the longitudinal section along the second Ge strip structure 106 in Figure 15a.

16a to 16c are schematic views showing the structure of the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention.

Figure 17a shows the energy band diagram of a FinFET quantum well transistor (QW-FinFET) with a multilayer structure on a germanium substrate with a flat voltage.

Figure 17b shows the energy band diagram of a FinFET quantum well transistor (QW-FinFET) of a multi-layered n-channel on a germanium substrate with a positive bias applied to the gate.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Please refer to Figures 1 to 16c. It should be noted that the illustrations provided in the embodiments merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, rather than the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

As shown in FIG. 1 to FIG. 16c, the present embodiment provides a method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor, including the steps: as shown in FIG. In step 1), a substrate 101 is provided, and a SiGe layer 102 is formed on the surface of the germanium substrate 101.

As an example, the SiGe layer 102 may be formed by a plasma enhanced chemical vapor deposition method equal to the surface of the tantalum substrate 101, and the concentration of the SiGe layer 102 ranges from 10 to 100 nm.

As shown in FIG. 2 to FIG. 3, then step 2) is performed to form a shallow trench isolation structure 103 in the SiGe layer 102 and the germanium substrate 101, and the shallow trench isolation structure 103 on the surface of the germanium substrate 101 is removed. A SiGe bump structure 104 on the surface of the germanium substrate 101.

Specifically, the method includes the following steps: Step 2-1), using a photolithography-etching process on the SiGe layer 102 and the germanium substrate In the 101, a plurality of spaced-apart trenches are formed, the cross-sectional shape of the trenches is an inverted trapezoid, and a SiGe bump structure 104 remains between the trenches; and step 2-2) is filled with an insulating dielectric in each trench. a thin trench isolation structure 103, such as cerium oxide, etc.; step 2-3), removing the shallow trench isolation structure 103 on the surface of the ruthenium substrate 101 by a dry etching process or a wet etching process to obtain the ruthenium substrate In the present embodiment, the SiGe bump structure 104 has a cross-sectional shape of a positive trapezoid.

As shown in FIG. 4, step 3) is followed by epitaxial SiGe on the surface of the SiGe bump structure 104 to form a SiGe strip structure 105.

Specifically, the SiGe ribbon structure 105 is formed by, for example, plasma enhanced chemical vapor deposition equal to the surface epitaxial SiGe of the SiGe bump structure 104.

As shown in FIG. 5 to FIG. 7, step 4) is followed by performing an oxidative concentration process on each SiGe strip structure 105 to form a Ge strip structure 106 surrounded by the oxide layer 106a, removing the oxide layer 106a, and The surface of the crucible substrate 101 is oxidized to form a surface oxide layer 107.

Specifically, the SiGe ribbon structure 105 is oxidized such that the Si element therein is oxidized to cerium oxide, and the Ge element is gradually concentrated to the central region of the SiGe ribbon structure 105 until the Ge ribbon structure 106 surrounded by the oxide layer 106a is formed. Then, the surface oxide layer 106a is removed by a process such as wet etching to obtain a bare Ge band structure 106 having a circular cross section. Finally, an oxidation process is used to expose the surface oxide layer 107 of the tantalum oxide layer 106a exposed to the tantalum substrate 101, thereby improving the insulating properties of the device. In this embodiment, the overall SiGe is oxidatively concentrated, so that the time required for the oxidation process can be shortened, and a higher quality Ge nanobelt can be obtained. In addition, the circular Ge nanobelt can effectively improve the gate of the subsequent component. Extreme control capability and reduced gate dielectric and Ge nanobelt surface The unevenness reduces the scattering effect of surface carriers.

As an example, in step 4), after removing the oxide layer 106a, the step of annealing the Ge band structure 106 in the H ₂ environment is further included to further eliminate the internal stress and defects of the Ge band structure 106. For example, the Ge band structure 106 has a diameter ranging from 10 to 100 nm. As shown in FIG. 7, the Ge strip structure 106 includes a first Ge strip structure 106' and a second Ge strip structure 106".

As shown in FIG. 8a to FIG. 9b, wherein FIG. 8b is a schematic diagram of a longitudinal section along the first Ge strip structure 106' in FIG. 8a, and FIG. 9b is a second Ge strip structure 106 in FIG. 9a. "The schematic diagram of the longitudinal section structure, followed by step 5), sequentially forming a surrounding N ^- -type InGaAs layer 108 and an N ⁺ -type InGaAs layer 109 on the surface of the first Ge strip structure 106' to form a surface on the second Ge strip structure 106" A surrounding P ⁺ -type Ge layer 110.

As shown in FIGS. 8a to 9b, as an example, in step 5), one of molecular beam epitaxy, atomic layer deposition, and metal organic compound chemical vapor deposition is used for the first Ge band structure 106'. The surface sequentially forms an N ⁻ -type InGaAs layer 108 and an N ⁺ -type InGaAs layer 109 surrounding the first Ge strip structure 106 ′.

As an example, the N ^- type InGaAs layer 108 has a concentration ranging from 10 to 100 nm and a doping concentration of the order of 10 ¹⁷ /cm ³ .

As an example, the N ⁺ -type InGaAs layer 109 has a concentration ranging from 10 to 200 nm and a doping concentration of the order of 10 ¹⁹ /cm ³ .

As shown in FIGS. 9a to 9b, as an example, in step 5), one of molecular beam epitaxy, atomic layer deposition, and metal organic compound chemical vapor deposition is used for the second Ge band structure. A 106" surface forms a P ⁺ type Ge layer 110 surrounding the second Ge strip structure 106".

As an example, the P ⁺ -type Ge layer 110 has a concentration ranging from 10 to 200 nm and a doping concentration of the order of 10 ¹⁹ /cm ³ .

10a to 11b, wherein FIG. 10b is a schematic diagram of a longitudinal section along the first Ge strip structure 106' in FIG. 10a, and FIG. 11b is a second Ge strip structure 106 in FIG. 11a. "The schematic diagram of the longitudinal section structure, a first gate region g1 is defined in the N ⁺ -type InGaAs layer 109, and a second gate region g2 is defined in the P ⁺ -type Ge layer 110. Then, step 6) is performed to remove the first gate region. The N ⁺ -type InGaAs layer 109 corresponding to the pole region g1 exposes the N ⁻ -type InGaAs layer 108, forms the first annular trench 109c, and removes the P ⁺ -type Ge layer 110 corresponding to the second gate region g2 to expose the second The Ge strip structure 106" forms a second annular trench 110c.

As an example, as shown in FIGS. 10a to 10b, the N ⁺ -type InGaAs layer 109 corresponding to the first gate region g1 is removed, and the N ^- -type InGaAs layer 108 is exposed to form the first annular trench 109c.

As an example, as shown in FIGS. 11a to 11b, the P ⁺ -type Ge layer 110 corresponding to the second gate region g2 is removed, and the second Ge strip structure 106" is exposed to form the second annular trench 110c.

As shown in Fig. 12a to Fig. 15b, wherein Fig. 12b is a schematic view of the longitudinal section along the first Ge strip structure 106' in Fig. 12a, and Fig. 13b is the first Ge strip structure 106 in Fig. 13a. Schematic diagram of longitudinal section structure, Fig. 14b is a schematic diagram of the longitudinal section along the first Ge strip structure 106' in Fig. 14a, and Fig. 15b is a schematic diagram of the longitudinal section along the second Ge strip structure 106" in Fig. 15a. Next, in step 7), a semiconductor barrier layer 111 (as shown in FIGS. 12a and 12b) and a first high-k dielectric layer 112 are sequentially formed on the surface of the first annular trench 109c (as shown in FIGS. 13a and 13b). And a first metal gate 113 (as shown in FIGS. 14a and 14b), a second high-k dielectric layer 114 and a second metal gate 115 are sequentially formed on the surface of the second annular trench 110c (eg, 15a, 15b) The first high-k dielectric layer 112 and the second high-k dielectric layer 114 can be simultaneously prepared, and the first metal gate 113 and the second metal gate 115 can be simultaneously prepared. Save process steps and system Cost of the process.

As shown in FIG. 12a to FIG. 12b, as an example, in step 7), the semiconductor barrier layer 111 is selected as an N ^- type InP layer, and the preparation method thereof includes molecular beam epitaxy, atomic layer deposition, and metal organic One of the chemical vapor deposition methods of the compound has a concentration ranging from 50 to 100 nm, and the concentration of doped Si is on the order of 10 ¹⁸ /cm ³ , and the preferred doping concentration is 1.2 × 10 ¹⁸ /cm ³ .

As shown in Fig. 13a to Fig. 13b and Fig. 15a to Fig. 15b, as an example, in step 7), atomic layer deposition, metal organic compound chemical vapor deposition and low pressure chemical vapor deposition are used. The first high-k dielectric layer 112 and the second high-k dielectric layer 114 are prepared, and the first high-k dielectric layer 112 and the second high-k dielectric layer 114 have a concentration ranging from 1 to 5 nm. One of Al ₂ O ₃ and TiSiO _{x is} included.

As shown in FIGS. 14a to 14b and 15a to 15b as an example, in the step 7), the physical vapor deposition method, the atomic layer deposition method, and the metal organic compound chemical vapor deposition method are used to prepare the The first metal gate 113 is electrically connected to the second metal gate 115, and the material of the first metal gate 113 and the second metal gate 115 includes one of TiN, NiAu and CrAu.

The ring gate III-V quantum well transistor and the 锗-free junction transistor of the invention can greatly improve the control ability of the gate and improve the driving capability of the component.

As shown in Fig. 16a, step 8) is followed to form sidewall structures 116 on both sides of the structures of the first and second gate regions g1, g2.

As an example, the material of the sidewall structure 116 may be ceria or tantalum nitride, or a two-layer material composed of ceria and tantalum nitride.

As shown in Figures 16a to 16c, wherein Figure 16b shows a side view of the III-V quantum well transistor in Figure 16a, and Figure 16c shows the connection in Figure 16a. A schematic view of the side view of the surface transistor, and finally step 9), respectively, a III-V quantum is fabricated on the N ⁺ -type InGaAs source region 109a and the N ⁺ -type InGaAs drain region 109b on both sides of the first gate region g1. The source metal 117 and the drain metal 118 of the well transistor are respectively fabricated on the P ⁺ -type Ge source region 110b and the P ⁺ -Ge germanium region 110a on both sides of the second gate region g2. The source metal 120 and the drain metal 119 of the crystal.

As shown in FIG. 16a to FIG. 16c, the present embodiment further provides a ring gate III-V family quantum well transistor and a germanium junctionless transistor, the ring gate III-V family quantum well transistor and The 锗-free junction transistor includes a III-V quantum well transistor and a 锗-free junction transistor, wherein FIG. 16b shows a side view structure of the III-V quantum well transistor in FIG. 16a, Figure 16c shows a schematic side view of the tantalum junctionless transistor in Figure 16a.

As shown in FIG. 16a, as an example, the ring gate III-V quantum well transistor and the tantalum junction transistor of the embodiment further include: a sidewall structure 116 formed on the first and second gate regions g1. The two sides of the structure of g2; the source metal 117 and the drain metal 118 of the III-V quantum well transistor are respectively formed in the N ⁺ -type InGaAs source region 109a and the N ⁺ -type InGaAs on both sides of the first gate region g1 The drain metal region 109b; and the source metal 120 and the drain metal 119 of the germanium-free transistor are respectively formed on the P ⁺ -type Ge source region 110b and the P ⁺ -type Ge on both sides of the second gate region g2 On the bungee region 110a.

As shown in FIGS. 16a and 16b, the III-V quantum well transistor includes: a first Ge strip structure 106'; and an N ^- type InGaAs layer 108 surrounding the surface of the first Ge strip structure 106'. An N ⁺ -type InGaAs layer 109 surrounds the surface of the N ⁻ -type InGaAs layer 108 , and the N ⁺ -type InGaAs layer 109 corresponding to the first gate region g1 is removed, exposing the N ⁻ -type InGaAs layer 108 to form a first The annular trench 109c; the first gate region g1 includes a semiconductor barrier layer 111, a first high-k dielectric layer 112, and a first metal gate 113 which are sequentially formed on the surface of the first annular trench 109c.

As shown in FIGS. 16a and 16c, the germanium junctionless transistor includes: a second Ge strip structure 106"; a P ⁺ -type Ge layer 110 surrounding the surface of the second Ge strip structure 106", and The P ⁺ -type Ge layer 110 corresponding to the second gate region g2 is removed to expose the second Ge strip structure 106" to form a second annular trench 110c; and the second gate region g2 includes sequentially formed in the second The annular trench 110c has a second high-k dielectric layer 114 and a second metal gate 115 on the surface.

As an example, the first Ge strip structure 106' and the second Ge strip structure 106" have a diameter ranging from 10 to 100 nm.

As an example, the N ^- type InGaAs layer 108 has a concentration ranging from 10 to 100 nm and a doping concentration of the order of 10 ¹⁷ /cm ³ .

As an example, the N ⁺ -type InGaAs layer 109 has a concentration ranging from 10 to 200 nm and a doping concentration of the order of 10 ¹⁹ /cm ³ .

As an example, the P ⁺ -type Ge layer 110 has a concentration ranging from 10 to 200 nm and a doping concentration of the order of 10 ¹⁹ /cm ³ .

As an example, the semiconductor barrier layer 111 is selected to be an N ^- type InP layer having a concentration ranging from 50 to 100 nm and a doped Si concentration of the order of 10 ¹⁸ /cm ³ .

As an example, the first high-k dielectric layer 112 and the second high-k dielectric layer 114 have a concentration ranging from 1 to 5 nm, and the material includes one of Al ₂ O ₃ and TiSiO _x .

As an example, the material of the first metal gate 113 and the second metal gate 115 includes one of TiN, NiAu, and CrAu.

Figure 17a shows the energy band diagram of a FinFET quantum well transistor (QW-FinFET) with a multilayer structure on a germanium substrate with a flat voltage. Figure 17b shows the gate on a germanium substrate with a positive bias applied to the gate. Multi-layered n-channel FinFET quantum well transistor (QW-FinFET) The energy band diagram shows that when the gate of the equivalent subwell is positively biased, the two-dimensional electron gas structure is formed in the InP and InGaAs interface regions due to the band bending, so that the components have a very high High electron mobility.

The present embodiment provides a ring-gate III-V quantum well transistor and a tantalum-free transistor. In fact, the III-V quantum well transistor and the tantalum-free transistor belong to the junctionless field effect transistor. In the category of crystals, the junction-free field effect transistor (JLT) consists of the source region, the channel, the drain region, the gate oxide layer and the gate, and the impurity doping type from the source region to the channel and the drain region. The same, no PN junction, belongs to the majority of the carrier conductive components. The insulator gate dielectric encapsulates the entire cylindrical channel and overlies the metal gate. The conductive channel and the metal gate are separated by an insulator dielectric, and most of the carriers (holes) in the channel reach the drain from the source of the cylinder channel rather than the surface. By accumulating or depleting the majority of the carriers in the component channel by the gate bias, the channel conduction can be modulated to control the channel current. When the gate bias is so large that the hole in the cylinder channel near a section of the drain is completely depleted, in this case, the component channel resistance becomes quasi-infinite and the component is turned off. Since the gate bias can deplete the cylindrical channel hole from the surface and the inside from the 360 degree direction, the gate can control the channel of the cylinder greatly, and the threshold voltage of the component is effectively reduced. Since the incomplete gate oxide layer and the semiconductor channel interface are avoided, the carrier is limited by the interface scattering, which improves the carrier mobility. In addition, the junctionless field effect transistor belongs to the majority carrier conductive element, and the electric field intensity near the drain in the channel direction is lower than that of the conventional inversion channel MOS transistor, so the performance and reliability of the component are greatly improved. .

As described above, the ring-gate III-V quantum well transistor and the tantalum-free transistor of the present invention and the method for fabricating the same have the following beneficial effects:

First, the present invention produces a suspended and high-quality Ge nanobelt by an oxidation and concentration process, and provides a good base material for the subsequent III-V quantum well transistor and the tantalum-free transistor;

Secondly, the present invention provides a method for effectively integrating a ring-gate III-V quantum well transistor and a tantalum-free transistor, and the ring-gate III-V quantum well of the present invention is compared to a planar structure. The transistor and the 锗-free transistor can greatly improve the control ability of the gate and improve the driving capability of the component;

Thirdly, the invention adopts a junctionless type of transistor, which reduces the parasitic capacitance of the component, and the channel avoids the interface of the incomplete gate oxide layer and the semiconductor channel, and the carrier is limited by the interface scattering, thereby greatly Improved carrier mobility.

Fourth, the structure and the process of the invention are simple, and have wide application prospects in the field of integrated circuit manufacturing.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

101‧‧‧矽Base

106‧‧‧Ge belt structure

106'‧‧‧First Ge band structure

106"‧‧‧Second Ge band structure

108‧‧‧N ^- type InGaAs layer

109‧‧‧N ⁺ type InGaAs layer

110‧‧‧P ⁺ type Ge layer

111‧‧‧Semiconductor barrier

112‧‧‧First high-k dielectric layer

113‧‧‧First metal gate

114‧‧‧Second high K dielectric layer

115‧‧‧Second metal gate

116‧‧‧ sidewall structure

109a‧‧‧N ⁺ type InGaAs source region

109b‧‧‧N ⁺ type InGaAs bungee region

Source metal of 117‧‧‧III-V quantum well transistor

118‧‧‧III-V family of quantum well dielectrics

110a‧‧‧P ⁺ type Ge bungee

110b‧‧‧P ⁺ type Ge source region

119‧‧‧锗 Bungee metal without junction transistor

120‧‧‧锗 source metal without junction transistor

109c‧‧‧ first annular groove

110c‧‧‧second annular groove

G1‧‧‧First Gate Area

G2‧‧‧second gate area

Claims (20)

A method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor, comprising the steps of: step 1), providing a germanium substrate, forming a SiGe layer on the surface of the germanium substrate; and step 2) Forming a shallow trench isolation structure in the SiGe layer and the germanium substrate, removing the shallow trench isolation structure on the surface of the germanium substrate to obtain a SiGe bump structure on the surface of the germanium substrate; and step 3) on the surface of the SiGe bump structure Epitaxial SiGe, forming a SiGe band structure; step 4), performing an oxidative concentration process on each SiGe band structure to form a Ge band structure surrounded by an oxide layer, removing the oxide layer, and oxidizing the surface of the germanium substrate to form a surface oxide layer, The Ge band structure includes a first Ge band structure and a second Ge band structure; and Step 5) sequentially forming a surrounding N ⁻ -type InGaAs layer and an N ⁺ -type InGaAs layer on the surface of the first Ge band structure, the N ⁺ -type InGaAs layer a first gate region is defined in the layer, and a surrounding P ⁺ -type Ge layer is formed on the surface of the second Ge strip structure, wherein the second gate region is defined in the P ⁺ -type Ge layer; and the step 6) is removed The N ⁺ -type InGaAs layer corresponding to a gate region exposes the N ^- -type InGaAs layer Forming a first annular trench, and removing the P ⁺ -type Ge layer corresponding to the second gate region, exposing the second Ge strip structure to form a second annular trench; and step 7), in the first ring The surface of the shaped trenches sequentially forms a semiconductor barrier layer, a first high-k dielectric layer and a first metal gate, and a second high-k dielectric layer and a second metal gate are sequentially formed on the surface of the second annular trench. The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to claim 1, wherein the method further comprises the step of: step 8), in the first gate region and A sidewall structure is respectively formed on both sides of the structure of the second gate region; Step 9), III-V is respectively formed on the N ⁺ -type InGaAs source region and the N ⁺ -type InGaAs drain region on both sides of the first gate region The source metal and the drain metal of the quantum well transistor, and the P ⁺ -Ge source region and the P ⁺ -Ge germanium region on both sides of the second gate region respectively form a germanium-free junction transistor Source metal and silicon metal. The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to claim 1, wherein in step 4), after removing the oxide layer, it is further included in H _{2 .} The step of annealing the Ge band structure in the environment, the Ge band structure having a diameter ranging from 10 to 100 nm. The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to the first aspect of the patent application, wherein: in step 5), molecular beam epitaxy and atomic layer deposition are used. And one of the metal organic compound chemical vapor deposition methods sequentially forming the N ⁻ -type InGaAs layer and the N ⁺ -type InGaAs layer surrounding the first Ge strip structure on the surface of the first Ge strip structure. The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to claim 1, wherein the concentration of the N ^- type InGaAs layer ranges from 10 to 100 nm, and is doped. The concentration is on the order of 10 ¹⁷ /cm ³ . The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to claim 1, wherein the concentration of the N ⁺ -type InGaAs layer ranges from 10 to 200 nm, and is doped. The concentration is on the order of 10 ¹⁹ /cm ³ . The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to the first aspect of the patent application, wherein: in step 5), molecular beam epitaxy and atomic layer deposition are used. And one of the metal organic compound chemical vapor deposition methods forms a P ⁺ -type Ge layer surrounding the second Ge band structure on the surface of the second Ge band structure. The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to claim 1, wherein the P ⁺ -type Ge layer has a concentration ranging from 10 to 200 nm, and is doped. The concentration is on the order of 10 ¹⁹ /cm ³ . The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to claim 1, wherein in the step 7), the semiconductor barrier layer is selected as an N ^- type InP layer. The preparation method includes one of molecular beam epitaxy, atomic layer deposition, and metal organic compound chemical vapor deposition, and the concentration thereof ranges from 50 to 100 nm, and the concentration of doped Si is on the order of 10 ¹⁸ /cm ³ . The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to the first aspect of the patent application, wherein: in step 7), an atomic layer deposition method, a metal organic compound chemical gas is used. The first high-k dielectric layer and the second high-k dielectric layer, the first high-k dielectric layer and the second high-k dielectric layer are prepared by one of a phase deposition method and a low-pressure chemical vapor deposition method The concentration ranges from 1 to 5 nm, and the material includes one of Al ₂ O ₃ and TiSiO _x . The method for manufacturing a ring-gate III-V quantum well transistor and a tantalum-free transistor according to the first aspect of the patent application, wherein: in step 7), physical vapor deposition and atomic layer deposition are used. And a metal organic compound chemical vapor deposition method for preparing the first metal gate and the second metal gate, the material of the first metal gate and the second metal gate comprises TiN, NiAu and CrAu One. A ring gate III-V quantum well transistor and a 锗-free junction transistor, comprising a III-V quantum well transistor and a 锗-free junction transistor; the III-V quantum well transistor comprises: a Ge-band structure; an N ^- type InGaAs layer surrounding the surface of the first Ge-band structure; an N ⁺ -type InGaAs layer surrounding the surface of the N ^- type InGaAs layer, the N ⁺ -type InGaAs layer defining a first gate region And the N ⁺ -type InGaAs layer corresponding to the first gate region is removed to expose the N ⁻ -type InGaAs layer to form a first annular trench; the first gate region includes sequentially formed on the first ring a semiconductor barrier layer on the surface of the trench, a first high-k dielectric layer, and a first metal gate; the germanium junctionless transistor includes: a second Ge band structure; a P ⁺ -type Ge layer surrounding the second Ge band a P ⁺ -type Ge layer defining a second gate region, and the P ⁺ -type Ge layer corresponding to the second gate region is removed to expose the second Ge band structure to form a second annular trench The second gate region includes a second high-k dielectric layer and a second metal gate sequentially formed on the surface of the second annular trench. The ring gate III-V quantum well transistor and the tantalum junctionless transistor according to claim 12, further comprising: a sidewall structure formed on the first gate region and the second gate Both sides of the structure of the polar region; the source metal and the drain metal of the III-V quantum well transistor are respectively formed in the N ⁺ -type InGaAs source region and the N ⁺ -type InGaAs drain region on both sides of the first gate region The source metal and the drain metal of the junctionless transistor are respectively formed on the P ⁺ -type Ge source region and the P ⁺ -type Ge drain region on both sides of the second gate region. The ring gate III-V quantum well transistor and the 锗 joint are as described in claim 12 The transistor, wherein: the first Ge strip structure and the second Ge strip structure have a diameter ranging from 10 to 100 nm. The ring gate III-V quantum well transistor and the tantalum junctionless transistor according to claim 12, wherein the N ^- type InGaAs layer has a concentration ranging from 10 to 100 nm and a doping concentration of 10 ¹⁷ / cm ³ orders of magnitude. The ring gate III-V quantum well transistor and the tantalum junctionless transistor according to claim 12, wherein the N ⁺ -type InGaAs layer has a concentration ranging from 10 to 200 nm and a doping concentration of 10 ¹⁹ / cm ³ orders of magnitude. The ring gate III-V quantum well transistor and the tantalum junctionless transistor according to claim 12, wherein the P ⁺ -type Ge layer has a concentration ranging from 10 to 200 nm and a doping concentration of 10 ¹⁹ / cm ³ orders of magnitude. The ring gate III-V quantum well transistor and the tantalum junctionless transistor according to claim 12, wherein the semiconductor barrier layer is selected as an N ^- type InP layer, and the concentration ranges from 50 to 100 nm. Its doped Si concentration is on the order of 10 ¹⁸ /cm ³ . The ring gate III-V quantum well transistor and the tantalum junctionless transistor according to claim 12, wherein: the concentration of the first high K dielectric layer and the second high K dielectric layer The range is 1 to 5 nm, and the material includes one of Al ₂ O ₃ and TiSiO _x . The ring gate III-V quantum well transistor and the tantalum junctionless transistor according to claim 12, wherein the material of the first metal gate and the second metal gate comprises TiN, NiAu And one of CrAu.