CN104701374A - Tunneling field effect transistor and forming method thereof - Google Patents
Tunneling field effect transistor and forming method thereof Download PDFInfo
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- CN104701374A CN104701374A CN201310669773.4A CN201310669773A CN104701374A CN 104701374 A CN104701374 A CN 104701374A CN 201310669773 A CN201310669773 A CN 201310669773A CN 104701374 A CN104701374 A CN 104701374A
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Abstract
Disclosed are a tunneling field effect transistor and a forming method thereof. The tunneling field effect transistor comprises a semiconductor substrate, a first semiconductor layer, an annular groove, a first doping region, a first channel region, a second doping region, second channel regions, a grid electrode and a grid dielectric layer, the first semiconductor layer is positioned on the semiconductor substrate and has a first doping type, the annular groove is positioned in the first semiconductor layer, the first doping region is positioned on the first semiconductor layer and surrounded by the annular groove and has a first doping type, the first channel region is positioned on the first doping region, the second doping region is positioned on the first channel region and has a second doping type, the second channel regions are positioned on the side faces of the second doping region, the first channel region and the first doping region and at the bottom of the annular groove, the grid electrode is positioned in the annular groove, and the grid dielectric layer is positioned between the second channel regions and the grid electrode. Tunneling path and tunneling area are increased, so that performance of the tunneling field effect transistor is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially relate to a kind of tunneling field-effect transistor and forming method thereof.
Background technology
In order to can by semiconductor device application in ultralow pressure low-power consumption field, adopt novel conduction mechanism and obtain the device architecture of super steep sub-threshold slope and its preparation process and become the focus that everybody pays close attention under small size device.Researchers proposed a kind of possible solution in the last few years, adopted tunneling field-effect transistor (Tunnel Field Effect transistor, TFET) exactly.Tunneling field-effect transistor is different from traditional metal-oxide layer-semiconductor field effect transistor (MOSFET), the source and drain doping type of tunneling field-effect transistor is contrary, the bandtoband utilizing grid to control back-biased P-I-N knot realizes conducting, can break through the restriction of conventional MOS FET sub-threshold slope 60mV/dec.
Existing a kind of tunneling field-effect transistor as shown in Figure 1, it comprises the insulating barrier 101 be positioned on Semiconductor substrate (not shown), be positioned at the semiconductor layer 103 on insulating barrier (insulator) 101, be positioned at source region 102 and the drain region 104 of semiconductor layer 103 both sides, wherein the doping type in source region 102 and drain region 104 is contrary, be positioned at the grid stacked structure on semiconductor layer 103, described grid stacked structure comprises and is positioned at gate dielectric layer 105 on semiconductor layer 103 and grid 106.
But existing tunneling field-effect transistor ties the restriction of tunnelling probability and tunnel area by source, it is faced with the little problem declined with subthreshold swing of ON state current.Although new tunneling field-effect transistor implementation is suggested, such as green FET, but, owing to suppressing the difficulty of edge tunnel assembly (lateraltunneling component) or reduction off-state current (off-state current), high drive current and the amplitude of oscillation lower than 60mV/dec are never implemented.In a word, although the simulation result of tunneling field-effect transistor is very attractive, but, due to low drive current (drive current) and degraded subthreshold swing (subthreshold swing), the experimental result of tunneling field-effect transistor can not be competed with traditional mos field effect transistor (MOSFET).
For this reason, need a kind of new tunneling field-effect transistor and preparation method thereof, to solve the little problem do not satisfied the demands with subthreshold swing of tunneling field-effect transistor ON state current.
Summary of the invention
The problem that the present invention solves is to provide a kind of tunneling field-effect transistor and forming method thereof, to improve the ON state current of tunneling field-effect transistor, and makes subthreshold swing reach corresponding demand, improves the performance of tunneling field-effect transistor.
For solving the problem, the invention provides a kind of tunneling field-effect transistor, comprising:
Semiconductor substrate is provided;
Form the first semiconductor layer of the first doping type on the semiconductor substrate;
Described first semiconductor layer forms the second semiconductor layer;
Described second semiconductor layer is formed the 3rd semiconductor layer of the second doping type;
Etch described 3rd semiconductor layer until form the second doped region;
Etch described second semiconductor layer until form the first channel region;
First semiconductor layer described in etching part until form the first doped region, and forms the ring-shaped groove around described first doped region simultaneously;
In the bottom of described ring-shaped groove and described first doped region, the side of the first channel region and the second doped region forms the second channel region;
Gate dielectric layer is formed on the surface of described second channel region;
Fill described ring-shaped groove and form grid.
Optionally, the thickness range of described first channel region is
the thickness range of described second channel region is
Optionally, the doping content scope of described first semiconductor layer is 1E19atom/cm
3~ 1E21atom/cm
3, the doping content scope of described 3rd semiconductor layer is 1E19atom/cm
3~ 1E21atom/cm
3.
Optionally, the thickness range of described first semiconductor layer is
the thickness range of described 3rd semiconductor layer is
Optionally, the material of described first channel region comprises silicon, germanium, SiGe or indium arsenide, and the material of described second channel region comprises silicon, germanium, SiGe or indium arsenide.
Optionally, the thickness range of described grid is
Optionally, described 3rd semiconductor layer is etched until the process forming described second doped region comprises:
Described 3rd semiconductor layer forms pad oxide;
Described pad oxide forms cap layer;
Described cap layer forms mask layer;
With described mask layer for mask, described cap layer, pad oxide and the 3rd semiconductor layer are etched.
Optionally, fill the process that described ring-shaped groove forms described grid to comprise:
Gate material layer is adopted to fill described ring-shaped groove and cover described cap layer;
Planarization is carried out to described gate material layer until expose described cap layer surface;
Etch-back is carried out to the gate material layer after planarization and forms described grid.
Optionally, the thickness range of described pad oxide is
the thickness range of described cap layer is
For solving the problem, present invention also offers a kind of tunneling field-effect transistor, comprising:
Semiconductor substrate;
Be positioned at the first semiconductor layer in described Semiconductor substrate, described first semiconductor layer has the first doping type;
Be arranged in the ring-shaped groove of described first semiconductor layer;
To be positioned on described first semiconductor layer and by described ring-shaped groove around the first doped region, described first doped region has the first doping type;
Be positioned at the first channel region on described first doped region;
Be positioned at the second doped region on described first channel region, described second doped region has the second doping type;
Be positioned at the second channel region bottom described second doped region, the first channel region and the first side, doped region and described ring-shaped groove;
Be arranged in the grid of described ring-shaped groove;
Gate dielectric layer between described second channel region and described grid.
Optionally, the thickness range of described first channel region is
the thickness range of described second channel region is
Optionally, the doping content scope of described first doped region is 1E19atom/cm
3~ 1E21atom/cm
3, the doping content scope of described second doped region is 1E19atom/cm
3~ 1E21atom/cm
3.
Optionally, the thickness range of described first doped region is
the thickness range of described second doped region is
Optionally, the material of described first channel region comprises silicon, germanium, SiGe or indium arsenide, and the material of described second channel region comprises silicon, germanium, SiGe or indium arsenide.
Optionally, the thickness range of described grid is
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, form the first doped region, the stacked structure of the first channel region and the second doped region, described first doped region and the second doped region are respectively one of them of source area and drain region, and the second channel region formed around described stacked structure, then continue to form gate dielectric layer on the second surface, channel region, the grid around gate dielectric layer is formed on gate dielectric layer surface, because the second channel region length is around the first doped region, first channel region and the second doped region, its length significantly increases, because this increasing the tunneling path of transistor, and because the second channel region covers the side of the first doped region and the first channel region completely, and at least cover the surface of the second doped region, therefore, the area of the second channel region is larger, add tunnelling area, when tunneling path and tunnelling area all increase, the performance of tunneling field-effect transistor is improved.
Further, the thickness range of the second semiconductor layer is
if the second semiconductor layer is too thick, then the first doped region of follow-up formation and the second doped region are at a distance of too far away, and namely channel length is too large, affects the performance of transistor.Same, if the second semiconductor layer is too thin, the first doped region and the second doped region are at a distance of too near, and the transistor performance of follow-up formation declines, and therefore, by the control of the thickness range of the second semiconductor layer are
Further, the doping content scope of the first semiconductor layer is 1E19atom/cm
3~ 1E21atom/cm
3if doping content is too low, then the first semiconductor layer resistance is too large, and the transistor performance of formation declines, if doping content is too high, then the foreign atom in the first semiconductor layer can be diffused in other structure sheaf, causes adverse effect equally to the performance of transistor; The doping content scope of the 3rd semiconductor layer is 1E19atom/cm
3~ 1E21atom/cm
3if doping content is too low, then the 3rd semiconductor layer resistance is too large, and the transistor performance of formation declines, if doping content is too high, then the foreign atom in the 3rd semiconductor layer can be diffused in other structure sheaf, causes adverse effect equally to the performance of transistor.
Further, the thickness range of the 3rd semiconductor layer is
because the 3rd semiconductor layer is follow-up for the formation of the second doped region, and the second surface, doped region needs to be formed metal silicide usually, and to reduce contact resistance, form metal silicide and will consume certain silicon, therefore the thickness of the 3rd semiconductor layer needs usually
above, but, when the thickness of the 3rd semiconductor layer is greater than
time, the resistance of whole 3rd semiconductor layer can increase.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of existing tunneling field-effect transistor;
The structural representation that each step of formation method of the tunneling field-effect transistor that Fig. 2 to Figure 11 provides for the embodiment of the present invention is corresponding.
Embodiment
Existing tunneling field-effect transistor cannot reach high ON state current and low sub-threshold slope, and tunneling path (tunneling path) and tunnelling area (tunneling area) are the most important factor determining tunneling field-effect transistor performance, longer tunneling path and larger tunnelling area contribute to improving tunneling field-effect transistor performance.
For this reason, the invention provides a kind of new tunneling field-effect transistor, have in described tunneling field-effect transistor simultaneously around the first doped region, second channel region of the first channel region and the second doped region, because the second channel region length significantly increases, because this increasing the tunneling path of transistor, and because the second channel region covers the side of the first doped region and the first channel region completely, and at least cover the surface of the second doped region, therefore, the area of the second channel region is larger, add tunnelling area, when tunneling path and tunnelling area all increase, the performance of tunneling field-effect transistor is improved.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of formation method of tunneling field-effect transistor, incorporated by reference to referring to figs. 2 to Figure 11.
Please refer to Fig. 2, Semiconductor substrate 200 is provided.
In the present embodiment, Semiconductor substrate 200 can be any applicable semi-conducting material, be specifically as follows silicon, germanium, SiGe, carborundum, GaAs, indium arsenide or indium phosphide etc., Semiconductor substrate 200 can also comprise epitaxial loayer, such as, can be silicon-on-insulator (SOI), germanium on insulator (GeOI) etc.Semiconductor substrate 200 can also carry out light dope.If Semiconductor substrate 200 is light dope Semiconductor substrate 200, Semiconductor substrate 200 doping type is identical with drain region doping type.
Please continue to refer to Fig. 2, form the first semiconductor layer 210a of the first doping type on semiconductor substrate 200.
In the present embodiment, when the material of Semiconductor substrate 200 is silicon, the material of the first semiconductor layer 210a can be preferably silicon, now, epitaxial growth method can be selected equally to form the first semiconductor layer 210a on semiconductor substrate 200, thus make the interface between the first semiconductor layer 210a and Semiconductor substrate 200 smooth on the one hand, make the lattice of silicon in the first semiconductor layer 210a neatly intact on the other hand.
First doped region 210b both can be source area, also can be drain region, in order to ensure that follow-up first doped region 210b can realize corresponding effect, particularly ensure that follow-up first doped region 210b can be electrically connected with other structure by the first semiconductor layer 210a after etching residue, the thickness range that the present embodiment arranges the first semiconductor layer 210a is
In the present embodiment, first semiconductor layer 210a is adulterated, described first doping type can be P type or N-type, for convenience of description, the present embodiment follow-up in steps all will with the first doping type for N-type be described, the first doping type is the equivalent replacement that the embodiment of P type is considered as that the first doping type is the embodiment of N-type.
In the present embodiment, when carrying out N-type doping to the first semiconductor layer 210a, can be realized by the trap doping in traditional handicraft, what adopt can be phosphonium ion, arsenic ion or antimony ion, and, high annealing can be carried out after doping.
In the present embodiment, the doping content scope of the first semiconductor layer 210a is 1E19atom/cm
3~ 1E21atom/cm
3if doping content is too low, then the first semiconductor layer 210a resistance is too large, the transistor performance formed declines, if doping content is too high, then the foreign atom in the first semiconductor layer 210a can be diffused in other structure sheaf, causes adverse effect equally to the performance of transistor.
Please continue to refer to Fig. 2, the first semiconductor layer 210a forms the second semiconductor layer 220a.
In the present embodiment, the second semiconductor layer 220a is intrinsic semiconductor layer, therefore, does not adulterate to it.
In the present embodiment, the thickness range of the second semiconductor layer 220a is
if the second semiconductor layer 220a is too thick, then the first doped region 210b of follow-up formation and the second doped region 230b is at a distance of too far away, and namely channel length is too large, affects the performance of transistor.Same, if the second semiconductor layer 220a is too thin, the first doped region 210b and the second doped region 230b is at a distance of too near, and the transistor performance of follow-up formation declines, and therefore, the control of the thickness range of the second semiconductor layer 220a is by the present embodiment
In the present embodiment, the material of the second semiconductor layer 220a can be silicon, germanium, SiGe or indium arsenide, also can be their combination.When the material of the first semiconductor layer 210a is silicon, the material of the second semiconductor layer 220a can be preferably silicon, now, epitaxial growth method can be selected equally on the first semiconductor layer 210a to form the second semiconductor layer 220a, thus make the interface between the first semiconductor layer 210a and the second semiconductor layer 220a smooth on the one hand, make the lattice of silicon in the second semiconductor layer 220a neatly intact on the other hand.
Please continue to refer to Fig. 2, the second semiconductor layer 220a forms the 3rd semiconductor layer 230a of the second doping type.
In the present embodiment, the material of the 3rd semiconductor layer 230a can be silicon, germanium, SiGe or indium arsenide equally, also can be their combination.When the material of the second semiconductor layer 220a is silicon, the material of the 3rd semiconductor layer 230a can be preferably silicon, now, epitaxial growth method can be selected equally on the second semiconductor layer 220a to form the 3rd semiconductor layer 230a, thus make the interface between the 3rd semiconductor layer 230a and the second semiconductor layer 220a smooth on the one hand, make the lattice of silicon in the 3rd semiconductor layer 230a neatly intact on the other hand.
In the present embodiment, when carrying out the doping of P type to the 3rd semiconductor layer 230a, can be realized equally by the trap doping in traditional handicraft, what adopt can be boron ion, boron fluoride ion or indium ion, and, high annealing can be carried out after doping.
In the present embodiment, the doping content scope of the 3rd semiconductor layer 230a is 1E19atom/cm
3~ 1E21atom/cm
3if doping content is too low, then the 3rd semiconductor layer 230a resistance is too large, the transistor performance formed declines, if doping content is too high, then the foreign atom in the 3rd semiconductor layer 230a can be diffused in other structure sheaf, causes adverse effect equally to the performance of transistor.
In the present embodiment, because the 3rd semiconductor layer 230a is follow-up for the formation of the second doped region, and the second surface, doped region needs to be formed metal silicide usually, to reduce contact resistance, form metal silicide and will consume certain silicon, therefore the thickness of the 3rd semiconductor layer 230a needs usually
above, but, when the thickness of the 3rd semiconductor layer 230a is greater than
time, the resistance of whole 3rd semiconductor layer 230a can increase, and therefore the thickness range of the present embodiment control the 3rd semiconductor layer 230a is
Please continue to refer to Fig. 3, the 3rd semiconductor layer 230a shown in etch figures(s) 2 is until form the second doped region 230b.
In the present embodiment, the detailed process forming the second doped region 230b can comprise four steps.
First step, the 3rd semiconductor layer 230a forms pad oxide 240a.
In the present embodiment, pad oxide 240a can be used as the stress release layer between the cap layer 250a of follow-up formation and the 3rd semiconductor layer 230a, the material of pad oxide 240a can be silicon dioxide, and pad oxide 240a can use ald (ALD), chemical vapour deposition (CVD) (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering or other suitable methods to be formed.
In the present embodiment, the thickness range of pad oxide 240a is
if pad oxide 240a is too thin, then cannot reaches the effect of release stress, if pad oxide 240a is too thick, increase follow-up removal difficulty.
Second step, pad oxide 240a is formed cap layer 250a.
In the present embodiment, cap layer 250a can protect the 3rd semiconductor layer 230a, and in subsequent gate material layer 290a planarization process, can serve as stop-layer.The material of cap layer 250a can be nitride, such as SiN etc., and ald, chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition, sputtering or other suitable methods can be used equally to be formed.
In the present embodiment, the thickness range of cap layer 250a is
if cap layer 250a is too thick, cap layer 250a can be caused too large to the stress of the 3rd semiconductor layer 230a, and if cap layer 250a is too thin, just cannot serve as stop-layer in subsequent planarization process.
Third step, cap layer 250a is formed mask layer (not shown).
In the present embodiment, in order to make mask layer patterning, photoresist layer can be formed on mask layer, then utilizing the photoresist layer of patterning for mask, mask layer is etched.It should be noted that, also can directly with photoresist layer as mask layer.
4th step take mask layer as mask, etches cap layer 250a, pad oxide 240a and the 3rd semiconductor layer 230a.
In the present embodiment, after cap layer 250a and pad oxide 240a, form remaining cap layer 250b and pad oxide 240b.
In the present embodiment, dry etching or wet etching specifically can be used to etch the 3rd semiconductor layer 230a, until form the second doped region 230b, then, can mask layer be removed.
In the present embodiment, the description in the past in the face of the 3rd semiconductor layer 230a is known, and the thickness range of the second doped region 230b is
Please continue to refer to Fig. 3, etch the second semiconductor layer 220a until form the first channel region 220b.
In the present embodiment, the description in the past in the face of the second semiconductor layer 220a is known, and the thickness range of the first channel region 220b is
and the material of the first channel region 220b can comprise silicon, germanium, SiGe or indium arsenide.
Please continue to refer to Fig. 3, etching part first semiconductor layer 210a until form the first doped region 210b, and forms the ring-shaped groove 260 around the first doped region 210b simultaneously.
In the present embodiment, the thickness of the first doped region 210b be original first semiconductor layer 210a(as shown in Figure 2) part of thickness.Concrete, because the first semiconductor layer 210a thickness range is
therefore the thickness of the first doped region 210b may be selected to be in some cases
In the present embodiment, after formation first doped region 210b, also remain a part of first semiconductor layer 210c, this part first semiconductor layer 210c can be used as the tie point (separating to show differentiation with dotted line between the first semiconductor layer 210c and the first doped region 210b) of follow-up first doped region 210b and external circuit connection.
It should be noted that, the above etching to the first semiconductor layer 210a, the second semiconductor layer 220a and the 3rd semiconductor layer 230a can be carried out step by step, and also can carry out in same step, the present invention is not construed as limiting this.
Fig. 4 is the schematic top plan view of structure shown in Fig. 3, therefrom can see further, after above step, the present embodiment defines the stacked structure formed by the first doped region 210b, the first channel region 220b and the second doped region 230b, and this stacked structure by ring-shaped groove 260 around, the bottom of ring-shaped groove 260 is remaining first semiconductor layer 210c.In described stacked structure, one of them of first doped region 210b and the follow-up source area respectively as transistor of the second doped region 230b and drain region, namely when using the first doped region 210b as source area time, second doped region 230b is as drain region, when using the second doped region 230b as drain region time, the first doped region 210b is as source area.
Please refer to Fig. 5, form the second channel region 270 in the side of the bottom of ring-shaped groove 260 and the first doped region 210b, the first channel region 220b and the second doped region 230b.
In the present embodiment, second channel region 270 is simultaneously around the first doped region 210b, the first channel region 220b and the second doped region 230b, as can see from Figure 5, second channel region 270 covers the side of the first doped region 210b, the first channel region 220b and the second doped region 230b completely, but, in follow-up etch-back process, the side of the second doped region 230b may have part to come out.
In the present embodiment, the material of the second channel region 270 comprises silicon, germanium, SiGe or indium arsenide, when above-mentioned first semiconductor layer 210a, the second semiconductor layer 220a and the 3rd semiconductor layer 230a are silicon materials, the Material selec-tion of the second channel region 270 adopts silicon materials, and adopt epitaxial growth regime to form the second channel region 270, thus ensure that the second channel region 270 has good lattice structure.
In the present embodiment, the thickness range of the second channel region 270 is
in fact, the second channel region 270 is in the transistor that formed of the present embodiment, as the region of main channel region, therefore its thickness determines the size of channel region, therefore, the thickness of the second channel region 270 is too large or too littlely all will affect the performance of transistor, and the present embodiment is arranged on
Fig. 6 is the schematic top plan view of structure shown in Fig. 5, therefrom can see further, and the second channel region 270 around described stacked structure, and covers the bottom of ring-shaped groove 260.
Please refer to Fig. 7, form gate dielectric layer 280 on the surface of the second channel region 270.
In the present embodiment, gate dielectric layer 280 can comprise SiO2, high K medium material or other suitable materials, or the combination of these materials, gate electrode can be formed by one or more layers structure, when for high-k gate dielectric material, be specifically as follows any one or several in HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON and HfTiON.
Please refer to Fig. 8 to Figure 11, the follow-up continuation of the present embodiment forms filling ring-shaped groove 260 and forms grid 290b, concrete, forms grid 290b and can comprise three steps.
First step, please refer to Fig. 8, adopts gate material layer 290a to fill ring-shaped groove 260 and covering cap cap rock 250b.
In the present embodiment, the material of gate material layer 290a can be polysilicon, metal material, metal material compound or other suitable materials, or its their combination, can be such as any one or several in TaAlN, TiAlN, MoAlN, AlNx, TaN, TiN, MoN, Mo and W.
Second step, please refer to Fig. 9, carries out planarization until expose cap layer 250b surface to gate material layer 290a.
In the present embodiment, cmp (CMP) method can be adopted to carry out planarization, mentioning cap layer 250b above as stop-layer during planarization, therefore, can stop planarization when being planarized to and exposing cap layer 250b surface.
Third step, please continue to refer to Fig. 9, carries out etch-back to the gate material layer 290a after planarization and forms grid 290b.
In the present embodiment, grid 290b fills ring-shaped groove 260 thus around gate dielectric layer 280.The thickness range of grid 290b can be controlled in
thus ensure the switching effect of the raceway groove of grid 290b.
Please refer to Figure 10, after etch-back forms grid 290b, the present embodiment carries out the removal of cap layer 250b and pad oxide 240b, thus exposes the surface of the second doped region 230b.
Figure 11 is the schematic top plan view of structure shown in Figure 10, therefrom can see further, grid 290b is around gate dielectric layer 280, gate dielectric layer 280 is around the second channel region 270, second channel region 270 is around the second doped region 230b, known in conjunction with Figure 10, the second channel region 270 is simultaneously also around the first doped region 210b and the first channel region 220b.
Can also see from Figure 11, in the present embodiment, the figure of overlooking of the second doped region 230b is rectangle, but, in other embodiments of the invention, the figure of overlooking of the second doped region 230b can be other polygons such as square, five limits or hexagon, also can be circular or oval, can also be irregular figure, the present invention be not construed as limiting this.
It should be noted that, the present embodiment is follow-up can form ohmic contact regions on the second doped region 230b and grid 290b, and described ohmic contact regions can be made up of metal silicide layer.
It should be noted that, the present embodiment is follow-up can be passed through an etching technics, be etched to and expose remaining first semiconductor layer 210c, and fill corresponding electric conducting material and be connected to the first semiconductor layer 210c, thus make the first doped region 210b connect external circuit by the first semiconductor layer 210c.
In the tunneling field-effect transistor that the formation method provided by the present embodiment is formed, there is the second channel region 270, because the second channel region 270 is simultaneously around the first doped region 210b, first channel region 220b and the second doped region 230b, its length significantly increases, because this increasing the tunneling path of transistor, and the second channel region 270 covers the side of the first doped region 210b and the first channel region 220b completely, and at least cover the surface of the second doped region 230b, therefore, the area of the second channel region 270 is larger, add tunnelling area, when tunneling path and tunnelling area all increase, the performance of tunneling field-effect transistor is improved.
The embodiment of the present invention additionally provides a kind of tunneling field-effect transistor, incorporated by reference to reference Figure 10 and Figure 11.
Described tunneling field-effect transistor comprises Semiconductor substrate 200.Be positioned at the first semiconductor layer 210c in Semiconductor substrate 200, the first semiconductor layer 210c has the first doping type.Be arranged in the ring-shaped groove 260 of the first semiconductor layer 210c.To be positioned on the first semiconductor layer 210c and by ring-shaped groove 260 around the first doped region 210b, the first doped region 210b has the first doping type.Be positioned at the first channel region 220b on the first doped region 210b.
Be positioned at the second doped region 230b on the first channel region 220b, the second doped region 230b has the second doping type.Be positioned at the second channel region 270 bottom the second doped region 230b, the first channel region 220b and the first 210b side, doped region and ring-shaped groove 260.Be arranged in the grid 290b of ring-shaped groove 260.Gate dielectric layer 280 between the second channel region 270 and grid 290b.
In the present embodiment, the doping content scope of the first doped region 210b can be 1E19atom/cm
3~ 1E21atom/cm
3, the doping content scope of the second doped region 230b can be 1E19atom/cm
3~ 1E21atom/cm
3.
In the present embodiment, the thickness range of the first doped region 210b can be
the thickness range of the second doped region 230b is
in the present embodiment, the material of the first channel region 220b can comprise silicon, germanium, SiGe or indium arsenide, and the material of the second channel region 270 can comprise silicon, germanium, SiGe or indium arsenide.In the present embodiment, the thickness range of grid 290b can be
The tunneling field-effect transistor that the present embodiment provides can be formed by the method that formed of above-described embodiment, and therefore, the structures and characteristics of tunneling field-effect transistor each several part can with reference to above embodiment corresponding contents.
It should be noted that, in other embodiments of the invention, other method also can be adopted to form described tunneling field-effect transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. a formation method for tunneling field-effect transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
Form the first semiconductor layer of the first doping type on the semiconductor substrate;
Described first semiconductor layer forms the second semiconductor layer;
Described second semiconductor layer is formed the 3rd semiconductor layer of the second doping type;
Etch described 3rd semiconductor layer until form the second doped region;
Etch described second semiconductor layer until form the first channel region;
First semiconductor layer described in etching part until form the first doped region, and forms the ring-shaped groove around described first doped region simultaneously;
In the bottom of described ring-shaped groove and described first doped region, the side of the first channel region and the second doped region forms the second channel region;
Gate dielectric layer is formed on the surface of described second channel region;
Fill described ring-shaped groove and form grid.
2. the formation method of tunneling field-effect transistor as claimed in claim 1, it is characterized in that, the thickness range of described first channel region is
the thickness range of described second channel region is
3. the formation method of tunneling field-effect transistor as claimed in claim 1, it is characterized in that, the doping content scope of described first semiconductor layer is 1E19atom/cm
3~ 1E21atom/cm
3, the doping content scope of described 3rd semiconductor layer is 1E19atom/cm
3~ 1E21atom/cm
3.
4. the formation method of tunneling field-effect transistor as claimed in claim 1, it is characterized in that, the thickness range of described first semiconductor layer is
the thickness range of described 3rd semiconductor layer is
5. the formation method of tunneling field-effect transistor as claimed in claim 1, it is characterized in that, the material of described first channel region comprises silicon, germanium, SiGe or indium arsenide, and the material of described second channel region comprises silicon, germanium, SiGe or indium arsenide.
6. the formation method of tunneling field-effect transistor as claimed in claim 1, it is characterized in that, the thickness range of described grid is
7. the formation method of tunneling field-effect transistor as claimed in claim 1, is characterized in that, etch described 3rd semiconductor layer until the process forming described second doped region comprises:
Described 3rd semiconductor layer forms pad oxide;
Described pad oxide forms cap layer;
Described cap layer forms mask layer;
With described mask layer for mask, described cap layer, pad oxide and the 3rd semiconductor layer are etched.
8. the formation method of tunneling field-effect transistor as claimed in claim 7, is characterized in that, fills the process that described ring-shaped groove forms described grid and comprises:
Gate material layer is adopted to fill described ring-shaped groove and cover described cap layer;
Planarization is carried out to described gate material layer until expose described cap layer surface;
Etch-back is carried out to the gate material layer after planarization and forms described grid.
9. the formation method of tunneling field-effect transistor as claimed in claim 7, it is characterized in that, the thickness range of described pad oxide is
the thickness range of described cap layer is
10. a tunneling field-effect transistor, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the first semiconductor layer in described Semiconductor substrate, described first semiconductor layer has the first doping type;
Be arranged in the ring-shaped groove of described first semiconductor layer;
To be positioned on described first semiconductor layer and by described ring-shaped groove around the first doped region, described first doped region has the first doping type;
Be positioned at the first channel region on described first doped region;
Be positioned at the second doped region on described first channel region, described second doped region has the second doping type;
Be positioned at the second channel region bottom described second doped region, the first channel region and the first side, doped region and described ring-shaped groove;
Be arranged in the grid of described ring-shaped groove;
Gate dielectric layer between described second channel region and described grid.
11. tunneling field-effect transistors as claimed in claim 10, it is characterized in that, the thickness range of described first channel region is
the thickness range of described second channel region is
12. tunneling field-effect transistors as claimed in claim 10, is characterized in that, the doping content scope of described first doped region is 1E19atom/cm
3~ 1E21atom/cm
3, the doping content scope of described second doped region is 1E19atom/cm
3~ 1E21atom/cm
3.
13. tunneling field-effect transistors as claimed in claim 10, it is characterized in that, the thickness range of described first doped region is
the thickness range of described second doped region is
14. tunneling field-effect transistors as claimed in claim 10, it is characterized in that, the material of described first channel region comprises silicon, germanium, SiGe or indium arsenide, and the material of described second channel region comprises silicon, germanium, SiGe or indium arsenide.
15. tunneling field-effect transistors as claimed in claim 10, it is characterized in that, the thickness range of described grid is
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| CN108878277A (en) * | 2017-05-08 | 2018-11-23 | 三星电子株式会社 | Grid is around nanometer gate fin-fet and its manufacturing method |
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