CN104617138B - Tunneling field-effect transistor and preparation method thereof - Google Patents
Tunneling field-effect transistor and preparation method thereof Download PDFInfo
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- CN104617138B CN104617138B CN201510038922.6A CN201510038922A CN104617138B CN 104617138 B CN104617138 B CN 104617138B CN 201510038922 A CN201510038922 A CN 201510038922A CN 104617138 B CN104617138 B CN 104617138B
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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Abstract
A kind of tunneling field-effect transistor, source region, two drain regions and two grid regions；Two drain regions are respectively arranged at the relative both sides of source region in the first direction, and two grid regions are respectively arranged at the relative both sides of source region in a second direction, and the first epitaxial layer and gate dielectric layer are equipped between source region and two grid regions；First epitaxial layer is arranged between source region and gate dielectric layer, and the first epitaxial layer forms p n tunnel junctions with source region；Two drain regions and two grid regions are enclosed in around source region, may be such that source region is completely under the control in two grid regions, and all by grid region electric field tunnelling can be occurred for the current-carrying electrons that source region plays the role of with grid region in overlapping region；First epitaxial layer is arranged between source region and gate dielectric layer, and its tunnelling type is linear tunnelling, and tunnelling area is big, and the electron tunneling direction of grid region direction of an electric field and source region is on a line, and tunnelling probability is big, so as to effectively improve tunnelling current.In addition, present invention also offers the preparation method of above-mentioned tunneling field-effect transistor.
Description
Technical field
The present invention relates to a kind of tunneling field-effect transistor and preparation method thereof.
Background technology
Since first piece of integrated circuit is born, integrated circuit technique develops all along the track of " mole theorem ", mesh
The size of preceding semiconductor transistor has accomplished 28nm, 22nm, and transistor size can constantly reduce, the lower power supply of demand
Voltage and threshold voltage, but traditional MOS structure has reached the limit, and the generation of low threshold voltage is more and more difficult.This is
Because threshold voltage reduces, (Ion/Ioff, wherein Ion are ON state current to on-off ratio, and Ioff is off-state current, and grid voltage is big
Ion is obtained in threshold voltage, grid voltage obtains Ioff less than threshold voltage) also to reduce, longer switch time can be caused.
Simultaneously because conventional MOS FET subthreshold swing slope S S is limited by thermoelectrical potential kT/q and can not be with device
The diminution of part size and synchronously reduce so that device Leakage Current increases, and the energy consumption of whole chip constantly rises, and chip power-consumption is close
Degree increased dramatically, and seriously hinder application of the chip in the system integration.In order to adapt to the development trend of integrated circuit, tunnelling field
Effect transistor (TFET, tunneling field-effect transistor) is suggested.Tunneling field-effect transistor
(TFET) be essentially gate control p-i-n diode, the doping type in its source region and drain region is opposite.For N-type TFET,
Source region is p-type heavy doping, and drain region is N-type heavy doping；For p-type TFET, source region is N-type heavy doping, and drain region is that p-type is heavily doped
It is miscellaneous.Source region causes TFET to form the working mechanism different from MOSFET, i.e. carrier quantum tunnel with drain region doping type difference
Mechanism is worn, is referred to as band-to-band-tunneling.For N-type TFET, the electronics at the source region conduction band bottom tunnelling under grid electric field action
Into drain region valence band, tunnelling current is formed, tunelling electrons flow to drain region and form drain current in the presence of drain voltage.Due to
It is different from MOSFET working mechanisms, so TFET is not limited by kT/q, its subthreshold swing SS<60mV/dec, it can reduce
Device static leakage current.
The tunnelling direction of carrier during TFET work and grid electric field not in the same direction, that is, put tunnelling machine at present
System.Therefore, in the prior art, cause carrier tunnelling probability relatively low using a tunneling mechanism so that TFET has tunnelling current
The shortcomings that small.Meanwhile the overlapping region between source region and grid region is limited so that tunnelling area is smaller, and tunneling current density with
Tunnelling area and tunnelling probability are directly proportional, so, cause relatively low tunnelling current.
The content of the invention
The present invention provides a kind of tunneling field-effect transistor and preparation method thereof, by increasing capacitance it is possible to increase tunnelling area, effectively improves
Tunnelling current.
On the one hand, there is provided the tunneling field-effect transistor includes source region, two drain regions and two grid regions；
Two drain regions are respectively arranged at the relative both sides of the source region in the first direction, described in the source region and two
Channel layer, the raceway groove that the channel layer is formed between the source region and the drain region are equipped between drain region；
Two grid regions are respectively arranged at the relative both sides of the source region in a second direction, and the second direction is vertical
The first direction；The first epitaxial layer and gate dielectric layer are equipped between the source region and two grid regions；First extension
Layer is arranged between the source region and the gate dielectric layer, and first epitaxial layer forms p-n tunnel junctions with the source region；It is described
The one side away from first epitaxial layer is connected with the grid region on gate dielectric layer, and the gate dielectric layer is used for outside described first
Prolong layer with the grid region to isolate.
In the first possible implementation, the first direction is the above-below direction of relatively described source region, described the
Two directions are the left and right directions of relatively described source region；
Two drain regions include the first drain region and the second drain region；First drain region is located at the underface of the source region, institute
State the surface that the second drain region is located at the source region；
In this second direction, the overall dimension of two grid regions and the source region is equal to or less than first drain region
Size, the source region is located at the surface in first drain region centre position, and two grid regions are respectively arranged at described first
Surface at the both ends of drain region.
With reference to the first possible implementation, in second of possible implementation, the channel layer includes first
Channel layer and the second channel layer, first channel layer are arranged between the source region and the first drain region, second channel layer
It is arranged between the source region and second drain region；First channel layer, the source region, second channel layer and described
The size of second drain region in this second direction is identical, and alignment is set in said first direction.
With reference to the first possible implementation, in the third possible implementation, on first drain region with institute
The corresponding opening position of source region is stated to raise up to form boss.
With reference to the first possible implementation, in the 4th kind of possible implementation, the shape knot in two grid regions
Structure is identical, and relatively described source region is symmetrical arranged.
With reference to the 4th kind of possible implementation, in the 5th kind of possible implementation, the grid region is L-shaped, and it two
Support arm is respectively Part I and Part II, and the Part I is oppositely arranged with the source region, and the Part II is from institute
The bottom for stating Part I extends towards the direction away from the source region.
With reference to the 5th kind of possible implementation, in the 6th kind of possible implementation, two grid regions and described the
Separation layer is equipped between one drain region, the separation layer isolates in the grid region with first drain region.
In the 7th kind of possible implementation, the one end of the grid region on third direction extends to be formed towards another grid region
There is grid connecting portion, the connecting portion is located at the side of the source region on third direction, and the third direction is both perpendicular to institute
State first direction and second direction；Two grid regions are connected by the grid connecting portion and form one first groove；
The one end of the gate dielectric layer on third direction extends to form media connection towards another gate dielectric layer, described in two
Gate dielectric layer is connected by the media connection and forms one second groove；
The one end of first epitaxial layer on third direction extends to form extension connecting portion towards another first epitaxial layer, and two
First epitaxial layer is connected by the extension connecting portion and forms one the 3rd groove；
The media connection, the extension connecting portion and the grid connecting portion are located at the source region on third direction
The same side；The media connection is between the grid connecting portion and the extension connecting portion, and the media connection is by institute
Grid connecting portion is stated with the extension connecting portion to isolate；The extension connecting portion between the grid connecting portion and the source region,
P-n tunnel junctions are formed between the extension connecting portion and the source region；
Two gate dielectric layers are embedded in first groove, and two first epitaxial layers are embedded in second groove,
The source region is embedded in the 3rd groove.
With reference to the 7th kind of possible implementation, in the 8th kind of possible implementation, the shape in two drain regions
Structure is identical；The relatively described source region in two drain regions is symmetrical arranged.
With reference to the 7th kind of possible implementation, in the 9th kind of possible implementation, the tunneling field-effect crystal
Pipe also includes substrate, and to be respectively arranged at the source region on the third direction relative two for the substrate and the grid connecting portion
At side；
In a first direction, the overall dimension of two drain regions, the channel layer and the source region is equal to or less than described
The size of substrate；In a second direction, two grid regions, the gate dielectric layer, first epitaxial layer and the source region is total
Body size is equal to or less than the size of the substrate.
With reference to foregoing any implementation, in the tenth kind of possible implementation, first epitaxial layer with it is described
Formed with the second epitaxial layer between source region；The doping type of first epitaxial layer and second epitaxial layer is on the contrary, described the
The doping type of two epitaxial layers is identical with the doping type of the source region, and the doping concentration of second epitaxial layer is more than the source
The doping concentration in area, to form precipitous p-n tunnel junctions between first epitaxial layer and the source region.
In a kind of the tenth possible implementation, tunneling field-effect transistor also includes electrode contact structure, the grid
Respectively corresponded in area, drain region and source region and be connected with electrode contact structure, to form grid, drain electrode and source electrode respectively.
On the other hand, there is provided a kind of preparation method of tunneling field-effect transistor, comprise the following steps：
One substrate is provided；
Drain region and source region are formed over the substrate, and the drain region is two, and two drain regions are distinguished in a second direction
It is arranged at the relative both sides of the source region, channel layer, the channel layer shape is equipped between the source region and two drain regions
Raceway groove between the source region and the drain region；
Prepare the first epitaxial layer of formation, gate dielectric layer and grid region, two grid regions and be respectively arranged at institute in a second direction
State at the relative both sides of source region, the vertical first direction of the second direction；It is all provided between the source region and two grid regions
There are the first epitaxial layer and gate dielectric layer；First epitaxial layer is arranged between the source region and the gate dielectric layer, and described
One epitaxial layer forms p-n tunnel junctions with the source region；On the gate dielectric layer away from first epitaxial layer one side with it is described
Grid region connects, and the gate dielectric layer is used to isolate first epitaxial layer with the grid region.
In the first possible implementation, two drain regions include the first drain region and the second drain region；The channel layer
Including the first channel layer and the second channel layer, first channel layer is arranged between the source region and the first drain region, and described
Two channel layers are arranged between the source region and second drain region；
Comprise the following steps in step " forming drain region and source region over the substrate "：
The first semiconductor layer is formed on substrate, to prepare the first drain region；
The second semiconductor layer is formed on first semiconductor layer, to prepare first channel layer；
The 3rd semiconductor layer is formed on second semiconductor layer, to prepare the source region；
The 4th semiconductor layer is formed on the 3rd semiconductor layer, to prepare second channel layer；
The 5th semiconductor layer is formed on the 4th semiconductor layer, to prepare second drain region；
A hard mask layer is deposited on the 5th semiconductor layer, the upper area in the first drain region includes the firstth area and two
Secondth area, the firstth area between two the secondth areas are located in a second direction, the part of etching hard mask layer on the second region,
Only retain hard mask layer in the part in the firstth area；
Using the hard mask layer as mask, etch the 5th semiconductor layer, the 4th semiconductor layer, the 3rd semiconductor layer,
And second semiconductor layer, make this four layers part only retained immediately below the hard mask layer；
Remove the hard mask layer.
With reference to the first possible implementation, in second of possible implementation, in step " with the hard mask
Layer be mask, etching the 5th semiconductor layer, the 4th semiconductor layer, the 3rd semiconductor layer and second semiconductor layer, make this four
After layer only part of the reservation immediately below the hard mask layer ", before the step " removing the hard mask layer ", also wrap
Include step：Using hard mask layer as mask, first semiconductor layer is etched, to cause the first semiconductor layer in the second direction
On middle part formed a boss.
With reference to the first possible implementation, in the third possible implementation, " prepare and formed in the step
Comprise the following steps in first epitaxial layer, gate dielectric layer and grid region "：
Two separation layers are prepared on first drain region, two separation layers are separately positioned on the source region in a second direction
Both sides at；
The first epitaxial layer and gate dielectric layer, first epitaxial layer and the gate medium are respectively formed in the both sides of the source region
Layer is located at the top of the separation layer；
Grid region is formed in side of each gate dielectric layer away from the source region, the grid region is located on the separation layer
Side.
In the 4th kind of possible implementation, include in the step " forming drain region and source region over the substrate "
Following steps：
It is square into semiconductor bar over the substrate；
The middle part for being located at the first direction in the semiconductor bar forms source region；
It is located to be formed at both ends relative on the first direction in the semiconductor bar and forms a drain region respectively, described half
Part of the conductor bar between the drain region and the source region forms the channel layer.
With reference to the third possible implementation, in the 4th kind of possible implementation, the source region and the drain region
Formed by ion implantation technology.
With reference to the third possible implementation, in the 5th kind of possible implementation, the step " prepares and forms the
Comprise the following steps in one epitaxial layer, gate dielectric layer and grid region "：
Semiconductor layer is formed on semiconductor bar, the semiconductor bar, which is located at the both sides in second direction, is each formed with half
Conductor layer, to cause the semiconductor layer to have threeth groove of the opening towards the source region, the source region is located at the described 3rd
In groove；The both ends of the semiconductor layer in a first direction are etched, two first epitaxial layers and its extension connecting portion are formed to prepare；
In a first direction, spacing, and the chi of first epitaxial layer between the end of first epitaxial layer and the drain region be present
The very little size more than or equal to the source region；
Dielectric layer is formed on first epitaxial layer, first epitaxial layer is located at equal at the both sides in second direction
Formed with the dielectric layer, to cause the dielectric layer that there is second groove of the opening towards the source region, and described the
One epitaxial layer is located in second groove；The both ends of the dielectric layer in a first direction are etched, two grid Jie is formed to prepare
Matter layer and media connection；In said first direction, the gate dielectric layer is identical with the size of both first epitaxial layers；
Grid region material is covered on the gate dielectric layer so that the grid region material forms an opening towards the source region
First groove, and the gate dielectric layer is located in first groove；The both ends of the grid region material in a first direction are etched, with
Prepare and form two grid regions and its grid connecting portion；In a first direction, the grid region and gate dielectric layer, the chi of the first epitaxial layer three
It is very little identical.
In the 6th kind of possible implementation, the preparation method of the tunneling field-effect transistor also includes step：Shape
Into electrode contact structure, each drain region, source region and grid region are respectively connected with electrode contact structure, to be correspondingly formed drain electrode, source electrode and grid
Pole.
Tunneling field-effect transistor according to the present invention and preparation method thereof, two drain regions and two grid regions are enclosed in source region week
Enclose, may be such that source region is completely under the control in two grid regions, source region there are current-carrying electrons in overlapping region all can be by with grid region
Tunnelling occurs to the effect of grid region electric field；First epitaxial layer is arranged between source region and gate dielectric layer, and its tunnelling type is line
Property tunnelling, tunnelling area is big, and the electron tunneling direction of grid region direction of an electric field and source region is on a line, and tunnelling probability is big, from
And effectively improve tunnelling current.
Brief description of the drawings
In order to illustrate more clearly of technical scheme, the required accompanying drawing used in embodiment will be made below
Simply introduce, it should be apparent that, drawings in the following description are only some embodiments of the present invention, general for this area
For logical technical staff, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the diagrammatic cross-section for the tunneling field-effect transistor that first embodiment of the invention provides；
Fig. 2 is the flow chart of the preparation method of Fig. 1 tunneling field-effect transistor；
Fig. 3 is profile corresponding to the step S11 of the preparation method of Fig. 1 tunneling field-effect transistor；
Fig. 4 is profile corresponding to the step S12 of the preparation method of Fig. 1 tunneling field-effect transistor；
Fig. 5 is profile corresponding to the step S126 of the preparation method of Fig. 1 tunneling field-effect transistor；
Fig. 6 is the step S127 of the preparation method of Fig. 1 tunneling field-effect transistor flow chart；
Fig. 7 is profile corresponding to the step S129 of the preparation method of Fig. 1 tunneling field-effect transistor；
Fig. 8 is profile corresponding to the step S131 of the preparation method of Fig. 1 tunneling field-effect transistor；
Fig. 9 is profile corresponding to the step S1321 of the preparation method of Fig. 1 tunneling field-effect transistor；
Figure 10 is the step S1322 of the preparation method of tunneling field-effect transistor in Fig. 1 flow chart；
Figure 11 is profile corresponding to the step S1323 of the preparation method of tunneling field-effect transistor in Fig. 1；
Figure 12 is profile corresponding to the step S1331 of the preparation method of tunneling field-effect transistor in Fig. 1；
Figure 13 is profile corresponding to the step S1332 of the preparation method of tunneling field-effect transistor in Fig. 1；
Figure 14 is profile corresponding to the step S1333 of the preparation method of tunneling field-effect transistor in Fig. 1；
Figure 15 is profile corresponding to the step S14 of the preparation method of tunneling field-effect transistor in Fig. 1
Figure 16 is the perspective exploded view for the tunneling field-effect transistor that second embodiment of the invention provides；
Figure 17 is the flow chart of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 18 is profile corresponding to the step S21 of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 19 is profile corresponding to the step S2212 of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 20 is stereogram corresponding to the step S2213 of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 21 is profile corresponding to the step S2221 of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 22 is profile corresponding to the step S2222 of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 23 is profile corresponding to the step S2231 of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 24 is profile corresponding to the step S2232 of the preparation method of tunneling field-effect transistor in Figure 16；
Figure 25 is profile corresponding to the step S2233 of the preparation method of tunneling field-effect transistor in Figure 16
Figure 26, Figure 27 are two visual angles corresponding to the step S23 of the preparation method of tunneling field-effect transistor in Figure 16
Profile
Figure 28 is the profile for the tunneling field-effect transistor that third embodiment of the invention provides；
Figure 29 is the profile for the tunneling field-effect transistor that four embodiment of the invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
Fig. 1 and Fig. 2 is referred to, the section knot of the tunneling field-effect transistor provided for the first better embodiment of the invention
Structure schematic diagram.Tunneling field-effect transistor includes source region 11, two drain regions 12,13 and two grid regions 14,15.Present embodiment
In, first direction Y is the above-below direction of relative source region 11, and second direction X is the left and right directions of relative source region 11.Source region 11 is side
Body shape, to facilitate the preparation of source region 11.Two drain regions 12,13 include the first drain region 12 and the second drain region 13.First drain region is located at
The underface in the first drain region 12, the second drain region 13 are located at the surface of source region 11, to cause the first drain region 12 and the second drain region 13
Y is separately positioned at the relative both sides of source region 11 in the first direction.The shape and structure in two grid regions 14,15 is roughly the same, two
X is separately positioned at the relative both sides of source region 11 in a second direction in grid region 14,15.First drain region 12, the second drain region 13 and two
Grid region 14,15 is enclosed in around source region 11, may be such that source region 11 is completely under the control in grid region, source region 11 and grid region 14,15
All by grid region electric field tunnelling can be occurred for the current-carrying electrons for playing the role of in overlapping region (as shown in dotted line frame in Fig. 1),
So as to improve tunnelling current.
In present embodiment, on second direction X, the overall dimension of two grid regions 14,15 and source region 11 can be equal to or small
Size in the first drain region 12, source region 11 are located at the surface in the centre position of the first drain region 12, and two grid regions 14,15 are respectively arranged at
Surface at the both ends of first drain region 11, carrying and branch can be played to whole tunneling field-effect transistor using the first drain region 11
Support acts on.
Both first drain region 12 and the second drain region 13 are equipped with channel layer between source region 11, i.e., in the presence of two channel layers,
Respectively the first channel layer 102 and the second channel layer 103.First channel layer 102 is arranged between the drain region 12 of source region 11 and first,
To form the raceway groove between the drain region 12 of source region 11 and first.Second channel layer 103 is arranged between the drain region 13 of source region 11 and second,
To form the raceway groove between the drain region 13 of source region 11 and second.First channel layer 102, source region 11, the second channel layer 103 and the second leakage
Area 13 is sequentially overlapped above the first drain region.
The size phase of first channel layer 102, source region 11, the second channel layer 103 and the second drain region 13 on second direction X
Together, and align and set in a first direction, consequently facilitating by the etch-forming of this four part one time, prepared beneficial to processing.Further,
The opening position corresponding with source region 11 raises up to form boss 121 on first drain region 12, the first channel layer 102, source region 11,
Two channel layers 103 and the second drain region 13 are arranged on the boss 121, so as to be beneficial to be located at the second direction X upper two of source region 11
Prepared by the processing of each part of side, convenient to set separation layer 122 to isolate source region 11 with grid region 14,15.Preferably, boss
121 size with both the first channel layers 102 on second direction X is identical, in order to the both sides of source region 11 carry out the moment from
And machine-shaping boss 121.
The shape in two grid regions 14,15 is identical, and relative source region 11 is symmetrical arranged.It is with wherein grid region 14 in present embodiment
Example is specifically described.Grid region is L-shaped, and its two support arm is respectively Part I 141 and Part II 142, Part I 141 with
Source region is oppositely arranged, and grid region face is formed at Part I 141.Part II 142 is from the bottom of Part I 141 towards away from source
The direction extension in area 11, Part II 142 are connected with grid 140, can be easy to set grid 140 using Part II 142.
It is equipped with separation layer 122 between two grid regions 14,15 and the first drain region 12, separation layer 122 is by grid region 14,15 and first
Drain region 11 isolates, to avoid electrically connecting between grid region and the first drain region.
The side away from source region 11 is additionally provided with abutment wall 16 on grid region 14, and grid region 142 and grid 140 are embedded in abutment wall 16
In, grid region 14 can be isolated with the miscellaneous part outside tunneling field-effect transistor using abutment wall, one end of grid 140 is exposed at side
Outside wall 16, to realize the electrical connection with miscellaneous part, so as to apply voltage to grid region 14.Herein, in other embodiment
In, grid region 14 can also be the tabular parallel to the surface of source region 11, i.e. grid region 14 only includes foregoing Part I 141.
The first epitaxial layer 17 and gate dielectric layer 18 are equipped between source region 11 and each grid region 14,15.With source region 11 and grid region
Exemplified by structure between 14, the first epitaxial layer 17 is arranged between source region 11 and gate dielectric layer 18, and its tunnelling type is linear tunnel
Wear, the contact surface between the first epitaxial layer 17 and source region 11 forms the tunnelling face for producing electron tunneling, the tunnelling of corresponding point tunnelling
Area is big；First epitaxial layer 17 is set between source region 11 and grid region 14, in direction of an electric field and the electricity of the electric signal that grid region 14 loads
The tunnelling of son is in opposite direction, i.e. the direction of an electric field of the electric signal that grid region 14 loads is parallel with the tunnelling direction of electronics so that grid region
The electron tunneling direction of 14 directions of an electric field and source region 11 is on a line, and tunnelling probability is big, so as to effectively improve tunnelling current.
The one side away from the first epitaxial layer 17 is connected with grid region on gate dielectric layer 18, and gate dielectric layer 18 can be by the extension of grid region 14 and first
Layer 17 is isolated.
Source region 11 is connected with the first epitaxial layer 17 completely towards the surface of the first epitaxial layer 17, so that the first epitaxial layer 17 is complete
Complete block can make full use of the external surface area of source region 11 to form tunnelling face in the left and right sides of source region 11, so as to be beneficial to tunnelling.
In present embodiment, in a first direction on Y, the size of the first epitaxial layer 17 is equal to the first channel layer 102, source region 11
And the total height of the three of the second channel layer 103, prepared in order to process.
Further, tunneling field-effect transistor also includes substrate 19 and electrode contact structure, and substrate 19 is arranged on the first leakage
The bottom in area 12.Whole tunneling field-effect transistor can be played a supporting role by substrate 19, and facilitate source region 11, grid region
14th, prepared by 15 etc. processing.Each grid region, drain region, and source region, on respectively correspond to be connected with electrode contact structure, with respectively shape
Into grid, drain electrode and source electrode, so as to realize the electrical connection of tunneling field-effect transistor and other components.
In present embodiment, grid 140 corresponding to grid region 14 is only illustrated, grid 140 is arranged on abutment wall, and is connected to
The Part II 142 in grid region 14, certainly in other implementations, grid 140 also may be connected to the Part I 141 in grid region
On.
Source electrode 110 is arranged at the right side of source region 11, i.e., source electrode 110 is arranged on the side that source region is provided with grid region 15.For
Avoid source electrode 110 from touching grid region 15, grid region 15, gate dielectric layer 18, be equipped with corresponding emptiness avoiding hole (figure on the first epitaxial layer 17
In do not indicate), source electrode 110 is embedded in abutment wall, and wears emptiness avoiding hole, and one end of source electrode 110 is connected to source region 11, other end dew
Outside abutment wall.Source electrode 110, which is located between the part of emptiness avoiding hole and grid region 15, the epitaxial layer 17 of gate dielectric layer 18 and first, to be filled with
Abutment wall material, to avoid contact with.
Drain electrode includes the first drain electrode 120 and the second drain electrode 130, wherein first drains and 120 is connected to the first drain region 12, second
Drain electrode 130 is connected to the second drain region 13.First drain electrode 120 be column, and it is electrically connected to drain region 12, and is embedded in abutment wall 16 and exhausted
In edge layer 122, to realize isolating between the first drain electrode 120 and miscellaneous part, it is located at abutment wall 16 at the right side of the first drain electrode 120
Outside, electrically connected with facilitating the first drain electrode 120 to be realized with outside.The material of abutment wall 16 can be identical with the material of insulating barrier 122, can
Think silicon nitride etc..In present embodiment, the first drain electrode 120 is arranged on the same side of source region 11 with source electrode 110, to avoid first
Drained 120 contacts with the Part II in grid region 15, and corresponding empty avoiding can be formed by etching on the Part II in grid region 15
Structure, and the isolation materials such as abutment wall are filled between drain electrode 120 and grid region 15, so that the first drain electrode 120 is isolated with grid region 15.
The drain electrode for being connected to the second drain region 13 is the second drain electrode 130, and the second drain electrode 130 (is not marked provided with storage tank in figure
Show), the opening of storage tank is arranged in storage tank towards source region 11, the second drain region 13, so that drain region 12 is surrounded in drain electrode,
Realize being reliably connected for the two.
Referring to Fig. 2, the stream of the preparation method for the tunneling field-effect transistor of first embodiment provided by the invention
Cheng Tu.The preparation method of tunneling field-effect transistor includes but is not limited to following steps.
Step S11 a, there is provided substrate 19.In the present embodiment, the material of substrate is silicon.As shown in figure 3, substrate can be rectangle
Substrate.In other embodiments, substrate can also be germanium (Ge) or SiGe, Jia Shendeng II-IV races or iii-v or IV-
The binary or ternary semiconductor of IV races, the silicon (Silicon on Insulator, SOI) in dielectric substrate or absolutely
Any one in germanium (Germanium on Insulator, GeOI) on edge substrate.
Step S12, drain region and source region are formed on the substrate 19, the drain region is two, and two drain regions are along the
Two directions are respectively arranged at the relative both sides of the source region, are equipped with channel layer between the source region and two drain regions, institute
State the raceway groove that channel layer is formed between the source region and the drain region.In the present embodiment, the drain region includes the first drain region and the
Two drain regions, channel layer include the first channel layer and the second channel layer, and the first channel layer is arranged between source region and the first drain region, the
Two channel layers are arranged between source region and the second drain region.Step S12 can specifically include following sub-step.
Step S121, as shown in figure 4, formed on substrate 19 first semiconductor layer 12a, the first semiconductor layer 12a to
Prepare the first drain region 12.First semiconductor layer 12a can be the N-type heavily doped semiconductor layer for the doping in situ that deposition is formed, its
Material can be any in silicon materials or germanium, germanium silicon material, III-V material or iii-v combination materials etc.
It is a kind of.
Step S122, formed on the first semiconductor layer 12a the second semiconductor layer 102a, the second semiconductor layer 102a to
Prepare the first channel layer 102.Second semiconductor layer can be the semiconductor layer for the assertive evidence doping that deposition is formed, and its material can be
Any one in silicon materials or germanium, germanium silicon material, III-V material or iii-v combination materials etc..
Step S123, on the second semiconductor layer 102a formed the 3rd semiconductor layer 11a, the 3rd semiconductor layer 11a to
Prepare source region 11.3rd semiconductor layer can be the semiconductor layer for the p-type heavy doping that deposition is formed, and its material can be silicon material
Any one in material or germanium, germanium silicon material, III-V material or iii-v combination materials etc..
Step S124, on the 3rd semiconductor layer 11a formed the 4th semiconductor layer 103a, the 4th semiconductor layer 103a to
Prepare the second channel layer 103.3rd semiconductor layer can be the semiconductor layer for the assertive evidence doping that deposition is formed, and its material can be
It is any one in silicon materials or germanium, germanium silicon material, III-V material or iii-v combination materials etc..
Step S125, the 5th semiconductor layer 13a is formed on the 4th semiconductor layer 103a, to prepare the second drain region.The
Five semiconductor layers can be the semiconductor layer for the N-type heavy doping that deposition is formed, its material can be silicon materials or germanium,
Any one in germanium silicon material, III-V material or iii-v combination materials etc..The tunnelling field prepared by the step
The semi-finished product structure of effect transistor is as shown in Figure 4.
Above depositing operation can by low-pressure chemical vapor deposition (LPCVD) or physical vapour deposition (PVD) (PVD) or
Molecular beam epitaxy (MBE) homepitaxy technique is realized, or is realized by ion implantation technology.The N-type impurity of doping so as to including
Arsenic ion, phosphonium ion etc., p type impurity generally comprises：Boron ion, fluorination boron ion etc..
Step S126, a hard mask layer 100a is deposited on the 5th semiconductor layer, etching hard mask layer is in a second direction
The part at both ends, only retain hard mask layer in a second direction among part.As shown in Figure 5.The preparation of hard mask layer can be with
Realized by low-pressure chemical vapor deposition (LPCVD) or physical vapour deposition (PVD) (PVD).
Step S127, using hard mask layer as mask, the 5th semiconductor layer 13a of etching, the 4th semiconductor layer 103a, the 3rd half
Conductor layer 11a and the second semiconductor layer 102a, make this four layers part only retained immediately below hard mask layer, so as to be formed
Structure as shown in Figure 6.When the hard mask layer is to prevent etching, influence of the etch liquids to mask layer underlying materials.It is logical
The step is crossed, as shown in fig. 6, the 5th semiconductor layer prepares to form the second drain region 13, the 4th semiconductor layer prepares to form the second ditch
Channel layer 103, the 3rd semiconductor layer prepare to form source region 11, and the second semiconductor layer prepares to form the first channel layer 102.
Step S128, using hard mask layer as mask, the first semiconductor layer 12a is etched, to cause the first semiconductor layer the
Middle part on two direction X forms a boss 121.Herein, can not also be in the first semiconductor in other embodiment
Boss 121 is formed on first area A of floor, that is, the upper surface for causing the first drain region 12 is a plane.
Step S129, hard mask layer is removed, it is as shown in Figure 7 to remove the structure formed after hard mask layer.
Step S13, prepare and form the first epitaxial layer, gate dielectric layer and grid region, two grid regions 14,15 are in a second direction
It is respectively arranged at the relative both sides of the source region 11, the vertical first direction Y of second direction X；The grid region 14 of source region 11 and two,
The first epitaxial layer 17 and gate dielectric layer 18 are equipped between 15.First epitaxial layer 17 be arranged on source region 11 and gate dielectric layer 18 it
Between, the first epitaxial layer 17 forms p-n tunnel junctions with source region 11；One side away from the first epitaxial layer 17 and grid region on gate dielectric layer 18
14 connections, gate dielectric layer 18 are used to isolate the first epitaxial layer 17 with grid region 14.The step can specifically include following sub-step.
Step S131, as shown in figure 8, a separation layer 122 is prepared respectively at two the second area B on the first drain region 12,
Separation layer 122 is used for insulate drain region 12 and grid region 14,15.The separation layer 122 can be the hard mask layer of insulation.In this step
In, can then it be etched away positioned at the 5th half in the first drain region 12 and the overall disposed thereon hard mask layer of the 5th semiconductor layer
Hard mask layer in conductor layer, only retain the hard mask layer on the second area B, separation layer is formed so as to prepare.
The upper level of separation layer 122 is equal to or less than the upper level of the first raceway groove 102, to ensure grid region and source
Corresponding area between area 11.In present embodiment, the upper level of separation layer is less than the upper level of the first raceway groove, and
The upper surface of separation layer is concordant with the upper surface of boss 121.
Step S132, is respectively formed the first epitaxial layer 17 and gate dielectric layer 18 in the both sides of source region 11, the first epitaxial layer 17 and
Gate dielectric layer 18 is located at the top of separation layer 122.The step specifically includes following steps.
Step S1321, one the 6th semiconductor layer 17a is formed, for preparing the first epitaxial layer 17.As shown in figure 9, the 6th half
Conductor layer is covered in the overall left and right sides of the first raceway groove, source region 11, the second raceway groove and the second drain electrode and the second drain electrode
Upper surface.6th semiconductor layer can use any of silicon, germanium, germanium silicon and III-V material, its doping type n-type,
Doping concentration can be undoped with, be lightly doped or heavy doping.6th semiconductor layer can form a p-n tunnel with source region 11
Wear knot.6th semiconductor layer can be formed by epitaxy technique.
Step S1321, a dielectric layer 18a is formed, for preparing gate dielectric layer 18.As shown in Figure 10, dielectric layer covers
It is placed on the top of the 6th semiconductor layer and its in the left and right sides.Dielectric layer can use high-k dielectrics material, Si oxide,
HfSiON or other oxide materials etc..The dielectric layer can be formed by extension or depositing operation.
Step S1322, the 6th semiconductor layer 17a and dielectric layer 18a is etched, the first epitaxial layer 17 and grid are formed to prepare
Dielectric layer 18.Etch away the 6th semiconductor layer in this step and dielectric layer be located at the second drain region just on part, only retain two
Person is located at the part on directly over separation layer.As shown in figure 11, the upper surface for preparing the first epitaxial layer 17 of formation is highly higher than
The upper level of source region 11, the upper surface of gate dielectric layer 18 are highly equal to or higher than the upper level of source region 11, and first
The height of epitaxial layer 17 is higher than the upper surface height of gate dielectric layer 18, to ensure tunnelling probability.In present embodiment, prepare and formed
The first epitaxial layer 17 upper surface highly be equal to the second raceway groove upper level, i.e., the two concordantly；Gate dielectric layer 18 it is upper
Face height is equal to the upper level of source region 11.
Step S133, grid region is formed in side of each gate dielectric layer 18 away from source region 11, grid region is located on the separation layer
Side.Following steps are specifically included in this step.
Step S1331, the first abutment wall 161 is formed on separation layer, as shown in figure 12, the upper surface of the first abutment wall 161 is high
Upper level of the degree equal to or less than the first raceway groove 102.In present embodiment, the upper level of the first abutment wall 161 is equal to
The upper level of first raceway groove 102, i.e., the two is concordant.The purpose of the step is the lower surface height in order that grid region 14,15
Equal to or less than the lower surface height of source region 11.
Step S1332, a grid region is formed respectively on each first abutment wall 161.As shown in figure 13, two grid regions 14,15 are L
Shape, its two support arm are respectively Part I and Part II, and Part I is correspondingly arranged with source region 11, and grid region face is formed at
A part.Part II extends from Part I towards the direction away from source region.The Part I upper surface in grid region 14,15 and grid are situated between
The upper surface of matter layer 18 is concordant, to cause in the present embodiment, the grid region face in grid region 14,15 and both second surfaces of source region 11 face
Product is identical, to maximize tunnelling probability.
Step S1333, the second abutment wall 162 is formed respectively on each grid region 14,15, as shown in figure 14.In present embodiment
In, abutment wall includes the first abutment wall 161 and the second abutment wall 162, abutment wall are divided into two parts and formed, and grid region can be caused to be embedded in abutment wall
In.The material of first abutment wall and the second abutment wall can with identical, its material can be Si oxide, silicon nitride, high-k dielectrics or its
His insulating materials.Second abutment wall 162 is covered in grid region and the upper surface of gate dielectric layer, to avoid the two to the second follow-up drain electrode
It is in contact.
Step S14, electrode contact structure is formed, as shown in figure 15, each grid region 14,15, the first drain region 12, the second drain region
13, and source region 11 is respectively connected with electrode contact structure, to be correspondingly formed grid 140,150, first the 120, second drain electrode 130 of drain electrode
And source electrode 110.Grid 140,150, first the 120, second drain electrode 130 of drain electrode and source electrode 110 prepare formation order can be regardless of elder generation
Afterwards.
Ar Ion Beam Etching is carried out to the grid, cobalt and titanium nitride ion beam precipitation are carried out on the surface of the grid
Afterwards, short annealing is carried out, titanium nitride ion beam and cobalt ions beam is removed, then carries out deposit passivation layer.This step is follow-up
Metallization process, in order to form a complete vertical tunneling transistors structure.
Figure 16 is referred to, the exploded pictorial of the tunneling field-effect transistor provided for the second better embodiment of the invention
Figure.Tunneling field-effect transistor includes source region 21, two drain regions 22 and two grid regions 23.Y is set respectively in the first direction in two drain regions 22
It is placed at the relative both sides of source region 21, X is respectively arranged at the relative both sides of source region 21 in a second direction in two grid regions 23.
Specifically, in the present embodiment, the shape and structure in two drain regions 22 is identical.Two drain regions 22 are symmetrically set with respect to source region 21
Put, and channel layer 24 is all provided between each drain region 22 and source region 21, the raceway groove that channel layer 24 is formed between source region 21 and drain region 22.
The first epitaxial layer 25 and gate dielectric layer 26 are equipped between two grid regions 23 and source region 21, the first epitaxial layer 25 is arranged on
Between source region 21 and gate dielectric layer 26, its tunnelling type is linear tunnelling, the contact surface between the first epitaxial layer 25 and source region 21
The tunnelling face for producing electron tunneling is formed, the tunnelling area of corresponding point tunnelling is big；First epitaxial layer 25 sets source region 21 and grid region
It is in opposite direction in the direction of an electric field for the electric signal that grid region 23 loads and the tunnelling of electronics between 23, i.e., the telecommunications that grid region 23 loads
Number direction of an electric field it is parallel with the tunnelling direction of electronics so that the electron tunneling direction of the direction of an electric field of grid region 23 and source region 21 is in
On one line, tunnelling probability is big, so as to effectively improve tunnelling current.On gate dielectric layer 26 away from the first epitaxial layer 25 one side with
Grid region 23 connects, and gate dielectric layer 26 can isolate in grid region 23 with the first epitaxial layer 25.
In present embodiment, the one end of grid region 23 on third direction Z extends formed with grid connecting portion towards another grid region
232, connecting portion is located at the side of source region 21 on third direction, and third direction Z is both perpendicular to first direction Y and second direction
X；Two grid regions 23 are connected by grid connecting portion 232 and form one first groove 231, so that two grid regions 23 are integral type knot
Structure, two grid regions 23 can be integrally formed, and facilitate two grid regions 23 to be processed and formed at one time.
The one end of gate dielectric layer 26 on third direction Z extends towards another gate dielectric layer 26 and forms media connection 262, and two
Gate dielectric layer 26 is connected by media connection 262 and forms one second groove 261, make it that two gate dielectric layers 26 can also one
It is body formed.
The one end of first epitaxial layer 25 on third direction Z forms extension connecting portion towards the extension of another first epitaxial layer 25
252, two first epitaxial layers 25 are connected by extension connecting portion 252 and form one the 3rd groove 251；To cause two the first epitaxial layers
25 can also be integrally formed.
Media connection 262, extension connecting portion 252 and grid connecting portion 232 are located at the same of source region 21 on third direction Z
Side；Media connection 262 is between grid connecting portion 232 and extension connecting portion 252, and media connection 262 is by grid connecting portion 232
Isolate with extension connecting portion 252；Extension connecting portion 252 between grid connecting portion 232 and source region 21, extension connecting portion 252 with
P-n tunnel junctions are formed between source region 21.Two gate dielectric layers 26 are embedded in the first groove 231, and two first epitaxial layers 25 are embedded in
In two grooves 261, source region 21 is embedded in the 3rd groove 251.
It can further increase the overlapping region between grid region 23 and source region 21 using grid connecting portion 232, make full use of source
Area 21 also forms tunnelling face in the outer surface of third direction Z sides, so as to increase tunnelling area, improves tunnelling current.Simultaneously should
It is simple in construction, it is easy to the preparation in grid region 23, the first epitaxial layer 25 and gate dielectric layer 26 to be molded.
Source region 21 is cube shape, is prepared in order to the processing of source region 21.In a first direction on Y, the size in grid region 23 is more than
The size of source region 21, so that two grid regions 23 are completely covered by three outer surfaces of source region 21, to make full use of source region 21
Tunnelling occurs for outer surface.
Tunneling field-effect transistor also includes substrate 29, and substrate 29 is respectively arranged at grid connecting portion 232 in third direction Z
At the relative both sides of source region 21.In a first direction on Y, the overall dimension in two drain regions 22, channel layer 24 and source region 21 is equal to or small
In the size of substrate 29；On second direction X, two grid regions 23, gate dielectric layer 26, the overall chi of the first epitaxial layer 25 and source region 21
The very little size equal to or less than substrate 29.To cause substrate 29 to play a supporting role whole tunneling field-effect transistor, and just
In the preparation of source region 21, grid region 23 and drain region 22.
Further, tunneling field-effect transistor also includes electrode contact structure (not shown), each grid region, drain region, and
Source region, on respectively correspond to and be connected with electrode contact structure, to form grid respectively, drain electrode and source electrode, so as to realize tunnelling field
The electrical connection of effect transistor and other components.
Present invention also offers the preparation method of the tunneling field-effect transistor of the second better embodiment, as shown in figure 16
The flow chart of the preparation method.The preparation method of tunneling field-effect transistor comprises the following steps.
Step S21 a, there is provided substrate 29, in the present embodiment, the material of substrate is silicon.As shown in figure 18, substrate can be side
Body shape.In other embodiments, the material of substrate 29 can be silicon, germanium, SOI (Silicon-On-Insulator, insulation lining
Silicon on bottom 29) or GeOI (Silicon-On-Insulator, the germanium in dielectric substrate 29) etc..
Step S22, drain region and source region are formed over the substrate, drain region is two, and two drain regions are distinguished in a second direction
It is arranged at the relative both sides of source region, channel layer is equipped between source region and two drain regions, channel layer is formed between source region and drain region
Raceway groove.The step can specifically include following sub-step.
Step S221, semiconductor bar 291 is formed above the substrate 29, its length direction is first direction Y, is partly led
Body bar is located at middle part of the substrate on second direction X.This step further comprises the steps.
Step S2212, as shown in figure 19, the first hard mask layer 200a is formed on the substrate 29, and it is hard to etch first
Mask layer 200a, only retain its center section on second direction X, second direction is perpendicular to first direction.First hard mask
Layer can be formed by depositing operation.
Step S2213, as shown in figure 20, using the first hard mask layer as mask, etched substrate 29, one is formed on substrate 29
Semiconductor bar 291, semiconductor bar are located at the middle part on the second direction X of substrate 29.Due to semiconductor bar 291 formed substrate 29 it
On, therefore, in the present embodiment, third direction Z is as vertical.
Step S2214, remove remaining first hard mask layer.
It can prepare to form semiconductor bar 291 by above step, certainly, in other embodiments, can also pass through
Other modes form semiconductor bar, for example, passing through FinFET (Fin Field-Effect Transistor；Imitate crystal in fin field
Pipe) forming method of fin ray forms semiconductor bar in device.
Step S222, the middle part that first direction Y is located in the semiconductor bar form source region 21.This step further comprises
Following steps.
Step S2221, as shown in figure 21, the second hard mask layer 200b is formed on semiconductor bar 291, etching second is covered firmly
The film layer center section on Y, and expose the semiconductor bar at the position in a first direction.Second hard mask layer can be by deposition side
Formula is formed.
Step S2222, as shown in figure 22, using the second hard mask layer 200b as mask, in semiconductor bar 291 in a first direction
Y center section forms source region 21 by ion implanting mode.In the present embodiment, P++ ion implantings are carried out, to form p-type weight
The source region 21 of doping.
Step S2223, remove remaining second hard mask layer 200b.
By step S222, can prepare to form source region 21, certainly, in other implementations, the formation of source region 21
Mode can also be that groove is opened up in semiconductor bar first direction Y center section, then deposition forms source region 21 in a groove.
Step S223, formation at both ends relative on first direction Y is located in the semiconductor bar and forms a drain region respectively
22, and the semiconductor bar is formed in part with channel layer between drain region 22 and source region 21.This step further comprise with
Lower step.
Step S2231, as shown in figure 23, the 3rd hard mask layer is formed on semiconductor bar, and etch the 3rd hard mask layer
In a first direction on Y both ends part；And in a first direction on Y, the size of remaining 3rd hard mask layer is more than source region 21
Size.3rd hard mask layer can be formed by depositional mode.
Step S2232, as shown in figure 24, using the 3rd hard mask layer as mask, the both ends on semiconductor bar first direction Y
Place forms drain region 22 by ion implanting mode.In present embodiment, N++ ion implantings are carried out, form the drain region of N-type heavy doping
22。
Step S2233, as shown in figure 25, remove remaining 3rd hard mask layer.
By above step S223, two drain regions 22 can be formed, and cause source region 21 in a first direction at the both sides on Y
Drain region 22 is respectively provided with, the part for not carrying out ion implanting on semiconductor bar partly forms ditch between source region 21 and drain region 22
Channel layer.Certainly, in other implementations, the generation type in drain region 22 can also be, at semiconductor first direction Y both ends
Part opens up groove, then deposition forms drain region 22 in a groove.
In step 22, source region is initially formed to prepare to form drain region again, certainly in other embodiments or, first
Drain region is formed, then prepares and to form source region, be i.e. step S222 and step S223 order can exchange.
Step S23, as shown in Figure 26, Figure 27, prepare and form the first epitaxial layer 25, gate dielectric layer 26 and grid region 23, source region
21 both sides on second direction X are each formed with grid region 23, and the first epitaxial layer 25 and gate dielectric layer 26 are formed in grid region 23 and source
Between area 21, the one side away from the first epitaxial layer 25 is connected with grid region 23 on gate dielectric layer 26.In the step, the semiconductor bar
Source region on be sequentially overlapped to form the first epitaxial layer 25, gate dielectric layer 26 and grid region 23, and both sides on source region second direction X
It is each formed with the first epitaxial layer 25, gate dielectric layer 26 and grid region 23 so that equal at the both sides relative on second direction X of source region 21
Grid region 23 is provided with, second direction X is perpendicular to first direction Y.Further specifically, this step further comprises the steps.
Step S231, semiconductor layer is formed on the semiconductor bar, and cause semiconductor layer that there is an opening towards source
3rd groove 251 in area 21, source region are located in the 3rd groove 251.Semiconductor layer, which is used to prepare, forms the first epitaxial layer 25.Specifically
Ground, the etching semiconductor layer both ends on Y in a first direction, two first epitaxial layers 25 and its extension connecting portion 252 are formed to prepare.
In a first direction, spacing between the end of the first epitaxial layer and drain region 22 be present, and the size of the first epitaxial layer 25 be more than or
Equal to the size of source region 21.
The doping type of semiconductor layer is n-type, and it can be undoped with being lightly doped, or heavy doping.First semiconductor layer
Material can be any one in silicon, germanium, germanium silicon, III-V material or iii-v combination materials etc..Semiconductor layer can
To be formed by epitaxy technique.
Step S232, dielectric layer is formed on the first epitaxial layer 25, and cause dielectric layer that there is an opening towards source
Second groove 261 in area 21, and the first epitaxial layer 25 is located in second groove 261.The dielectric layer, which is used to prepare, forms two grid Jie
Matter layer 26 and its media connection 261.Dielectric layer can be formed by depositing operation.Dielectric layer can be high-k dielectrics
Material, Si oxide, HfSiON, or other oxide materials etc..Etching dielectric layer both ends on Y in a first direction, with
Preparation forms gate dielectric layer 26, and in a first direction on Y, gate dielectric layer 26 is identical with the size of both the first epitaxial layers 25.
Step S233, grid region material is covered on gate dielectric layer 26, and cause grid region material that there is an opening towards source region
21 the first groove 233, and gate dielectric layer 26 is located in first groove 233.The grid region material both ends on Y in a first direction are etched,
Two grid regions 23 and its grid connecting portion 231 are formed to prepare.In a first direction on Y, grid region 23 and gate dielectric layer 26, the first epitaxial layer
The size of 25 threes is identical.Grid region material can be metal or polysilicon.Grid region material can be covered in by depositing operation
On gate dielectric layer 26.
By step S23, can prepare to form the first epitaxial layer 25, gate dielectric layer 26 and grid region 23.Herein, as in addition
Embodiment, sequentially form semiconductor layer, dielectric layer and grid region material on semiconductor bar, and semiconductor layer is had
One the 3rd groove 251, semiconductor bar are located in the 3rd groove 251, and dielectric layer has one second groove 261, and semiconductor layer is located at second
In groove 261, grid region material has one first groove 233, and dielectric layer is located in the first groove 233, to grid region material, dielectric
The both ends of layer and semiconductor layer three in a first direction on Y perform etching simultaneously, form grid region 23 with disposable preparation, grid are situated between
The epitaxial layer 25 of matter layer 26 and first, so as to simplify technique, it is easy to prepare shaping.
Step S24, electrode contact structure is formed, each drain region, source region and grid region are respectively connected with electrode contact structure, with right
Drain electrode, source electrode and grid should be formed.Electrode contact structure can prepare to be formed by metal contact process.
In the implementation of this preparation method, depositing operation can by low-pressure chemical vapor deposition (LPCVD) or
Physical vapour deposition (PVD) (PVD), epitaxy technique can be MBE epitaxy techniques.The material of hard mask layer can be silica, nitridation
Any one in silicon and silicon oxy-nitride material.
As shown in figure 28, the section signal of the tunneling field-effect transistor provided for the 3rd better embodiment of the invention
Figure.The overall structure of this 3rd embodiment is substantially the same with first embodiment, herein only to being retouched with difference part
State, other parts repeat no more.
In this 3rd embodiment, in a first direction, the first epitaxial layer 38 is identical with the size of source region 31；In second party
Upwards, two the first epitaxial layers 38 and the three's overall dimensions of source region 31 are identical with the size of channel layer 303, and two the first extensions
Layer 38 and the overall setting of being alignd with channel layer 303 of the three of source region 21, can cause two the first epitaxial layers 38 to be located at two raceway grooves
Between layer 303, so as to reduce the size of whole device in a second direction.
The first drain electrode 320 for being connected to the first drain region 32 is arranged on the first surface of the drain region 32 away from source region 31, so as to
It is easy to the preparation of the first drain electrode 320 to be molded.
As shown in figure 29, the section signal of the tunneling field-effect transistor provided for the 4th better embodiment of the invention
Figure.The overall structure of this 4th embodiment is substantially the same with the 3rd embodiment, herein only to being retouched with difference part
State, other parts repeat no more.
In this 4th embodiment, formed with the second epitaxial layer 49 between the first epitaxial layer 48 and source region 41.Outside first
Prolong layer 48 with the doping type of the second epitaxial layer 49 on the contrary, the doping type of second epitaxial layer 49 and mixing for the source region 41
Miscellany type is identical, and the doping concentration of second epitaxial layer 49 is more than the doping concentration of the source region 41.So can be with source region 41
One very precipitous concentration gradient of upper formation, i.e., form a precipitous p-n tunnelling between the epitaxial layer 48 of source region 41 and first
Knot, and then tunnelling probability can be increased, improve tunnelling current.The tunneling field-effect transistor is preparing the in preparation process
Before one epitaxial layer, the second epitaxial layer of shaping is prepared first in source region, then prepare and to form the first epitaxial layer.
Herein, in the tunneling field-effect transistor that first embodiment and second embodiment provide, the first epitaxial layer
One above-mentioned second epitaxial layer can be set between source region, a precipitous p-n is formed between source region and the first epitaxial layer
Tunnel junctions, increase tunnelling probability, improve tunnelling current.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
To be modified to the technical scheme described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (20)
- A kind of 1. tunneling field-effect transistor, it is characterised in that the tunneling field-effect transistor include source region, two drain regions and Two grid regions；Two drain regions are respectively arranged at the relative both sides of the source region in the first direction, the source region and two drain regions Between be equipped with channel layer, the raceway groove that the channel layer is formed between the source region and the drain region；Two grid regions are respectively arranged at the relative both sides of the source region in a second direction, and the second direction is vertically described First direction；The first epitaxial layer and gate dielectric layer are equipped between the source region and two grid regions；First epitaxial layer is set Put between the source region and the gate dielectric layer, first epitaxial layer forms p-n tunnel junctions with the source region；The grid are situated between The one side away from first epitaxial layer is connected with the grid region on matter layer, and the gate dielectric layer is used for first epitaxial layer Isolate with the grid region.
- 2. the tunneling field-effect transistor as described in any one of claim 1, it is characterised in that the first direction is relative institute The above-below direction of source region is stated, the second direction is the left and right directions of relatively described source region；Two drain regions include the first drain region and the second drain region；First drain region is located at the underface of the source region, and described Two drain regions are located at the surface of the source region；In this second direction, the overall dimension of two grid regions and the source region is equal to or less than the chi in first drain region Very little, the source region is located at the surface in first drain region centre position, and two grid regions are respectively arranged at first drain region Surface at both ends.
- 3. tunneling field-effect transistor as claimed in claim 2, it is characterised in that the channel layer include the first channel layer with Second channel layer, first channel layer are arranged between the source region and the first drain region, and second channel layer is arranged on institute State between source region and second drain region；First channel layer, the source region, second channel layer and second drain region Size in this second direction is identical, and alignment is set in said first direction.
- 4. tunneling field-effect transistor as claimed in claim 2, it is characterised in that on first drain region with the source region phase Corresponding opening position raises up to form boss.
- 5. tunneling field-effect transistor as claimed in claim 2, it is characterised in that the shape and structure in two grid regions is identical, And relatively described source region is symmetrical arranged.
- 6. tunneling field-effect transistor as claimed in claim 5, it is characterised in that the grid region is L-shaped, and its two support arm is distinguished For Part I and Part II, the Part I is oppositely arranged with the source region, and the Part II is from described first The bottom divided extends towards the direction away from the source region.
- 7. tunneling field-effect transistor as claimed in claim 6, it is characterised in that two grid regions and first drain region it Between be equipped with separation layer, the separation layer isolates in the grid region with first drain region.
- 8. the tunneling field-effect transistor as described in any one of claim 1, it is characterised in that the grid region is on third direction One end towards another grid region extend formed with grid connecting portion, the connecting portion on third direction be located at the source region side, The third direction is both perpendicular to the first direction and second direction；Two grid regions are connected simultaneously by the grid connecting portion Form one first groove；The one end of the gate dielectric layer on third direction extends to form media connection towards another gate dielectric layer, and two grid are situated between Matter layer is connected by the media connection and forms one second groove；The one end of first epitaxial layer on third direction extends to form extension connecting portion towards another first epitaxial layer, described in two First epitaxial layer is connected by the extension connecting portion and forms one the 3rd groove；The media connection, the extension connecting portion and the grid connecting portion are located at the same of the source region on third direction Side；The media connection is between the grid connecting portion and the extension connecting portion, and the media connection is by the grid Connecting portion is isolated with the extension connecting portion；The extension connecting portion is described between the grid connecting portion and the source region P-n tunnel junctions are formed between extension connecting portion and the source region；Two gate dielectric layers are embedded in first groove, and two first epitaxial layers are embedded in second groove, described Source region is embedded in the 3rd groove.
- 9. tunneling field-effect transistor as claimed in claim 8, it is characterised in that the shape and structure phase in two drain regions Together；The relatively described source region in two drain regions is symmetrical arranged.
- 10. tunneling field-effect transistor as claimed in claim 8, it is characterised in that the tunneling field-effect transistor also wraps Include substrate, the substrate and the grid connecting portion are respectively arranged on the third direction at the relative both sides of the source region；In a first direction, the overall dimension of two drain regions, the channel layer and the source region is equal to or less than the substrate Size；In a second direction, the overall chi of two grid regions, the gate dielectric layer, first epitaxial layer and the source region The very little size equal to or less than the substrate.
- 11. the tunneling field-effect transistor as described in claim any one of 1-10, it is characterised in that first epitaxial layer with Formed with the second epitaxial layer between the source region；The doping type of first epitaxial layer and second epitaxial layer is on the contrary, institute State that the doping type of the second epitaxial layer is identical with the doping type of the source region, the doping concentration of second epitaxial layer is more than institute The doping concentration of source region is stated, to form precipitous p-n tunnel junctions between first epitaxial layer and the source region.
- 12. tunneling field-effect transistor as claimed in claim 1, it is characterised in that tunneling field-effect transistor also includes electricity Pole contact structures, respectively correspond in the grid region, drain region and source region and be connected with electrode contact structure, with formed respectively grid, Drain electrode and source electrode.
- 13. a kind of preparation method of tunneling field-effect transistor, it is characterised in that comprise the following steps：One substrate is provided；Drain region and source region are formed over the substrate, and the drain region is two, and two drain regions are set respectively in a second direction At the relative both sides of the source region, channel layer is equipped between the source region and two drain regions, the channel layer forms institute State the raceway groove between source region and the drain region；Prepare the first epitaxial layer of formation, gate dielectric layer and grid region, two grid regions and be respectively arranged at the source in a second direction At the relative both sides in area, the vertical first direction of the second direction；Is equipped between the source region and two grid regions One epitaxial layer and gate dielectric layer；First epitaxial layer is arranged between the source region and the gate dielectric layer, outside described first Prolong layer and form p-n tunnel junctions with the source region；One side away from first epitaxial layer and the grid region on the gate dielectric layer Connection, the gate dielectric layer are used to isolate first epitaxial layer with the grid region.
- 14. the preparation method of tunneling field-effect transistor according to claim 13, it is characterised in that the two drain region bags Include the first drain region and the second drain region；The channel layer includes the first channel layer and the second channel layer, and first channel layer is set Between the source region and the first drain region, second channel layer is arranged between the source region and second drain region；Comprise the following steps in step " forming drain region and source region over the substrate "：The first semiconductor layer is formed on substrate, to prepare the first drain region；The second semiconductor layer is formed on first semiconductor layer, to prepare first channel layer；The 3rd semiconductor layer is formed on second semiconductor layer, to prepare the source region；The 4th semiconductor layer is formed on the 3rd semiconductor layer, to prepare second channel layer；The 5th semiconductor layer is formed on the 4th semiconductor layer, to prepare second drain region；Deposit a hard mask layer on the 5th semiconductor layer, the part at etching hard mask layer both ends in a second direction, only Retain hard mask layer in a second direction among part；Using the hard mask layer as mask, the 5th semiconductor layer, the 4th semiconductor layer, the 3rd semiconductor layer and the are etched Two semiconductor layers, make this four layers part only retained immediately below the hard mask layer；Remove the hard mask layer.
- 15. the preparation method of tunneling field-effect transistor according to claim 14, it is characterised in that in step " with institute It is mask to state hard mask layer, etches the 5th semiconductor layer, the 4th semiconductor layer, the 3rd semiconductor layer and second semiconductor Layer, make this four layers part only retained immediately below the hard mask layer " after, the step " removing the hard mask layer " Before, in addition to step：Using hard mask layer as mask, first semiconductor layer is etched, to cause the first semiconductor layer in institute The middle part stated in second direction forms a boss.
- 16. the preparation method of tunneling field-effect transistor according to claim 14, it is characterised in that in the step Comprise the following steps in " prepare and form the first epitaxial layer, gate dielectric layer and grid region "：Two separation layers are prepared on first drain region, two separation layers are separately positioned on the two of the source region in a second direction At side；The first epitaxial layer and gate dielectric layer, first epitaxial layer and the gate dielectric layer position are respectively formed in the both sides of the source region In the top of the separation layer；AndGrid region is formed in side of each gate dielectric layer away from the source region, the grid region is located above the separation layer.
- 17. the preparation method of tunneling field-effect transistor according to claim 13, it is characterised in that in the step Comprise the following steps in " forming drain region and source region over the substrate "：It is square into semiconductor bar over the substrate；The middle part for being located at the first direction in the semiconductor bar forms source region；AndIt is located to be formed at both ends relative on the first direction in the semiconductor bar and forms a drain region, the semiconductor respectively Part of the bar between the drain region and the source region forms the channel layer.
- 18. the preparation method of tunneling field-effect transistor according to claim 17, it is characterised in that the source region and institute Drain region is stated to be formed by ion implantation technology.
- 19. the preparation method of tunneling field-effect transistor according to claim 17, it is characterised in that the step " system Comprise the following steps in the first epitaxial layer of standby formation, gate dielectric layer and grid region "：Form semiconductor layer on the semiconductor bar, and cause the semiconductor layer that there is an opening the towards the source region Three grooves, the source region are located in the 3rd groove；The both ends of the semiconductor layer in a first direction are etched, two are formed to prepare First epitaxial layer and its extension connecting portion；In a first direction, exist between the end of first epitaxial layer and the drain region Spacing, and the size of first epitaxial layer is more than or equal to the size of the source region；Dielectric layer is formed on first epitaxial layer, and causes the dielectric layer that there is an opening towards the source region Second groove, and first epitaxial layer is located in second groove；The both ends of the dielectric layer in a first direction are etched, with Prepare and form two gate dielectric layers and media connection；In said first direction, the gate dielectric layer and first epitaxial layer The size of the two is identical；Grid region material is covered on the gate dielectric layer so that the grid region material forms an opening towards the first of the source region Groove, and the gate dielectric layer is located in first groove；The both ends of the grid region material in a first direction are etched, to prepare Form two grid regions and its grid connecting portion；In a first direction, the grid region and gate dielectric layer, the size phase of the first epitaxial layer three Together.
- 20. the preparation method of tunneling field-effect transistor according to claim 13, it is characterised in that the tunnelling field effect Answering the preparation method of transistor also includes step：Electrode contact structure is formed, each drain region, source region and grid region are respectively connected with electrode Contact structures, to be correspondingly formed drain electrode, source electrode and grid.
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| WO2017079979A1 (en) * | 2015-11-13 | 2017-05-18 | 华为技术有限公司 | Tunnel field-effect transistor, and manufacturing method thereof |
| CN109429526B (en) * | 2017-06-30 | 2021-10-26 | 华为技术有限公司 | Tunneling field effect transistor and preparation method thereof |
| WO2024138687A1 (en) * | 2022-12-30 | 2024-07-04 | 复旦大学 | Gate-all-around transistor based on hybrid conduction mechanism, and manufacturing method therefor |
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| CN102272933A (en) * | 2008-12-30 | 2011-12-07 | 英特尔公司 | Tunnel field effect transistor and method of manufacturing same |
| CN103474459A (en) * | 2013-09-06 | 2013-12-25 | 北京大学深圳研究生院 | Tunneling field effect transistor |
| CN104201198A (en) * | 2014-08-01 | 2014-12-10 | 华为技术有限公司 | Tunneling transistor structure and manufacturing method thereof |
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| US8975123B2 (en) * | 2013-07-09 | 2015-03-10 | International Business Machines Corporation | Tunnel field-effect transistors with a gate-swing broken-gap heterostructure |
| CN104617138B (en) * | 2015-01-26 | 2017-12-08 | 华为技术有限公司 | Tunneling field-effect transistor and preparation method thereof |
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| CN102272933A (en) * | 2008-12-30 | 2011-12-07 | 英特尔公司 | Tunnel field effect transistor and method of manufacturing same |
| CN103474459A (en) * | 2013-09-06 | 2013-12-25 | 北京大学深圳研究生院 | Tunneling field effect transistor |
| CN104201198A (en) * | 2014-08-01 | 2014-12-10 | 华为技术有限公司 | Tunneling transistor structure and manufacturing method thereof |
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