CN106548983B - Semiconductor devices and forming method thereof - Google Patents

Semiconductor devices and forming method thereof Download PDF

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Publication number
CN106548983B
CN106548983B CN201510612767.4A CN201510612767A CN106548983B CN 106548983 B CN106548983 B CN 106548983B CN 201510612767 A CN201510612767 A CN 201510612767A CN 106548983 B CN106548983 B CN 106548983B
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source
core
drain area
periphery
area
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CN106548983A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Abstract

A kind of semiconductor devices and forming method thereof, wherein the forming method of semiconductor devices includes: to carry out the first ion implantation technology to the peripheral region the PMOS substrate of first grid structure two sides, and the first gradual interface is formed below the first periphery source-drain area；Second ion implantation technology is carried out to the first periphery source-drain area and the first core source-drain area, forms the first contact resistance area on the first periphery source-drain area surface and the first core source-drain area surface；Third ion implantation technology is carried out to the peripheral region the NMOS substrate of third gate structure two sides, forms the second gradual interface below the second periphery source-drain area；4th ion implantation technology is carried out to the second periphery source-drain area and the second core source-drain area, forms the second contact resistance area on the second periphery source-drain area surface and the second core source-drain area surface.The present invention improves the short channel effect problem of core devices, while reducing the junction leakage of input/output device so as to improve the electric property of the semiconductor devices of formation.

Description

Semiconductor devices and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of semiconductor devices and forming method thereof.
Background technique
Metal-oxide semiconductor (MOS) (MOS, Metal-Oxide-Semiconductor) device has been known as in integrated circuit often One of semiconductor devices.The MOS device includes: P type metal oxide semiconductor (PMOS, P-type MOS) device, N Type metal oxide semiconductor (NMOS, N-type MOS) device and CMOS complementary metal-oxide-semiconductor (CMOS, Complementary MOS) device.
Metal oxide semiconductor device is broadly divided into core (Core) device and periphery (I/O) device according to function distinguishing (or being input/output device).It is distinguished according to the conductivity type of metal oxide semiconductor device, core devices can be divided into core Heart NMOS device and core PMOS device, input/output device can be divided into input/output NMOS device and input/output PMOS Device.
Under normal conditions, much bigger than the operating voltage of core devices of the operating voltage of input/output device.To prevent electricity The problems such as breakdown, when the operating voltage of device is bigger, it is desirable that the thickness of the gate dielectric layer of device is thicker, therefore, input/output The thickness of the gate dielectric layer of device is typically larger than the thickness of the gate dielectric layer of core devices.
However, the semiconductor devices that the prior art is formed still remains the poor problem of electric property.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, so that core devices and input/ The performance of output device is improved, to optimize the electric property of semiconductor devices.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: providing includes core space With the substrate of peripheral region, the core space includes NMOS core space and PMOS core space, and the peripheral region includes the peripheral region NMOS With the peripheral region PMOS, wherein the peripheral region PMOS substrate surface is formed with first grid structure, the PMOS core space substrate Surface is formed with second grid structure, and the peripheral region NMOS substrate surface is formed with third gate structure, the NMOS core Area's substrate surface is formed with the 4th gate structure, is formed with first in the peripheral region the PMOS substrate of first grid structure two sides Periphery source-drain area, is formed with the first core source-drain area in the PMOS core space substrate of second grid structure two sides, and described The second periphery source-drain area is formed in the peripheral region the NMOS substrate of three gate structure two sides, the 4th gate structure two sides The second core source-drain area is formed in NMOS core space substrate；To the peripheral region the PMOS substrates of first grid structure two sides into The first ion implantation technology of row forms the first gradual interface, first ion implanting below the source-drain area of first periphery The injection ion of technique is P-type ion；Second ion implanting is carried out to first periphery source-drain area and the first core source-drain area Technique forms the first contact resistance area on the first periphery source-drain area surface and the first core source-drain area surface, and described second The injection ion of ion implantation technology is P-type ion；The is carried out to the peripheral region the NMOS substrates of third gate structure two sides Three ion implantation technologies form the second gradual interface, the third ion implantation technology below the source-drain area of second periphery Injection ion be N-type ion；4th ion implantation technology is carried out to second periphery source-drain area and the second core source-drain area, The second contact resistance area, the 4th ion note are formed on the second periphery source-drain area surface and the second core source-drain area surface The injection ion for entering technique is N-type ion.
Optionally, the Doped ions concentration in the described first gradual interface is dense less than the Doped ions of the first periphery source-drain area Degree；The Doped ions concentration in first contact resistance area is greater than the Doped ions concentration of first periphery source-drain area；It is described Doped ions concentration of the Doped ions concentration in the second gradual interface less than the second periphery source-drain area；Second contact resistance area Doped ions concentration be greater than the second periphery source-drain area Doped ions concentration.
Optionally, it includes B that the technological parameter of first ion implantation technology, which includes: injection ion, and Implantation Energy is 5KeV to 15KeV, injection ion dose are 1E13atom/cm2To 1E14atom/cm2, tilted ion implantation angle is 0 degree to 15 Degree.
Optionally, it includes BF that the technological parameter of second ion implantation technology, which includes: injection ion,2, Implantation Energy is 2KeV to 5KeV, injection ion dose are 1E15atom/cm2To 1E16atom/cm2, tilted ion implantation angle is 0 degree to 5 degree.
Optionally, it includes P that the technological parameter of the third ion implantation technology, which includes: injection ion, and Implantation Energy is 100eV to 5KeV, injection ion dose are 1E15atom/cm2To 5E15atom/cm2, tilted ion implantation angle is 0 degree to 15 Degree.
Optionally, it includes P that the technological parameter of the 4th ion implantation technology, which includes: injection ion, and Implantation Energy is 100eV to 5KeV, injection ion dose are 1E15atom/cm2To 5E15atom/cm2, tilted ion implantation angle is 0 degree to 15 Degree.
Optionally, it further comprises the steps of: to the described first gradual interface, the first contact resistance area, the second gradual interface and Two contact resistance areas are made annealing treatment.
Optionally, the technological parameter of the annealing includes: using spike annealing process, and annealing temperature is 950 Celsius Degree is to 1000 degrees Celsius.
Optionally, the first edge stress layer is formed in the source-drain area of first periphery；In the first core source-drain area It is formed with the first core stressor layers；The second periphery stressor layers are formed in the source-drain area of second periphery；Second core source The second core stressor layers are formed in drain region.
Optionally, the material of the first edge stress layer is SiGe or SiGeB；The material of the first core stressor layers For SiGe or SiGeB；The material of second periphery stressor layers is SiC or SiCP；The material of the second core stressor layers is SiC or SiCP.
Optionally, forming first periphery source-drain area and the processing step of the first core source-drain area includes: etching first The substrate of the peripheral region the PMOS segment thickness of gate structure two sides, the PMOS core region for etching second grid structure two sides are thick The substrate of degree forms opening in the substrate of first grid structure two sides and in the substrate of second grid structure two sides； The the first edge stress layer for filling the opening of full first grid structure two sides is formed, the full second grid knot of filling is formed simultaneously First core stressor layers of the opening of structure two sides.
Optionally, auto-dope in situ is carried out during forming the first edge stress layer forms the first periphery source and drain Area carries out auto-dope in situ during forming the first core stressor layers and forms the first core source-drain area；Alternatively, in shape After the first edge stress layer and the first core stressor layers, to the first edge stress layer and the first core stressor layers Ion implanting is carried out, first periphery source-drain area and the first core source-drain area are formed.
Optionally, the substrate includes substrate and several discrete fins positioned at substrate surface；The first grid Structure covers the peripheral region PMOS fin atop part and sidewall surfaces across the peripheral region PMOS fin；The second grid knot Structure covers PMOS core space fin atop part and sidewall surfaces across PMOS core space fin；The third gate structure Across the peripheral region NMOS fin, and cover the peripheral region NMOS part fin top and sidewall surfaces；4th gate structure is horizontal Across NMOS core space fin, and cover NMOS core region fin top and sidewall surfaces.
The present invention also provides a kind of forming methods of semiconductor devices, comprising: provides the base including core space and peripheral region Bottom, the core space substrate surface are formed with first grid structure, and the peripheral region substrate surface is formed with second grid structure, Core source-drain area, the periphery of second grid structure two sides are formed in the core space substrate of first grid structure two sides Periphery source-drain area is formed in area's substrate, wherein the core source-drain area is identical with the Doped ions type of periphery source-drain area；It is right The peripheral region substrate of second grid structure two sides carries out the first ion implantation technology, is formed below the periphery source-drain area The injection ionic type in gradual interface, first ion implantation technology is identical as the Doped ions type of periphery source-drain area；It is right The periphery source-drain area and core source-drain area carry out the second ion implantation technology, on periphery source-drain area surface and core source and drain Area surface forms contact resistance area, the Doped ions of the injection ionic type and core source-drain area of second ion implantation technology Type is identical.
Optionally, the Doped ions concentration in the gradual interface is less than the Doped ions concentration of the periphery source-drain area；Institute The Doped ions concentration for stating contact resistance area is greater than the Doped ions concentration of the periphery source-drain area and the core source-drain area.
Optionally, edge stress layer is formed in the periphery source-drain area；Core is formed in the core source-drain area to answer Power layer.
Correspondingly, the present invention also provides a kind of semiconductor devices, comprising: the substrate including core space and peripheral region, it is described Core space includes NMOS core space and PMOS core space, and the peripheral region includes the peripheral region NMOS and the peripheral region PMOS, wherein institute It states the peripheral region PMOS substrate surface and is formed with first grid structure, the PMOS core space substrate surface is formed with second grid knot Structure, the peripheral region NMOS substrate surface are formed with third gate structure, and the NMOS core space substrate surface is formed with the 4th Gate structure, is formed with the first periphery source-drain area in the peripheral region the PMOS substrate of first grid structure two sides, and described second The first core source-drain area, the NMOS of third gate structure two sides are formed in the PMOS core space substrate of gate structure two sides It is formed with the second periphery source-drain area in the substrate of peripheral region, is formed in the NMOS core space substrate of the 4th gate structure two sides Second core source-drain area；The first gradual interface below the source-drain area of first periphery, the first gradual interface are mixed Heteroion is P-type ion；The first contact resistance positioned at the first periphery source-drain area surface and the first core source-drain area surface Area, the Doped ions in first contact resistance area are P-type ion；Second below the source-drain area of second periphery is gradual Interface, the Doped ions in the second gradual interface are N-type ion；Positioned at the second periphery source-drain area surface and the second core The second contact resistance area on source-drain area surface, the Doped ions in second contact resistance area are N-type ion.
Optionally, the Doped ions concentration in the described first gradual interface is dense less than the Doped ions of the first periphery source-drain area Degree；The Doped ions concentration in first contact resistance area is greater than the Doped ions concentration of first periphery source-drain area；, described Doped ions concentration of the Doped ions concentration in the second gradual interface less than the second periphery source-drain area；Second contact resistance area Doped ions concentration be greater than the second periphery source-drain area Doped ions concentration.
Optionally, the first edge stress layer is formed in the source-drain area of first periphery；In the first core source-drain area It is formed with the first core stressor layers；The second periphery stressor layers are formed in the source-drain area of second periphery；Second core source The second core stressor layers are formed in drain region.
The present invention also provides a kind of semiconductor devices, comprising: the substrate including core space and peripheral region, the core space base Bottom surface is formed with first grid structure, and the peripheral region substrate surface is formed with second grid structure, the first grid knot It is formed with core source-drain area in the core space substrate of structure two sides, is formed in the peripheral region substrate of second grid structure two sides Periphery source-drain area, wherein the core source-drain area is identical with the Doped ions type of periphery source-drain area；Positioned at the periphery source and drain Gradual interface below area, the Doped ions type in the gradual interface and the Doped ions type of periphery source-drain area are identical；Position In the contact resistance area on periphery source-drain area surface and core source-drain area surface, the Doped ions type in the contact resistance area It is identical as the Doped ions type of core source-drain area.
Compared with prior art, technical solution of the present invention has the advantage that
First ion implantation technology is carried out to the peripheral region the PMOS substrate of first grid structure two sides, on first periphery The first gradual interface is formed below source-drain area, first graded transition junction is suitable for making being formed between the first periphery source-drain area and substrate slow Become knot, so as to improve the junction leakage of PMOS input/output device；To the peripheral region the NMOS substrates of third gate structure two sides into Row third ion implantation technology forms the second gradual interface, the second gradual interface below the source-drain area of second periphery Suitable for making to form graded transition junction between the second periphery source-drain area and substrate, so as to improve the junction leakage of NMOS input/output device. And the present invention not formed first gradual interface below the first core source-drain area, avoid the formation in the first gradual interface from causing PMOS Occurs short-channel effect in core devices；The not formed second gradual interface below the second core source-drain area avoids second gradual The formation in interface causes short-channel effect occur in NMOS core devices.The present invention balances core devices and input/output device Performance, reduce input/output device junction leakage while, avoid the short channel effect problem of core devices from deteriorating.
Meanwhile the present invention also forms the first contact resistance on the first periphery source-drain area surface and the first core source-drain area surface Area can reduce the contact resistance of PMOS input/output device and the contact resistance of PMOS core devices.Also in the second peripheral source Drain region and the second core source-drain area surface form the second contact resistance area, can reduce the contact electricity of NMOS input/output device The contact resistance of resistance and NMOS core devices.
Further, the first edge stress layer is formed in the source-drain area of first periphery；In the first core source-drain area It is formed with the first core stressor layers；The second periphery stressor layers are formed in the source-drain area of second periphery；Second core source It is formed with the second core stressor layers in drain region, to improve the carrier mobility of the semiconductor devices of formation, further improves The electric property of semiconductor devices.
The present invention also provides a kind of superior semiconductor devices of structural behaviour, wherein is formed below the first periphery source-drain area There is the first gradual interface, the first gradual interface can form graded transition junction between the first periphery source-drain area and substrate, thus Improve the junction leakage of PMOS input/output device.It is formed with the second gradual interface below second periphery source-drain area, described second Gradual interface can form graded transition junction between the second periphery source-drain area and substrate, so as to improve NMOS input/output device Junction leakage.And the first contact resistance area, energy are formed with positioned at the first periphery source-drain area surface and the first core source-drain area surface Enough reduce the contact resistance of PMOS input/output device and PMOS core devices；Positioned at the second periphery source-drain area surface and second Core source-drain area surface is formed with the second contact resistance area, can reduce NMOS input/output device and NMOS core devices Contact resistance.
Detailed description of the invention
Fig. 1 to Figure 14 is the schematic diagram of the section structure for the semiconductor devices forming process that one embodiment of the invention provides.
Specific embodiment
It can be seen from background technology that the electric property for the semiconductor devices that the prior art is formed is to be improved.
It has been investigated that operating voltage (Vdd) difference of core devices and input/output device in semiconductor devices compared with Greatly, for example, the operating voltage of core devices is in 0.8V or so, the operating voltage of input/output device in 1.8V or so or 3.3V left and right.Since operating voltage differs larger, so that the junction leakage (junction of core devices and input/output device Leakage) also significantly different, when the operating voltage of core devices is in 0.8V or so, the junction leakage of core devices exists 0.1pA/ μm to 100pA/ μm, and the operating voltage of input/output device, in 1.8V or so, junction leakage will be greater than 10000pA/μm。
Therefore, the excessive problem of the junction leakage of input/output device in urgent need to resolve semiconductor devices.To solve this Problem, the method generallyd use are as follows: the periphery source-drain area of core source-drain area and input/output device to core devices carry out from Sub- injection technology forms gradual interface below the source-drain area of periphery, to form graded transition junction between periphery source-drain area and substrate (graded junction), to adjust the junction leakage of input/output device.
However, still poor using the electric property of the semiconductor devices of above method formation.Further study show that core Source-drain area is usually to be formed in technique with along with periphery source-drain area, the Doped ions of core source-drain area and periphery source-drain area Concentration is identical.While forming gradual interface below the source-drain area of periphery, gradual interface can be also formed below core source-drain area. For core devices, the gradual interface below core source-drain area will cause the short-channel effect of core devices (SCE, Short Channel Effect) problem is significant, causes the degradation of core devices, influences the whole of semiconductor devices Body performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, to first grid structure two sides The peripheral region PMOS substrate carry out the first ion implantation technology, form the first graded transition junction below the source-drain area of first periphery Area, first graded transition junction be suitable for make to form graded transition junction between the first periphery source-drain area and substrate, so as to improve PMOS input/it is defeated The junction leakage of device out；Third ion implantation technology is carried out to the peripheral region the NMOS substrate of third gate structure two sides, in institute It states and forms the second gradual interface below the second periphery source-drain area, the second gradual interface is suitable for making the second periphery source-drain area and base Graded transition junction is formed between bottom, so as to improve the junction leakage of NMOS input/output device.And the present invention is in the first core source-drain area The gradual interface in lower section not formed first, avoids the formation in the first gradual interface from causing occur short channel effect in PMOS core devices It answers；Not formed second gradual interface, avoids the formation in the second gradual interface from causing NMOS core below the second core source-drain area Occurs short-channel effect in device.
The present invention balances the performance of core devices and input/output device, in the junction leakage for reducing input/output device While, avoid the short channel effect problem of core devices from deteriorating；Meanwhile reducing core devices and input/output device Contact resistance, thus the overall performance of the semiconductor devices effectively improved.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Fig. 1 to Figure 14 is the schematic diagram of the section structure for the semiconductor devices forming process that one embodiment of the invention provides.
With reference to Fig. 1, the substrate including core space and peripheral region is provided.
The core space provides technique platform to form core devices；The peripheral region is to form input/output device to mention For Process ba- sis, and the operating voltage of input/output device is higher than the operating voltage of core devices.The present embodiment is with semiconductor device Part is cmos device as example.
The core space includes PMOS core space 110 and NMOS core space 130, and the PMOS core space 110 is to be formed PMOS core devices provide technique platform, and the NMOS core space 130 provides technique platform to form NMOS core devices.It is described Peripheral region includes the peripheral region PMOS 120 and the peripheral region NMOS 140, and the peripheral region PMOS 120 is to form PMOS input/output device Part provides technique platform, and the peripheral region NMOS 140 provides technique platform to form NMOS input/output device.
In the present embodiment, with PMOS core space 110, the peripheral region PMOS 120, NMOS core space 130 and the peripheral region NMOS 140 For being arranged successively.In other embodiments, PMOS core space, the peripheral region PMOS, NMOS core space can be determined according to demand With the position of the peripheral region NMOS.
The material of the substrate is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium；The substrate can also be exhausted The SiGe substrate in silicon base or insulator on edge body.
The present embodiment by semiconductor devices be fin field effect pipe for, the substrate include substrate 101 and be located at lining Several discrete fins 102 on 101 surface of bottom.The material of the substrate 101 be silicon, germanium, SiGe, silicon carbide, GaAs or Gallium indium；The material of the fin 102 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the material of the substrate 101 is silicon, and the material of the fin 102 is silicon.It is embodied at one In example, the processing step for forming the substrate includes: offer initial substrate；Patterned cover is formed in the initial substrate surface Film layer；Using the patterned mask layer as exposure mask, etch the initial substrate, the initial substrate after etching as substrate 101, The protrusion on 101 surface of substrate is as fin 102.
In order to make to be electrically insulated between adjacent fin 102, the substrate further include: the dielectric layer positioned at 101 surface of substrate 103, the dielectric layer 103 covers 102 partial sidewall surface of fin, and lower than 102 top of fin at the top of the dielectric layer 103. The dielectric layer 103 is used to form the isolation structure of semiconductor devices.
In other embodiments, the semiconductor devices of formation can also be planar device, and the substrate is made of substrate.
With reference to Fig. 2 and Fig. 3, first grid structure 111 is formed in 120 substrate surface of the peripheral region PMOS；Described 110 substrate surface of PMOS core space forms second grid structure 112；Third is formed in 140 substrate surface of the peripheral region NMOS Gate structure 113 forms the 4th gate structure 114 in 130 substrate surface of NMOS core space.
Fig. 2 and Fig. 3 is the schematic diagram of the section structure that the cutting wire cutting parallel with 102 orientation of fin is formed, In, Fig. 2 shows the cutting line of the schematic diagram of the section structure do not cut to first grid structure 111, second grid structure 112, Three gate structures 113 and the 4th gate structure 114, the cutting line of the schematic diagram of the section structure shown in Fig. 3 cut to first grid Structure 111, second grid structure 112, third gate structure 113 and the 4th gate structure 114.
In the present embodiment, the first grid structure 111 covers the periphery PMOS across 120 fin 102 of the peripheral region PMOS 120 fin of area, 102 atop part and sidewall surfaces；The second grid structure 112 across 110 fin 102 of PMOS core space, and Cover 110 fin of PMOS core space, 102 atop part and sidewall surfaces；The third gate structure 113 is across the peripheral region NMOS 140 fins 102, and cover 140 fin of the peripheral region NMOS, 102 atop part and sidewall surfaces；4th gate structure 114 is horizontal Across NMOS 130 fin 102 of core space, and cover 130 fin of NMOS core space, 102 atop part and sidewall surfaces.
The first grid structure 111 includes the first gate dielectric layer and the first grid electricity positioned at first grid dielectric layer surface Pole layer；The second grid structure 112 includes the second gate dielectric layer and the second gate electrode positioned at second gate dielectric layer surface Layer；The third gate structure 113 includes third gate dielectric layer and the third gate electrode layer positioned at third gate dielectric layer surface； 4th gate structure 114 includes the 4th gate dielectric layer and the 4th gate electrode layer positioned at the 4th gate dielectric layer surface.
The material of first gate dielectric layer is silica or high-k gate dielectric material, and high-k gate dielectric material refers to relatively Dielectric constant is greater than the material of silica relative dielectric constant, for example, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthana, oxidation Zirconium silicon, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.
The material of second gate dielectric layer is silica or high-k gate dielectric material；The material of the third gate dielectric layer For silica or high-k gate dielectric material；The material of 4th gate dielectric layer is silica or high-k gate dielectric material.
The first gate electrode layer, the second gate electrode layer, third grid electrode layer and the 4th gate electrode layer material be electricity Pole material, wherein electrode material can be polysilicon, the polysilicon of doping, titanium nitride, tantalum nitride, copper, tungsten, aluminium, gold or silver.
In a specific embodiment, the first grid structure 111, second grid structure 112, third grid knot are formed The processing step of structure 113 and the 4th gate structure 114 includes: in 102 top of fin and sidewall surfaces and dielectric layer 103 surfaces form gate dielectric film；Gate electrode film is formed on the gate dielectric film surface；The graphical peripheral region PMOS 120 Gate electrode film and gate dielectric film form the first grid structure 111；The gate electrode film of the graphical PMOS core space 110 And gate dielectric film, form the second grid structure 112；The gate electrode film and gate medium of the graphical peripheral region NMOS 140 Film forms the third gate structure 113；The gate electrode film and gate dielectric film of the graphical NMOS core space 130, form institute State the 4th gate structure 114.
In the present embodiment, 111 sidewall surfaces of first grid structure, 112 sidewall surfaces of second grid structure, third grid Pole structure side wall surface 113 and the 4th gate structure sidewall surface 114 are also formed with side wall 104, and the side wall 104 is also covered in The partial sidewall surface of fin 102.In other embodiments, the first grid structure, second grid structure, third grid knot Structure or the 4th gate structure can also be pseudo- grid structure (dummy gate).
Unless otherwise instructed, the structural schematic diagram of subsequent offer is the schematic diagram on the basis of Fig. 2.
In conjunction with reference Fig. 3 and Fig. 4, first is carried out to 130 substrate of NMOS core space of 114 two sides of the 4th gate structure Doping treatment forms the second core lightly doped district in 130 substrate of NMOS core space of 114 two sides of the 4th gate structure.
The second core lightly doped district is used to form LDD (the Lightly Doped Drain) knot of NMOS core devices Structure.The technique that first doping treatment uses is ion implanting；The Doped ions of first doping treatment are N-type ion, For example, P, As or Sb.
In the present embodiment, the processing step for forming the second core lightly doped district includes: to form covering first grid knot Structure 111, second grid structure 112, the 4th gate structure 114,110 dielectric layer 103 of PMOS core space, the peripheral region PMOS 120 are situated between First graph layer on 102 surface of fin other than matter layer 103,140 dielectric layer 103 of the peripheral region NMOS and NMOS core space 130 105；It is exposure mask with first graph layer 105, to 130 fin 102 of NMOS core space of 114 two sides of the 4th gate structure The first doping treatment is carried out, the second core lightly doped district is formed；Remove first graph layer 105.
In the present embodiment, the material of first graph layer 105 is photoresist, is removed photoresist using wet process or cineration technics removes First graph layer 105.
In conjunction with reference Fig. 3 and Fig. 5, second is carried out to 140 substrate of the peripheral region NMOS of 113 two sides of third gate structure Doping treatment forms the second periphery lightly doped district in 140 substrate of the peripheral region NMOS of 113 two sides of third gate structure.
Second periphery lightly doped district is used to form the LDD structure of NMOS input/output device.At second doping The technique used is managed as ion implanting；The Doped ions of second doping treatment are N-type ion, for example, P, As or Sb.
In the present embodiment, the processing step for forming second periphery lightly doped district includes: to form covering first grid knot Structure 111, second grid structure 112, third gate structure 113,110 dielectric layer 103 of PMOS core space, the peripheral region PMOS 120 are situated between The second graph layer on 102 surface of fin other than matter layer 103,130 dielectric layer 103 of NMOS core space and the peripheral region NMOS 140 106；It is exposure mask with the second graph layer 106, to 140 fin 102 of the peripheral region NMOS of 113 two sides of third gate structure The second doping treatment is carried out, second periphery lightly doped district is formed；Remove the second graph layer 106.
In conjunction with reference Fig. 3 and Fig. 6, third is carried out to 110 substrate of PMOS core space of 112 two sides of second grid structure Doping treatment forms the first core lightly doped district in 110 substrate of PMOS core space of 112 two sides of second grid structure.
The first core lightly doped district is used to form the LDD structure of PMOS core devices.The third doping treatment is adopted Technique is ion implanting；The Doped ions of the third doping treatment are P-type ion, for example, B, Ga or In.
In the present embodiment, the processing step for forming the first core lightly doped district includes: to form covering first grid knot Structure 111, third gate structure 113, the 4th gate structure 114,120 dielectric layer 103 of the peripheral region PMOS, NMOS core space 130 are situated between The third graph layer on 102 surface of fin other than matter layer 103,140 dielectric layer 103 of the peripheral region NMOS and PMOS core space 110 107；It is exposure mask with the third graph layer 107, to 110 fin 102 of PMOS core space of 112 two sides of second grid structure Third doping treatment is carried out, the first core lightly doped district is formed；Remove the third graph layer 107.
In conjunction with reference Fig. 3 and Fig. 7, the 4th is carried out to 120 substrate of the peripheral region PMOS of 111 two sides of first grid structure Doping treatment forms the first periphery lightly doped district in 120 substrate of the peripheral region PMOS of 111 two sides of first grid structure.
First periphery lightly doped district is used to form the LDD structure of PMOS input/output device.At 4th doping The technique used is managed as ion implanting；The Doped ions of 4th doping treatment are P-type ion, for example, B, Ga or In.
In the present embodiment, the processing step for forming first periphery lightly doped district includes: to form covering second grid knot Structure 112, third gate structure 113, the 4th gate structure 114,130 dielectric layer 103 of NMOS core space, the peripheral region NMOS 140 are situated between 4th graph layer on 102 surface of fin other than matter layer 103,110 dielectric layer 103 of PMOS core space and the peripheral region PMOS 120 108；With the 4th graph layer 108 for exposure mask, the is carried out to the peripheral regions PMOS 120 of 111 two sides of first grid structure Four doping treatments form first periphery lightly doped district；Remove the 4th graph layer 108.
In conjunction with reference Fig. 3 and Fig. 8, is formed in 120 substrate of the peripheral region PMOS of 111 two sides of first grid structure One periphery source-drain area 122；The first core source is formed in 110 substrate of PMOS core space of 112 two sides of second grid structure Drain region 121.
First periphery source-drain area 122 is used to form the source electrode and drain electrode of PMOS input/output device；First core Heart source-drain area 121 is used to form the source electrode and drain electrode of PMOS core devices.Doped ions in first periphery source-drain area 122 Concentration is identical as the Doped ions concentration in the first core source-drain area 121, the first periphery source-drain area 122, the first core source-drain area Doped ions in 121 are P-type ion.
In the present embodiment, the Doped ions in first periphery source-drain area 122 are B ion, first periphery source and drain B ion concentration is 1E20atom/cm in area 1223To 2E21atom/cm3；Doped ions in the first core source-drain area 121 For B ion, B ion concentration is 1E20atom/cm in the first core source-drain area 1213To 2E21atom/cm3。
In order to improve the carrier mobility of PMOS input/output device and PMOS core devices, first peripheral source It is formed with the first edge stress layer in drain region 122, is formed with the first core stressor layers in the first core source-drain area 121.Institute The material for stating the first edge stress layer is SiGe or SiGeB；The material of the first core stressor layers is SiGe or SiGeB.
The processing step for forming first periphery source-drain area 122 and the first core source-drain area 121 includes: the etching first grid The substrate of 120 segment thickness of the peripheral region PMOS of 111 two sides of pole structure etches the PMOS core of 112 two sides of second grid structure The substrate of 110 segment thickness of area, in the substrate of 111 two sides of first grid structure and 112 two sides of second grid structure Substrate in form opening, in the present embodiment, the opening is located in the fin 102 of 111 two sides of first grid structure, Yi Ji In the fin 102 of two gate structures, 112 two sides；Form first week of the opening for filling full 111 two sides of first grid structure Side stressor layers are formed simultaneously the first core stressor layers for filling the opening of full 112 two sides of second grid structure.
The first edge stress layer and the first core stressor layers are formed using selective epitaxial process.In the present embodiment, Auto-dope (in-situ doping) in situ is carried out during forming the first edge stress layer forms the first periphery source-drain area 122, son doping in situ is carried out during forming the first core stressor layers forms the first core source-drain area 121.At it In his embodiment, additionally it is possible to after forming the first edge stress layer and the first core stressor layers, to first periphery Stressor layers and the first core stressor layers carry out ion implanting, form first periphery source-drain area and the first core source-drain area.
In conjunction with reference Fig. 3 and Fig. 9, is formed in 140 substrate of the peripheral region NMOS of 113 two sides of third gate structure Two periphery source-drain areas 124；The second core source is formed in 130 substrate of NMOS core space of 114 two sides of the 4th gate structure Drain region 123.
Second periphery source-drain area 124 is used to form the source electrode and drain electrode of NMOS input/output device；Second core Heart source-drain area 123 is used to form the source electrode and drain electrode of NMOS core devices.Doped ions in second periphery source-drain area 124 Concentration is identical as the Doped ions concentration in the second core source-drain area 123, the second periphery source-drain area 124, the second core source-drain area Doped ions in 123 are N-type ion.
In the present embodiment, the Doped ions in second periphery source-drain area 124 are P ion, and P ion concentration is 1E20atom/cm3To 2E21atom/cm3；Doped ions in the second core source-drain area 123 are P ion, P ion concentration For 1E20atom/cm3To 2E21atom/cm3.It is moved to improve the carrier of NMOS input/output device and NMOS core devices Shifting rate is formed with the second periphery stressor layers in second periphery source-drain area 124；It is formed in the second core source-drain area 123 There are the second core stressor layers.The material of second periphery stressor layers is SiC or SiCP；The material of the second core stressor layers For SiC or SiCP.
The processing step for forming second periphery source-drain area 124 and the second core source-drain area 123 includes: etching third grid The substrate of 140 segment thickness of the peripheral region NMOS of 113 two sides of pole structure etches the NMOS core of 114 two sides of the 4th gate structure The substrate of 130 segment thickness of area, in the substrate of 113 two sides of third gate structure and 114 two sides of the 4th gate structure Substrate in form opening, in the present embodiment, the opening is located in the fin 102 of 113 two sides of third gate structure, Yi Ji In the fin 102 of four gate structures, 114 two sides；Form the second week for filling the opening of full 113 two sides of third gate structure Side stressor layers are formed simultaneously the second core stressor layers for filling the opening of full 4th gate structure, 114 two sides.
Second periphery stressor layers and the second core stressor layers are formed using selective epitaxial process.In the present embodiment, Auto-dope in situ is carried out during forming the second periphery stressor layers and forms the second periphery source-drain area 124, is forming described the Auto-dope in situ is carried out during two core stressor layers forms the second core source-drain area 123.In other embodiments, additionally it is possible to After forming second periphery stressor layers and the second core stressor layers, second periphery stressor layers and the second core are answered Power layer carries out ion implanting, forms second periphery source-drain area and the second core source-drain area.
In conjunction with reference Fig. 3 and Figure 10, the is carried out to 120 substrate of the peripheral region PMOS of 111 two sides of first grid structure One ion implantation technology forms the first gradual interface 131 below first periphery source-drain area 122.
In the present embodiment, the first ion note is carried out to 120 fin 102 of the peripheral region PMOS of 111 two sides of first grid structure Enter technique, forms the first gradual interface 131.Specifically, forming covering PMOS core space 110,130 and of NMOS core space 5th graph layer 151 of the peripheral region NMOS 140, the 5th graph layer 151 expose 122 surface of the first periphery source-drain area；With 5th graph layer 151 is exposure mask, carries out the first ion implanting to the fin 102 of first periphery source-drain area, 122 lower section Technique forms the first gradual interface 131；Remove the 5th graph layer 151.
Due to the region that the peripheral region PMOS 120 is PMOS input/output device to be formed, PMOS core space 110 is to shape At the region of PMOS core devices, the operating voltage of PMOS input/output device is greater than the operating voltage of PMOS core devices, and The Doped ions concentration of first periphery source-drain area 122 is identical as the Doped ions concentration of the first core source-drain area 121, so that PMOS The junction leakage of input/output device is greater than the junction leakage of PMOS core devices.
For this reason, it may be necessary to form the first gradual interface 131, the first gradual interface below the first periphery source-drain area 122 131 Doped ions concentration less than the first periphery source-drain area 122 Doped ions concentration, thus in the first periphery source-drain area 122 Graded transition junction is formed, between substrate to reduce the junction leakage of PMOS input/output device.
And for PMOS core devices, operating voltage is lower, and after forming the first core source-drain area 121 Very little even can ignore that and disregard the junction leakage of PMOS core devices.If the also shape below the first core source-drain area 121 At the first gradual interface, then the first gradual interface for being located at 121 lower section of the first core source-drain area will cause PMOS core devices Short channel effect problem is serious.
For this purpose, in the present embodiment, the only is carried out to 120 substrate of the peripheral region PMOS of 111 two sides of first grid structure One ion implantation technology forms the first gradual interface 131.The injection ion of first ion implantation technology be p-type from Son, for example, B, Ga or In.
The Implantation Energy of first ion implantation technology is unsuitable too small, and otherwise ion implanting depth is excessively shallow；Described first The Implantation Energy of ion implantation technology should not be too large, otherwise between the first gradual interface 131 and the first periphery source-drain area 122 away from From too far；The implantation dosage of first ion implantation technology also should not be too large, the formation that otherwise the first gradual interface 131 is played The effect of graded transition junction is unobvious.
Amid all these factors consider, in the present embodiment, the technological parameter of first ion implantation technology include: injection from Attached bag includes B, and Implantation Energy is 5KeV to 15KeV, and injection ion dose is 1E13atom/cm2To 1E14atom/cm2, ion note Entering inclination angle (tilt) is 0 degree to 15 degree.
It is 0 degree that first ion implantation technology intermediate ion, which injects rotation angle (twist),.In the present embodiment, first ion The injection number of injection technology is 2 times, in other embodiments, additionally it is possible to according to the Doped ions concentration in the first gradual interface and The technological parameter of first ion implantation technology determines injection number.
With reference to Figure 11, the second ion implanting work is carried out to first periphery source-drain area 122 and the first core source-drain area 121 Skill, on first periphery, 122 surface of source-drain area and 121 surface of the first core source-drain area form the first contact resistance area 141.
Specifically, forming the 6th graph layer 152 of covering NMOS core space 130 and the peripheral region NMOS 140, the 6th figure Shape layer 152 exposes the first periphery source-drain area 122 and the first core source-drain area 121；With the 6th graph layer 152 be exposure mask into Row second ion implantation technology, forms first contact resistance area 141；Remove the 6th graph layer 152.
It is suitable for reducing PMOS input/output device positioned at the first doped resistor area 141 on 122 surface of the first periphery source-drain area Contact resistance；The first contact resistance area 141 positioned at 121 surface of the first core source-drain area is suitable for reducing PMOS core devices Contact resistance.The injection ion of second ion implantation technology is P-type ion, for example, B, Ga or In.
The Doped ions that the Doped ions concentration in first contact resistance area 141 is greater than the first periphery source-drain area 122 are dense Degree；The Doped ions concentration in first contact resistance area 141 is greater than the Doped ions concentration of the first core source-drain area 121.
In the present embodiment, the technological parameter of second ion implantation technology includes: that injection ion includes BF2, inject energy Amount is 2KeV to 5KeV, and injection ion dose is 1E15atom/cm2To 1E16atom/cm2, tilted ion implantation angle is 0 degree to 5 Degree.
The injection rotation angle of second ion implantation technology is 0 degree.In the present embodiment, second ion implantation technology Injection number be 2 times, in other embodiments, can be according to the Doped ions concentration necessary and second in the first contact resistance area Ion implantation technology parameter determines injection number.
In conjunction with reference Fig. 3 and Figure 12, the is carried out to 140 substrate of the peripheral region NMOS of 113 two sides of third gate structure Three ion implantation technologies form the second gradual interface 132 below second periphery source-drain area 124.
In the present embodiment, third ion note is carried out to 140 fin 102 of the peripheral region NMOS of 113 two sides of third grid Enter technique, forms the second gradual interface 132.The PMOS core space 110, the peripheral region PMOS are covered specifically, being formed 120, the 7th graph layer 153 of NMOS core space 130, the 7th graph layer 153 expose the second periphery source-drain area 124；With 7th graph layer 153 is that exposure mask carries out the third ion implantation technology, forms the second gradual interface 132；Removal 7th graph layer 153.
Due to the region that the peripheral region NMOS 140 is NMOS input/output device to be formed, NMOS core space 130 is to shape At the region of NMOS core devices, the operating voltage of NMOS input/output device is greater than the operating voltage of NMOS core devices, and The Doped ions concentration of second periphery source-drain area 124 is identical as the Doped ions concentration of the second core source-drain area 123, so that NMOS Input/input device junction leakage is greater than the junction leakage of NMOS core devices.
For this reason, it may be necessary to form the second gradual interface 132, the second gradual interface below the second periphery source-drain area 124 132 Doped ions concentration less than the second periphery source-drain area 124 Doped ions concentration, thus in the second periphery source-drain area 124 Graded transition junction is formed, between substrate to reduce the junction leakage of NMOS input/output device.
And for NMOS core devices, operating voltage is lower, and after forming the first core source-drain area 123 Very little even can ignore that and disregard the junction leakage of NMOS core devices.If the also shape below the second core source-drain area 123 At the second gradual interface, then the second gradual interface for being located at 123 lower section of the second core source-drain area will cause NMOS core devices Short channel effect problem is significant.
For this purpose, in the present embodiment, only to 140 substrate of the peripheral region NMOS of 113 two sides of third gate structure carry out third from Sub- injection technology forms the second gradual interface 132.The injection ion of the third ion implantation technology is N-type ion, example For example P, As or Sb.
The Implantation Energy of the third ion implantation technology is unsuitable too small, and otherwise ion implanting depth is excessively shallow；The third The Implantation Energy of ion implantation technology also should not be too large, otherwise between the second gradual interface 132 and the second periphery source-drain area 124 Hypertelorism；The implantation dosage of the third ion implantation technology also should not be too large, the shape that otherwise the second gradual interface 132 is played It is unobvious at the effect of graded transition junction.
Amid all these factors consider, in the present embodiment, the technological parameter of the third ion implantation technology include: injection from Attached bag includes P, and Implantation Energy is 100eV to 5KeV, and injection ion dose is 1E15atom/cm2To 5E15atom/cm2, ion note Entering inclination angle is 0 degree to 15 degree.
The injection rotation angle of the third ion implantation technology is 0 degree.In the present embodiment, the third ion implantation technology Injection number be 2 times, in other embodiments, can according to the Doped ions concentration necessary in the second gradual interface and third from Sub- injection technology parameter determines injection number.
With reference to Figure 13, the 4th ion implanting work is carried out to second periphery source-drain area 124 and the second core source-drain area 123 Skill, on second periphery, 124 surface of source-drain area and 123 surface of the second core source-drain area form the second contact resistance area 142.
Specifically, forming the 8th graph layer 154 of covering PMOS core space 110 and the peripheral region PMOS 120, second is exposed 123 surface of 124 surface of periphery source-drain area and the second core source-drain area；It is that exposure mask carries out described the with the 8th graph layer 154 Four ion implantation technologies form second contact resistance area 142；Remove the 8th graph layer 154.
It is suitable for reducing NMOS input/output device positioned at the second contact resistance area 142 on 124 surface of the second periphery source-drain area Overall electrical resistance；The second contact resistance area 142 positioned at 123 surface of the second core source-drain area is suitable for reducing NMOS core devices Contact resistance.The injection ion of 4th ion implantation technology is N-type ion, for example, P, As or Sb.
The Doped ions that the Doped ions concentration in second contact resistance area 142 is greater than the second periphery source-drain area 124 are dense Degree；The Doped ions concentration in second contact resistance area 142 is greater than the Doped ions concentration of the second core source-drain area 123.
In the present embodiment, the technological parameter of the 4th ion implantation technology includes: that injection ion includes P, Implantation Energy For 100eV to 5KeV, injection ion dose is 1E15atom/cm2To 5E15atom/cm2, tilted ion implantation angle is 0 degree to 15 Degree.
The injection rotation angle of 4th ion implantation technology is 0 degree.In the present embodiment, the 4th ion implantation technology Injection number be 2 times, in other embodiments, can be according to the Doped ions concentration necessary and the 4th in the second contact resistance area Ion implantation technology parameter determines injection number.
With reference to Figure 14, to the described first gradual interface 131, the second gradual interface 132, the first contact resistance area 141 and Two contact resistance areas 142 are made annealing treatment.
The effect of the annealing is: on the one hand, the first gradual interface 131 of activation, the second gradual interface 132, the Doped ions in one contact resistance area 141, the second contact resistance area 142, so that Doped ions carry out concentration redistribution；It is another Aspect, the annealing can also repair the first ion implantation technology, the second ion implantation technology, third ion implantation technology The implant damage introduced with the 4th ion implantation technology repairs the lattice defect in fin 102；The annealing can also swash First periphery source-drain area 122, the first core source-drain area 121, the second periphery source-drain area 124 and the second core source-drain area 123 living Interior Doped ions.
The annealing is carried out using laser annealing, spike annealing or rapid thermal anneal process.It is described in the present embodiment The technological parameter of annealing includes: using spike annealing process, and annealing temperature is 950 degrees Celsius to 1000 degrees Celsius.At it In his embodiment, the technological parameter of the annealing includes: using laser annealing technique, and annealing temperature is 1200 degrees Celsius.
In the present embodiment, due to being formed with the first gradual interface 131 below the first periphery source-drain area 122, so that PMOS is defeated Enter/junction leakage of output device reduces, while the present embodiment does not form the first graded transition junction below the first core source-drain area 121 Area becomes serious so as to avoid the short channel effect problem of PMOS core devices.Therefore, the present embodiment balance PMOS input/ The junction leakage problem of output device and the short channel effect problem of PMOS core devices, so that the electricity of the semiconductor devices formed Performance is learned to be improved.Likewise, the present embodiment also balances the junction leakage problem and NMOS core of NMOS input/output device The short channel effect problem of device also can be such that the electric property for the semiconductor devices to be formed is improved.
The present embodiment also provides a kind of semiconductor devices, in conjunction with reference Fig. 3 and Figure 14, comprising:
Substrate including core space and peripheral region, the core space include NMOS core space 130 and PMOS core space 110, The peripheral region includes the peripheral region NMOS 140 and the peripheral region PMOS 120, wherein 120 substrate surface of the peripheral region PMOS is formed There is first grid structure 111,110 substrate surface of PMOS core space is formed with second grid structure 112, the periphery NMOS 140 substrate surface of area is formed with third gate structure 113, and 130 substrate surface of NMOS core space is formed with the 4th grid knot Structure 114；
It is formed with the first periphery source-drain area 122 in 120 substrate of the peripheral region PMOS of 111 two sides of first grid structure, The first core source-drain area 121, the third are formed in 110 substrate of PMOS core space of 112 two sides of second grid structure The second periphery source-drain area 124, the 4th gate structure are formed in 140 substrate of the peripheral region NMOS of 113 two sides of gate structure The second core source-drain area 123 is formed in 130 substrate of NMOS core space of 114 two sides；
The first gradual interface 131 below first periphery source-drain area 122, the first gradual interface 131 Doped ions are P-type ion；
Positioned at the first contact resistance area on first periphery source-drain area, 122 surface and 121 surface of the first core source-drain area 141, the Doped ions in first contact resistance area 141 are P-type ion；
The second gradual interface 132 below second periphery source-drain area 124, the second gradual interface 132 Doped ions are N-type ion；
Positioned at the second contact resistance area on second periphery source-drain area, 124 surface and 123 surface of the second core source-drain area 142, the Doped ions in second contact resistance area 142 are P-type ion.
In the present embodiment, the substrate includes substrate 101 and several discrete fins 102 positioned at 101 surface of substrate. The peripheral region PMOS 120 is the region for being formed with PMOS input/output device, and the PMOS core space 110 is to be formed with The region of PMOS core devices, wherein the operating voltage of PMOS input/output device is greater than the region of PMOS core devices.Institute Stating the peripheral region NMOS 140 is the region for being formed with NMOS input/output device, and the NMOS core space 130 is to be formed with NMOS The region of core devices, the operating voltage of the NMOS input/output device are greater than the operating voltage of NMOS core devices.
The Doped ions concentration of the Doped ions concentration of first periphery source-drain area 122 and the first core source-drain area 121 It is identical；The Doped ions concentration phase of the Doped ions concentration of second periphery source-drain area 124 and the second core source-drain area 123 Together.
The Doped ions concentration in the first gradual interface 131 less than the first periphery source-drain area 122 Doped ions concentration, To form graded transition junction between the first periphery source-drain area 122 and substrate, then reduce the junction leakage of PMOS input/output device Stream.The Doped ions concentration in the second gradual interface 132 less than the second periphery source-drain area 124 Doped ions concentration, thus Graded transition junction is formed between the second periphery source-drain area 124 and substrate, then reduces the junction leakage of NMOS input/output device.
The Doped ions concentration in first contact resistance area 141 is greater than first periphery source-drain area 122 and first The Doped ions concentration of core source-drain area 121 reduces PMOS core to reduce the contact resistance of PMOS input/output device The contact resistance of device.The Doped ions concentration in second contact resistance area 142 be greater than second periphery source-drain area 124, And second the Doped ions concentration of core source-drain area 123 reduce to reduce the contact resistance of NMOS input/output device The contact resistance of NMOS core devices.
In order to improve the carrier mobility of semiconductor devices, in the present embodiment, shape in first periphery source-drain area 122 At there is the first edge stress layer, the material of the first edge stress layer is SiGe or SiGeB.The first core source-drain area The first core stressor layers are formed in 121, the material of the first core stressor layers is SiGe or SiGeB.Second periphery The second periphery stressor layers are formed in source-drain area 124, the material of second periphery stressor layers is SiC or SiCP.Described second The second core stressor layers are formed in core source-drain area 123, the material of the second core stressor layers is SiC or SiCP.
Further embodiment of this invention also provides a kind of forming method of semiconductor devices, unlike previous embodiment, The semiconductor devices that the present embodiment is formed is NMOS device or PMOS device.Specifically, the method for forming the semiconductor devices Include:
The substrate including core space and peripheral region is provided, the core space substrate surface is formed with first grid structure, institute It states peripheral region substrate surface and is formed with second grid structure, be formed with core in the core space substrate of first grid structure two sides Heart source-drain area is formed with periphery source-drain area in the peripheral region substrate of second grid structure two sides, wherein the core source and drain Area is identical with the Doped ions type of periphery source-drain area；
First ion implantation technology is carried out to the peripheral region substrate of second grid structure two sides, in the periphery source and drain Gradual interface, the Doped ions class of the injection ionic type and periphery source-drain area of first ion implantation technology are formed below area Type is identical；
Second ion implantation technology is carried out to the periphery source-drain area and core source-drain area, on periphery source-drain area surface Contact resistance area, the injection ionic type and core source-drain area of second ion implantation technology are formed with core source-drain area surface Doped ions type it is identical.
Semiconductor devices will be described in detail below.
The core source-drain area is identical with the Doped ions concentration of periphery source-drain area.The core space is core device to be formed The region of part, the peripheral region are the region of input/output device to be formed, wherein the operating voltage of input/output device is big In the operating voltage of core devices.
In one embodiment, when the semiconductor devices of formation is PMOS device, the gradual interface and periphery source-drain area Doped ions be P-type ion.In another embodiment, when the semiconductor devices of formation is NMOS device, the gradual interface Doped ions with periphery source-drain area are N-type ion.
The Doped ions concentration in the gradual interface is less than the Doped ions concentration of periphery source-drain area, therefore can be on periphery Graded transition junction is formed between source-drain area and substrate, to reduce the junction leakage of input/output device.And below core source-drain area not Gradual interface is formed, to prevent the gradual interface being located at below core source-drain area from the short channel of input/output device being caused to imitate Answer problem serious, therefore the present embodiment can balance the electric property of input/output device and core devices, both made input/ The junction leakage of output device reduces, additionally it is possible to improve the short channel effect problem of core devices.
In order to improve the carrier mobility of semiconductor devices, edge stress layer, institute are formed in the periphery source-drain area It states and is formed with core stressor layers in core source-drain area.In one embodiment, when the semiconductor devices of formation is PMOS device, institute The material for stating edge stress layer is SiGe or SiGeB, and the material of the core stressor layers is SiGe or SiGeB.In another implementation In example, when the semiconductor devices of formation is NMOS device, the material of the edge stress layer is SiC or SiCP, and the core is answered The material of power layer is SiC or SiCP.
The Doped ions concentration in the contact resistance area is greater than the Doped ions concentration of periphery source-drain area, to reduce defeated Enter/the contact resistance of output device.The Doped ions that the Doped ions concentration in the contact resistance area is greater than core source-drain area are dense Degree, to reduce the contact resistance of core devices.
Correspondingly, the present embodiment also provides a kind of semiconductor devices, comprising:
Substrate including core space and peripheral region, the core space substrate surface are formed with first grid structure, the week Border area substrate surface is formed with second grid structure, is formed with core source in the core space substrate of first grid structure two sides Drain region is formed with periphery source-drain area in the peripheral region substrate of second grid structure two sides, wherein the core source-drain area and The Doped ions type of periphery source-drain area is identical；
Gradual interface below the periphery source-drain area, the Doped ions type and periphery source and drain in the gradual interface The Doped ions type in area is identical；
Positioned at the contact resistance area on periphery source-drain area surface and core source-drain area surface, the contact resistance area is mixed Heteroion type is identical as the Doped ions type of core source-drain area.
The Doped ions concentration of the periphery source-drain area and the Doped ions concentration of core source-drain area are identical.The graded transition junction The Doped ions concentration in area is less than the Doped ions concentration of periphery source-drain area；The Doped ions concentration in the contact resistance area is greater than The Doped ions concentration of periphery source-drain area；The Doped ions concentration in the contact resistance area be also greater than the doping of core source-drain area from Sub- concentration.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (20)

1. a kind of forming method of semiconductor devices characterized by comprising
The substrate including core space and peripheral region is provided, the core space includes NMOS core space and PMOS core space, the week Border area includes the peripheral region NMOS and the peripheral region PMOS, wherein and the peripheral region PMOS substrate surface is formed with first grid structure, The PMOS core space substrate surface is formed with second grid structure, and the peripheral region NMOS substrate surface is formed with third grid Structure, the NMOS core space substrate surface are formed with the 4th gate structure, the periphery PMOS of first grid structure two sides It is formed with the first periphery source-drain area in area's substrate, is formed with first in the PMOS core space substrate of second grid structure two sides Core source-drain area, is formed with the second periphery source-drain area in the peripheral region the NMOS substrate of third gate structure two sides, and described The second core source-drain area is formed in the NMOS core space substrate of four gate structure two sides；
First ion implantation technology is carried out to the peripheral region the PMOS substrate of first grid structure two sides, on first periphery The first gradual interface is formed below source-drain area, the injection ion of first ion implantation technology is P-type ion；
Second ion implantation technology is carried out to first periphery source-drain area and the first core source-drain area, in first peripheral source Drain region surface and the first core source-drain area surface form the first contact resistance area, the injection ion of second ion implantation technology For P-type ion；
Third ion implantation technology is carried out to the peripheral region the NMOS substrate of third gate structure two sides, on second periphery The second gradual interface is formed below source-drain area, the injection ion of the third ion implantation technology is N-type ion；
4th ion implantation technology is carried out to second periphery source-drain area and the second core source-drain area, in second peripheral source Drain region surface and the second core source-drain area surface form the second contact resistance area, the injection ion of the 4th ion implantation technology For N-type ion.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the doping in the first gradual interface Doped ions concentration of the ion concentration less than the first periphery source-drain area；The Doped ions concentration in first contact resistance area is greater than The Doped ions concentration of first periphery source-drain area；The Doped ions concentration in the second gradual interface is less than the second peripheral source The Doped ions concentration in drain region；The Doped ions concentration in second contact resistance area be greater than the second periphery source-drain area doping from Sub- concentration.
3. the forming method of semiconductor devices as described in claim 1, which is characterized in that first ion implantation technology Technological parameter includes: that injection ion includes B, and Implantation Energy is 5KeV to 15KeV, and injection ion dose is 1E13atom/cm2Extremely 1E14atom/cm2, tilted ion implantation angle is 0 degree to 15 degree.
4. the forming method of semiconductor devices as described in claim 1, which is characterized in that second ion implantation technology Technological parameter includes: that injection ion includes BF2, Implantation Energy is 2KeV to 5KeV, and injection ion dose is 1E15atom/cm2Extremely 1E16atom/cm2, tilted ion implantation angle is 0 degree to 5 degree.
5. the forming method of semiconductor devices as described in claim 1, which is characterized in that the third ion implantation technology Technological parameter includes: that injection ion includes P, and Implantation Energy is 100eV to 5KeV, and injection ion dose is 1E15atom/cm2Extremely 5E15atom/cm2, tilted ion implantation angle is 0 degree to 15 degree.
6. the forming method of semiconductor devices as described in claim 1, which is characterized in that the 4th ion implantation technology Technological parameter includes: that injection ion includes P, and Implantation Energy is 100eV to 5KeV, and injection ion dose is 1E15atom/cm2Extremely 5E15atom/cm2, tilted ion implantation angle is 0 degree to 15 degree.
7. the forming method of semiconductor devices as described in claim 1, which is characterized in that further comprise the steps of: to described first Gradual interface, the first contact resistance area, the second gradual interface and the second contact resistance area are made annealing treatment.
8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that the technological parameter of the annealing It include: using spike annealing process, annealing temperature is 950 degrees Celsius to 1000 degrees Celsius.
9. the forming method of semiconductor devices as described in claim 1, which is characterized in that shape in the source-drain area of first periphery At there is the first edge stress layer；The first core stressor layers are formed in the first core source-drain area；Second periphery source and drain The second periphery stressor layers are formed in area；The second core stressor layers are formed in the second core source-drain area.
10. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that the first edge stress layer Material is SiGe or SiGeB；The material of the first core stressor layers is SiGe or SiGeB；Second periphery stressor layers Material is SiC or SiCP；The material of the second core stressor layers is SiC or SiCP.
11. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that form first periphery source and drain The processing step of area and the first core source-drain area includes: the base for etching the peripheral region the PMOS segment thickness of first grid structure two sides Bottom etches the substrate of the PMOS core region thickness of second grid structure two sides, the base in first grid structure two sides Opening is formed in bottom and in the substrate of second grid structure two sides；It is formed and fills opening for full first grid structure two sides First edge stress layer of mouth is formed simultaneously the first core stressor layers for filling the opening of full second grid structure two sides.
12. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that answered forming first periphery Auto-dope in situ is carried out during power layer and forms the first periphery source-drain area, during forming the first core stressor layers It carries out auto-dope in situ and forms the first core source-drain area；Alternatively, forming the first edge stress layer and the first core stress After layer, ion implanting is carried out to the first edge stress layer and the first core stressor layers, forms first periphery source and drain Area and the first core source-drain area.
13. the forming method of semiconductor devices as described in claim 1, which is characterized in that the substrate include substrate and Positioned at several discrete fins of substrate surface；The first grid structure covers PMOS weeks across the peripheral region PMOS fin Border area fin atop part and sidewall surfaces；The second grid structure covers PMOS core across PMOS core space fin Area's fin atop part and sidewall surfaces；The third gate structure covers the peripheral region NMOS across the peripheral region NMOS fin Part fin top and sidewall surfaces；4th gate structure covers NMOS core space portion across NMOS core space fin Divide fin top and sidewall surfaces.
14. a kind of forming method of semiconductor devices characterized by comprising
The substrate including core space and peripheral region is provided, the core space substrate surface is formed with first grid structure, the week Border area substrate surface is formed with second grid structure, is formed with core source in the core space substrate of first grid structure two sides Drain region is formed with periphery source-drain area in the peripheral region substrate of second grid structure two sides, wherein the core source-drain area and The Doped ions type of periphery source-drain area is identical；
First ion implantation technology is carried out to the peripheral region substrate of second grid structure two sides, under the periphery source-drain area It is rectangular at gradual interface, the Doped ions type phase of the injection ionic type and periphery source-drain area of first ion implantation technology Together；
Second ion implantation technology is carried out to the periphery source-drain area and core source-drain area, in periphery source-drain area surface and core Heart source-drain area surface forms contact resistance area, the injection ionic type of second ion implantation technology and mixing for core source-drain area Heteroion type is identical.
15. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that the doping in the gradual interface from Sub- concentration is less than the Doped ions concentration of the periphery source-drain area；The Doped ions concentration in the contact resistance area is greater than the week The Doped ions concentration of side source-drain area and the core source-drain area.
16. the forming method of semiconductor devices as claimed in claim 14, which is characterized in that formed in the periphery source-drain area There is edge stress layer；Core stressor layers are formed in the core source-drain area.
17. a kind of using the semiconductor devices formed such as the described in any item methods of claim 1 to 13, which is characterized in that packet It includes:
Substrate including core space and peripheral region, the core space include NMOS core space and PMOS core space, the peripheral region Including the peripheral region NMOS and the peripheral region PMOS, wherein the peripheral region PMOS substrate surface is formed with first grid structure, described PMOS core space substrate surface is formed with second grid structure, and the peripheral region NMOS substrate surface is formed with third grid knot Structure, the NMOS core space substrate surface are formed with the 4th gate structure, the peripheral region PMOS of first grid structure two sides It is formed with the first periphery source-drain area in substrate, is formed with the first core in the PMOS core space substrate of second grid structure two sides Heart source-drain area, is formed with the second periphery source-drain area in the peripheral region the NMOS substrate of third gate structure two sides, and the described 4th The second core source-drain area is formed in the NMOS core space substrate of gate structure two sides；
The first gradual interface below the source-drain area of first periphery, the Doped ions in the first gradual interface are p-type Ion；
It is connect positioned at the first contact resistance area on the first periphery source-drain area surface and the first core source-drain area surface, described first The Doped ions for touching resistance area are P-type ion；
The second gradual interface below the source-drain area of second periphery, the Doped ions in the second gradual interface are N-type Ion；
It is connect positioned at the second contact resistance area on the second periphery source-drain area surface and the second core source-drain area surface, described second The Doped ions for touching resistance area are N-type ion.
18. semiconductor devices as claimed in claim 17, which is characterized in that the Doped ions concentration in the first gradual interface Less than the Doped ions concentration of the first periphery source-drain area；The Doped ions concentration in first contact resistance area is greater than described first The Doped ions concentration of periphery source-drain area；Doped ions concentration the mixing less than the second periphery source-drain area in the second gradual interface Heteroion concentration；The Doped ions concentration in second contact resistance area is greater than the Doped ions concentration of the second periphery source-drain area.
19. semiconductor devices as claimed in claim 17, which is characterized in that be formed with first in the source-drain area of first periphery Edge stress layer；The first core stressor layers are formed in the first core source-drain area；It is formed in the source-drain area of second periphery There are the second periphery stressor layers；The second core stressor layers are formed in the second core source-drain area.
20. a kind of semiconductor devices formed such as the described in any item methods of claim 14 to 16 characterized by comprising
Substrate including core space and peripheral region, the core space substrate surface are formed with first grid structure, the peripheral region Substrate surface is formed with second grid structure, is formed with core source and drain in the core space substrate of first grid structure two sides Area is formed with periphery source-drain area in the peripheral region substrate of second grid structure two sides, wherein the core source-drain area and week The Doped ions type of side source-drain area is identical；
Gradual interface below the periphery source-drain area, Doped ions type and the periphery source-drain area in the gradual interface Doped ions type is identical；
Positioned at the contact resistance area on periphery source-drain area surface and core source-drain area surface, the doping in the contact resistance area from Subtype is identical as the Doped ions type of core source-drain area.
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CN103943504A (en) * 2013-01-22 2014-07-23 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof
CN104425520A (en) * 2013-08-27 2015-03-18 中芯国际集成电路制造(上海)有限公司 Semiconductor device and formation method

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CN102437028A (en) * 2011-11-30 2012-05-02 上海华力微电子有限公司 PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source/drain region ion implantation method and corresponding device manufacturing method
CN103943504A (en) * 2013-01-22 2014-07-23 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof
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