WO2022028365A1 - Trench-type schottky diode terminal structure and manufacturing method therefor - Google Patents

Trench-type schottky diode terminal structure and manufacturing method therefor Download PDF

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Publication number
WO2022028365A1
WO2022028365A1 PCT/CN2021/110060 CN2021110060W WO2022028365A1 WO 2022028365 A1 WO2022028365 A1 WO 2022028365A1 CN 2021110060 W CN2021110060 W CN 2021110060W WO 2022028365 A1 WO2022028365 A1 WO 2022028365A1
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region
trench
termination
conductivity type
trenches
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PCT/CN2021/110060
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French (fr)
Chinese (zh)
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罗厚彩
张小辛
粟笛
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华润微电子（重庆）有限公司
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]

Definitions

  • the invention belongs to the field of semiconductor integrated circuits, and relates to a trench Schottky diode terminal structure and a manufacturing method thereof.
  • Schottky diode devices are widely used in switching power supplies, frequency converters and power conversion systems due to their low forward voltage drop and very short reverse recovery time.
  • the structure of Schottky devices has changed from the traditional planar type to the trench type.
  • the maximum electric field strength area is mainly concentrated at the bottom of the trench, which weakens the electric field of the Schottky part.
  • the trench type The device greatly reduces the reverse leakage current of the device.
  • the curvature effect of the terminal region makes the electric field in this region much stronger than the electric field in the cell region, resulting in the loss of the trench Schottky diode device. It is difficult to raise the withstand voltage to a higher level.
  • the key problem in realizing high-voltage trench Schottky devices is the design of the termination region structure.
  • the purpose of the present invention is to provide a trench Schottky diode terminal structure and a manufacturing method thereof, which are used to solve the withstand voltage of trench Schottky diode devices in the prior art. level to be improved.
  • the present invention provides a trench Schottky diode termination structure, including:
  • a first conductive type epitaxial layer located on the first conductive type substrate, and divided into a cell area and a terminal area;
  • transition region trench structure located in the first conductivity type epitaxial layer and at the junction of the cell region and the termination region;
  • a plurality of second conductivity type field limiting ring structures located in the first conductivity type epitaxial layer and located in the termination region, a plurality of the second conductivity type field limiting ring structures and a plurality of the termination region trenches structures are alternately arranged in the terminal area;
  • an insulating medium layer located on the first conductivity type epitaxial layer
  • a front Schottky anode located on the insulating dielectric layer, and filled into the opening to be electrically connected to the cell region trench structure, the transition region trench structure and at least one of the termination region trench structures ;
  • a back cathode located under the first conductivity type substrate.
  • the bottom surface of the second conductivity type field limiting ring structure is higher than the bottom surface of the terminal area trench structure; a plurality of the second conductivity type field limiting ring structures and a plurality of the terminal area trenches are formed. At least one end of the first and last ends of the alternately arranged structure composed of the structure is the second conductive type field confinement ring structure.
  • the cell region trench structure, the terminal region trench structure and the transition region trench structure are all filled with conductive materials, and the cell region trench structure, the termination region trench structure A gate dielectric layer is arranged between the inner wall of the trench of the transition region trench structure and the conductive material.
  • the width of the trench structure in the termination region is greater than or equal to the width of the trench structure in the cell region.
  • the spacing between the adjacent trench structures in the termination region is less than or equal to the spacing between the adjacent trench structures in the cell region.
  • the projection of the front Schottky anode on the horizontal plane overlaps with the projections of all the trench structures in the termination region on the horizontal plane.
  • the present invention also provides a method for fabricating a trench-type Schottky diode terminal structure, comprising the following steps:
  • the cell region trenches, the transition region trenches and the termination region The bottom surfaces of the region trenches are all lower than the bottom surface of the second conductivity type implantation region, the transition region trenches are located between the cell region trenches and the termination region trenches, the transition region trenches and The termination region trenches all penetrate the second conductivity type implantation region up and down, and one end of the second conductivity type implantation region is located within the opening range of the transition region trench, so that only one transition region trench is formed.
  • the second conductive type implantation region is formed on the side, and the second conductive type implantation region is formed between adjacent trenches of the termination region;
  • An opening is formed in the insulating dielectric layer, and the opening penetrates the insulating dielectric layer up and down to expose the conductive portion of the cell region trench structure, the conductive portion of the transition region trench structure and at least one of the a conductive portion of the trench structure in the termination region;
  • a front-side Schottky anode is formed on the insulating dielectric layer, and the front-side Schottky anode is filled into the opening to connect with the cell region trench structure, the transition region trench structure and at least one of the terminations
  • the area trench structure is electrically connected;
  • a backside cathode is formed under the first conductivity type substrate.
  • the bottom surface of the second conductivity type field limiting ring structure is higher than the bottom surface of the terminal area trench structure; a plurality of the second conductivity type field limiting ring structures and a plurality of the terminal area trenches are formed. At least one end of the first and last ends of the alternately arranged structure composed of the structure is the second conductive type field confinement ring structure.
  • the width of the trench structure in the terminal area is greater than or equal to the width of the trench structure in the cell area; the spacing between the trench structures in the adjacent terminal area is less than or equal to the trench structure in the adjacent cell area Spacing of the structure.
  • the projection of the front Schottky anode on the horizontal plane overlaps with the projections of all the trench structures in the termination region on the horizontal plane.
  • a P-type implantation region is introduced at the termination position, and the P-type implantation region is blocked by a trench array to form a plurality of field limiting ring structures.
  • the position opens part of the trench to make contact with the metal electrode, forming a combination of the polar field plate and the floating field plate, which can alleviate the electric field change gradient of the trench Schottky device in the terminal region, thereby reducing the reaction of the device.
  • Leakage current increases the reverse breakdown voltage of the device.
  • the trench Schottky diode termination structure of the present invention can use a higher epitaxial layer concentration to achieve the same withstand voltage capability as the conventional structure, which is beneficial to reduce the on-resistance and forward voltage Vf of the device.
  • FIG. 1 is a schematic diagram of a trench Schottky diode termination structure of the present invention.
  • FIG. 2 is a schematic diagram showing the reverse breakdown voltage of the trench Schottky diode termination structure of the present invention and the reverse breakdown voltage characteristic curve of a conventional trench Schottky diode device.
  • FIG. 3 is a schematic diagram of forming a first conductivity type epitaxial layer on the first conductivity type substrate, and forming a second conductivity type implantation region in the first conductivity type epitaxial layer.
  • FIG. 4 is a schematic diagram of forming a plurality of cell region trenches, a plurality of termination region trenches and a transition region trench on the front surface of the first conductivity type epitaxial layer.
  • FIG. 5 is a schematic diagram showing a plurality of second-conductivity-type field-confining ring structures separated by trenches of the termination region by pushing the junction of the second-conductivity-type implant region.
  • FIG. 6 is a schematic diagram illustrating the formation of a gate dielectric layer on the inner sidewalls and inner bottoms of the cell region trenches, the transition region trenches and the termination region trenches.
  • FIG. 7 is a schematic diagram showing the formation of conductive material in the cell region trenches, the transition region trenches and the termination region trenches.
  • FIG. 8 is a schematic diagram illustrating that the excess dielectric layer and polysilicon on the upper surface of the first conductivity type epitaxial layer are removed by an etching process to expose the silicon surface of the first conductivity type epitaxial layer.
  • FIG. 9 is a schematic diagram of forming an insulating dielectric layer on the first conductive type epitaxial layer and forming openings in the insulating dielectric layer.
  • FIG. 10 shows a schematic diagram of forming a front-side Schottky anode on the insulating dielectric layer.
  • FIG. 11 shows a schematic diagram of forming a backside cathode under the first conductivity type substrate.
  • FIG. 1 is a schematic diagram of the trenched Schottky diode termination structure, including a first conductivity type substrate 1 , a first conductivity type Epitaxial layer 2 , multiple cell region trench structures 3 , multiple termination region trench structures 4 , a transition region trench structure 5 , multiple second conductivity type field confinement ring structures 6 , insulating dielectric layer 7 , opening 8 , front Schottky anode 9 and back cathode 10, wherein, the first conductivity type epitaxial layer 2 is located on the first conductivity type substrate 1, and is divided into a cell area I and a terminal area II; the The cell region trench structure 3 is located in the first conductive type epitaxial layer 2 and is located in the cell region; the terminal region trench structure 4 is located in the first conductive type epitaxial layer 2 and located in the cell region.
  • the transition area trench structure 5 is located in the first conductivity type epitaxial layer 2 and at the junction of the cell area and the terminal area;
  • the second conductivity type field confinement ring structure 6 is located in the first conductive type epitaxial layer 2 and is located in the termination region, and a plurality of the second conductive type field limiting ring structures 6 and a plurality of the termination region trench structures 4 are located in the termination region Alternately arranged;
  • the insulating dielectric layer 7 is located on the first conductive type epitaxial layer 2 ;
  • the opening 8 penetrates the insulating dielectric layer 7 up and down, and exposes the conductive portion, The conductive portion of the transition region trench structure 5 and the conductive portion of at least one of the termination region trench structures 4;
  • the front Schottky anode 9 is located on the insulating dielectric layer 7 and filled into the opening 8 to be electrically connected to the cell region trench structure 3 , the transition region trench structure 5 and at least one of the termination region trench structures 4 ; the back
  • At least one end of the first and last ends of the alternately arranged structure composed of a plurality of the second conductivity type field limiting ring structures and a plurality of the termination region trench structures is the second conductivity type field limiting ring structure.
  • the alternately arranged structure composed of a plurality of the second conductivity type field limiting ring structures 6 and a plurality of the terminal region trench structures 4 preferably adopts both ends of the second conductivity type field limiting ring
  • the scheme of structure 6 has better performance.
  • the first conductivity type substrate 1 includes an N-type silicon substrate
  • the first conductivity type epitaxial layer 2 includes an N-type silicon epitaxial layer
  • the conductivity type of the second conductivity type field limiting ring structure 6 is The P-type can be obtained by performing P-type ion implantation at a predetermined position of the first conductive type epitaxial layer 2 and pushing the junction.
  • the trench widths of the cell region trench structure 3 , the termination region trench structure 4 and the transition region trench structure 5 are all in the range of 0.1 ⁇ m ⁇ 10 ⁇ m, preferably 1 ⁇ m ⁇ 3 ⁇ m.
  • the trench depths of the cell region trench structure 3 , the termination region trench structure 4 and the transition region trench structure 5 are all in the range of 0.1 ⁇ m ⁇ 10 ⁇ m, preferably 1 ⁇ m ⁇ 4 ⁇ m.
  • the width of the trench structures 4 in the termination region is preferably greater than or equal to the width of the trench structures 3 in the cell region; the spacing between adjacent trench structures 4 in the termination region is preferably smaller than or equal to the same width The spacing between the trench structures 3 adjacent to the cell region.
  • the bottom surface of the second conductivity type field limiting ring structure 6 is higher than the bottom surface of the termination region trench structure 4 .
  • the cell region trench structure 3 , the termination region trench structure 4 and the transition region trench structure 5 are all filled with conductive material 11
  • the cell region trench structure 3 the A gate dielectric layer 12 is provided between the inner walls of the trenches of the trench structure 4 in the termination region and the trench structure 5 in the transition region and the conductive material 11 .
  • the gate dielectric layer 12 can be an oxide layer with a thickness ranging from 0.01 ⁇ m to 5 ⁇ m, preferably 0.2 ⁇ m to 1 ⁇ m
  • the conductive material 11 can be doped polysilicon with a doping concentration higher than that of the first conductivity type Doping concentration of epitaxial layer 2 .
  • the thickness of the insulating dielectric layer 7 ranges from 0.5 ⁇ m to 5 ⁇ m.
  • the material of the front Schottky anode 9 includes any one of Ti, Pt, Ni, Cr, W, Mo and Co.
  • the projection of the front Schottky anode 9 on the horizontal plane overlaps with the projection of all the trench structures 4 in the termination region on the horizontal plane, that is, the front Schottky anode 9 does not completely cover the insulating medium.
  • FIG. 2 shows the reverse breakdown voltage of the trench Schottky diode termination structure of the present embodiment (shown as “the present invention” in the figure) and the conventional trench Schottky diode device (shown in the figure).
  • FIG. 2 shows the reverse breakdown voltage of the trench Schottky diode termination structure of the present embodiment (shown as “the present invention” in the figure) and the conventional trench Schottky diode device (shown in the figure).
  • FIG. 2 shows the reverse breakdown voltage of the trench Schottky diode termination structure of the present embodiment (shown as “the present invention” in the figure) and the conventional trench Schottky diode device (shown in the figure).
  • the second conductivity type field confinement ring structure 6 and a plurality of terminal area trench structures 4 are alternately arranged in the terminal area, and some of the terminal area trench structures 4 are in contact with the front Schottky anode 9 to form a polar field plate and a floating
  • the combination of the empty field plates can alleviate the electric field variation gradient of the trench Schottky device in the terminal region, thereby reducing the reverse leakage current of the device and increasing the reverse breakdown voltage of the device. Therefore, the trenched Schottky diode termination structure of this embodiment can use a higher epitaxial layer concentration to achieve the same withstand voltage capability as the conventional structure, and reduce the on-resistance and forward voltage Vf of the device.
  • This embodiment provides a method for fabricating a trench Schottky diode terminal structure, including the following steps:
  • a first conductivity type substrate 1 is provided, a first conductivity type epitaxial layer 2 is formed on the first conductivity type substrate 1, and a second conductivity type implantation region 13 is formed on the first conductivity type type epitaxial layer 2.
  • an N-type silicon substrate is provided, an N-type silicon epitaxial layer is epitaxially grown on the surface of the N-type silicon substrate, and an oxide barrier layer 14 is deposited on the surface of the N-type silicon epitaxial layer by chemical vapor deposition, Then photolithography, development, and etching of an implant window 15 in the oxide barrier layer 14 are performed. After the photoresist is removed, P-type ion implantation is performed, and the implantation dose is 1E12-1E16/CM 2 to form a P-type implantation region.
  • a plurality of cell region trenches 16 , a plurality of terminal region trenches 17 and a transition region trench 18 are formed on the front surface of the first conductivity type epitaxial layer 2 , the cell region trenches 16 , the bottom surface of the transition region trench 18 and the termination region trench 17 are lower than the bottom surface of the second conductivity type implantation region 13, that is, the cell region trench 16 and the transition region trench
  • the trench depths of the trenches 18 and the termination region trenches 17 are both larger than the implantation depths of the second conductivity type implantation regions 13 .
  • the transition region trenches 18 are located between the cell region trenches 16 and the termination region trenches 17 , and the transition region trenches 18 and the termination region trenches 17 both penetrate the second conductive region up and down.
  • type implanted region 13 and extends into the first conductive type epitaxial layer 2 below the second conductive type implanted region 13 , and one end of the second conductive type implanted region 13 is located in the transition region trench 18 Within the opening range of the transition region trench 18, only one side of the transition region trench 18 (on one side of the termination region) is formed with the second conductivity type implantation region, and the second conductive type implantation region is formed between adjacent trenches in the termination region.
  • the second conductivity type implantation region is formed between the cell region trenches 16 and the termination region trenches 17 , and the transition region trenches 18 and the termination region trenches 17 both penetrate the second conductive region up and down.
  • type implanted region 13 and extends into the first conductive type epitaxial layer 2 below the second
  • the oxide barrier layer 14 is first removed, and then an oxide mask layer 19 is grown by a chemical vapor deposition process with a thickness of 0.1 ⁇ m-2 ⁇ m, and several oxide masks are etched in the oxide mask layer 19 There are etching windows 20, and then the trench morphology is etched in the first conductivity type epitaxial layer 2 by etching, the trench width is 0.1 ⁇ m ⁇ 10 ⁇ m, preferably 1 ⁇ m ⁇ 3 ⁇ m, and the trench depth is 0.1 ⁇ m ⁇ 10 ⁇ m , preferably 1 ⁇ m to 4 ⁇ m.
  • the width of the trench structures 4 in the termination region is preferably greater than or equal to the width of the trench structures 3 in the cell region; the spacing between adjacent trench structures 4 in the termination region is preferably smaller than or equal to the same width The spacing between the trench structures 3 adjacent to the cell region.
  • the trench region needs to cover the boundary position on the left side of the second conductivity type implantation region 13 , and the boundary position on the right side of the second conductivity type injection region 13 may be hollowed out by the trench, or may be left with a certain size Not hollowed out by trenches.
  • a plurality of the second conductivity type field confinement ring structures and a plurality of the termination region trench structures are subsequently formed.
  • the end close to the cell region is the second conductivity type field confinement ring structure
  • the end far from the cell region is the termination region trench structure.
  • the second conductivity type implanted region 13 is pushed out to obtain a plurality of second conductivity type field confinement ring structures 6 separated by the trenches 17 in the termination region.
  • the second conductivity type implanted region 13 is pushed through a high temperature annealing process, and the push junction time and temperature are controlled, so that the second conductivity type implantation region 13 and the first conductivity type epitaxial layer 2 are formed.
  • the depth of the PN junction is less than the depth of the trench, that is, the bottom surface of the second conductive type field limiting ring structure 6 is higher than the bottom surface of the termination region trench structure 4 .
  • a gate dielectric layer 12 is formed on the inner walls of the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 , and the inner walls include inner sidewalls and inner bottom surfaces.
  • an oxide layer is grown on the surfaces of the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 by a wet oxidation process, and the thickness of the oxide layer may be 0.01 ⁇ m ⁇ 5 ⁇ m, preferably 0.2 ⁇ m. ⁇ m ⁇ 1 ⁇ m.
  • conductive material 11 is formed in the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 .
  • the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 are filled with a heavily doped polysilicon material by a CVD process, and a chemical mechanical polishing (CMP) process is used to remove the material. Surface flattening.
  • CMP chemical mechanical polishing
  • the excess dielectric layer and polysilicon on the upper surface of the first conductivity type epitaxial layer 2 are removed by an etching process, and the silicon surface of the first conductivity type epitaxial layer 2 is exposed.
  • the gate dielectric layer 12 and the conductive material 11 in the cell region trench 16 constitute the cell region trench structure 3
  • the gate dielectric layer 12 and the conductive material 11 in the transition region trench 18 constitute the transition region trench
  • the gate dielectric layer 12 and the conductive material 11 in the termination region trench 17 constitute the termination region trench structure 4 .
  • an insulating dielectric layer 7 is formed on the first conductive type epitaxial layer 2 , and an opening 8 is formed in the insulating dielectric layer 7 , and the opening 8 penetrates the insulating dielectric layer 7 up and down to expose The conductive portion of the cell region trench structure 3 , the conductive portion of the transition region trench structure 5 and the conductive portion of at least one of the termination region trench structures 4 are extracted.
  • the insulating dielectric layer 7 is deposited on the structure shown in FIG. 8 by a deposition process, with a thickness of 0.5 ⁇ m ⁇ 5 ⁇ m, and then the surface of the insulating dielectric layer 7 is subjected to glue coating, exposure, development, and dry etching. The process removes part of the insulating dielectric layer 7 in the cell region and the terminal region to obtain the opening 8, and finally removes the photoresist.
  • a front-side Schottky anode 9 is formed on the insulating dielectric layer 7 , and the front-side Schottky anode 9 is filled into the opening 8 to connect with the cell region trench structure 3 and the transition region.
  • the trench structure 5 and at least one of the trench structures 4 in the termination region are electrically connected.
  • a Schottky metal layer is grown on the first conductivity type epitaxial layer 2 , the surface of the trench structure and the surface of the insulating dielectric layer 7 , and the Schottky metal material includes but is not limited to Ti, Pt, Ni, Cr, W, Mo or Co, annealed to form a Schottky junction and grow a thick metal layer on its surface as the front Schottky anode 9 .
  • the projection of the front Schottky anode 9 on the horizontal plane overlaps with the projections of all the trench structures 4 in the termination region on the horizontal plane.
  • a backside cathode 10 is formed under the first conductive type substrate 1 .
  • the first conductive type substrate 1 is thinned, and a cathode metal is formed on the back surface of the first conductive type substrate 1 to serve as the back surface cathode 10 .
  • a trenched Schottky diode termination structure is fabricated.
  • the method of this embodiment introduces a P-type implantation region at the termination position, and uses a trench array to block the P-type implantation region to form a plurality of field limiting ring structures.
  • the position opens part of the trench to make contact with the metal electrode, forming a combination of polar field plate and floating field plate, which can alleviate the gradient of the electric field change in the terminal area of the trench Schottky device, which is conducive to reducing the reaction of the device. leakage current and increase the reverse breakdown voltage of the device.
  • the trenched Schottky diode termination structure and its fabrication method of the present invention introduce a P-type implantation region at the termination position, and use the trench array to block the P-type implantation region to form a plurality of field confinement ring structures.
  • the terminal position opens part of the trench to make contact with the metal electrode, forming a combination of polar field plate and floating field plate, which can alleviate the electric field change gradient of the trench Schottky device in the terminal region, thereby reducing the device's performance.
  • the reverse leakage current increases the reverse breakdown voltage of the device.
  • the trench Schottky diode termination structure of the present invention can use a higher epitaxial layer concentration to achieve the same withstand voltage capability as the conventional structure, which is beneficial to reduce the on-resistance and forward voltage Vf of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

Provided are a trench-type Schottky diode terminal structure and a manufacturing method therefor. The terminal structure comprises a first-conductive-type substrate, a first-conductive-type epitaxial layer, a plurality of cellular area trench structures, a plurality of terminal area trench structures, a transition area trench structure, a plurality of second-conductive-type field limiting ring structures, an insulating dielectric layer, an opening, a front Schottky anode and a back cathode. In the present invention, a P-type injection area is introduced into a terminal area, a trench array is used to separate the P-type injection area, so as to form a plurality of field limiting ring structures, and some terminal area trench structures are in contact with a metal electrode, so as to form a combination of a polar field plate and a floating field plate, such that an electric field change gradient of a trench-type Schottky device in the terminal area can be alleviated, thereby reducing a reverse leakage current of the device and improving a reverse breakdown voltage of the device. In addition, the terminal structure of the present invention can use a higher epitaxial layer concentration to achieve the same voltage withstand capability as a conventional structure, thereby facilitating the reduction of an on-resistance and a forward voltage of the device.

Description

一种沟槽型肖特基二极管终端结构及其制作方法A trench type Schottky diode terminal structure and fabrication method thereof 技术领域technical field
本发明属于半导体集成电路领域，涉及一种沟槽性肖特基二极管终端结构及其制作方法。The invention belongs to the field of semiconductor integrated circuits, and relates to a trench Schottky diode terminal structure and a manufacturing method thereof.
背景技术Background technique
肖特基二极管器件由于具有较低的正向导通压降以及非常短的反向恢复时间，被大量使用在开关电源、变频器以及电力转换系统中。近年来，随着沟槽技术的发展，肖特基器件结构由传统的平面型向沟槽型转变。沟槽型肖特基结构的器件在承受反向电压时，最大电场强度区域主要集中在沟槽底部，减弱了肖特基部分的电场，与传统平面型肖特基二极管相比，沟槽型器件大大降低了器件的反向漏电流。然而，沟槽型肖特基器件中由于沟槽结构的存在，终端区域的曲率效应使其在该区域的电场比元胞区的电场强度大得多，导致沟槽型肖特基二极管器件的耐压难以提升到较高的水平。实现高电压沟槽型肖特基器件的关键问题在于终端区结构的设计。Schottky diode devices are widely used in switching power supplies, frequency converters and power conversion systems due to their low forward voltage drop and very short reverse recovery time. In recent years, with the development of trench technology, the structure of Schottky devices has changed from the traditional planar type to the trench type. When the device of the trench Schottky structure is subjected to reverse voltage, the maximum electric field strength area is mainly concentrated at the bottom of the trench, which weakens the electric field of the Schottky part. Compared with the traditional planar Schottky diode, the trench type The device greatly reduces the reverse leakage current of the device. However, due to the existence of the trench structure in the trench Schottky device, the curvature effect of the terminal region makes the electric field in this region much stronger than the electric field in the cell region, resulting in the loss of the trench Schottky diode device. It is difficult to raise the withstand voltage to a higher level. The key problem in realizing high-voltage trench Schottky devices is the design of the termination region structure.
发明内容SUMMARY OF THE INVENTION
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种沟槽性肖特基二极管终端结构及其制作方法，用于解决现有技术中沟槽型肖特基二极管器件的耐压水平有待提高的问题。In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a trench Schottky diode terminal structure and a manufacturing method thereof, which are used to solve the withstand voltage of trench Schottky diode devices in the prior art. level to be improved.
为实现上述目的及其他相关目的，本发明提供一种沟槽型肖特基二极管终端结构，包括：In order to achieve the above purpose and other related purposes, the present invention provides a trench Schottky diode termination structure, including:
第一导电类型衬底；a first conductivity type substrate;
第一导电类型外延层，位于所述第一导电类型衬底上，并划分为元胞区及终端区；a first conductive type epitaxial layer, located on the first conductive type substrate, and divided into a cell area and a terminal area;
多个元胞区沟槽结构，位于所述第一导电类型外延层中，并位于所述元胞区；a plurality of cell region trench structures located in the first conductivity type epitaxial layer and in the cell region;
多个终端区沟槽结构，位于所述第一导电类型外延层中，并位于所述终端区；a plurality of terminal area trench structures located in the first conductive type epitaxial layer and located in the terminal area;
一过渡区沟槽结构，位于所述第一导电类型外延层中，并位于所述元胞区与所述终端区的交界处；a transition region trench structure located in the first conductivity type epitaxial layer and at the junction of the cell region and the termination region;
多个第二导电类型场限环结构，位于所述第一导电类型外延层中，并位于所述终端区，多个所述第二导电类型场限环结构与多个所述终端区沟槽结构在所述终端区中交替排列；a plurality of second conductivity type field limiting ring structures located in the first conductivity type epitaxial layer and located in the termination region, a plurality of the second conductivity type field limiting ring structures and a plurality of the termination region trenches structures are alternately arranged in the terminal area;
绝缘介质层，位于所述第一导电类型外延层上；an insulating medium layer, located on the first conductivity type epitaxial layer;
开口，上下贯穿所述绝缘介质层，所述开口暴露出所述元胞区沟槽结构的导电部分、所述过渡区沟槽结构的导电部分及至少一所述终端区沟槽结构的导电部分；an opening, penetrating the insulating medium layer up and down, the opening exposing the conductive portion of the trench structure in the cell region, the conductive portion of the trench structure in the transition region and at least one conductive portion of the trench structure in the termination region ;
正面肖特基阳极，位于所述绝缘介质层上，并填充进所述开口以与所述元胞区沟槽结构、所述过渡区沟槽结构及至少一所述终端区沟槽结构电连接；a front Schottky anode, located on the insulating dielectric layer, and filled into the opening to be electrically connected to the cell region trench structure, the transition region trench structure and at least one of the termination region trench structures ;
背面阴极，位于所述第一导电类型衬底下方。a back cathode, located under the first conductivity type substrate.
可选地，所述第二导电类型场限环结构的底面高于所述终端区沟槽结构的底面；由多个所述第二导电类型场限环结构与多个所述终端区沟槽结构组成的交替排列结构的首尾两端中，至少有一端为所述第二导电类型场限环结构。Optionally, the bottom surface of the second conductivity type field limiting ring structure is higher than the bottom surface of the terminal area trench structure; a plurality of the second conductivity type field limiting ring structures and a plurality of the terminal area trenches are formed. At least one end of the first and last ends of the alternately arranged structure composed of the structure is the second conductive type field confinement ring structure.
可选地，所述元胞区沟槽结构、所述终端区沟槽结构及所述过渡区沟槽结构均填充有导电材料，所述元胞区沟槽结构、所述终端区沟槽结构及所述过渡区沟槽结构的沟槽内壁与所述导电材料间设有栅介质层。Optionally, the cell region trench structure, the terminal region trench structure and the transition region trench structure are all filled with conductive materials, and the cell region trench structure, the termination region trench structure A gate dielectric layer is arranged between the inner wall of the trench of the transition region trench structure and the conductive material.
可选地，所述终端区沟槽结构的宽度大于或等于所述元胞区沟槽结构的宽度。Optionally, the width of the trench structure in the termination region is greater than or equal to the width of the trench structure in the cell region.
可选地，相邻所述终端区沟槽结构的间距小于或等于相邻所述元胞区沟槽结构的间距。Optionally, the spacing between the adjacent trench structures in the termination region is less than or equal to the spacing between the adjacent trench structures in the cell region.
可选地，所述正面肖特基阳极在水平面上的投影与所有所述终端区沟槽结构在水平面上的投影均有重叠部分。Optionally, the projection of the front Schottky anode on the horizontal plane overlaps with the projections of all the trench structures in the termination region on the horizontal plane.
本发明还提供一种沟槽型肖特基二极管终端结构的制作方法，包括以下步骤：The present invention also provides a method for fabricating a trench-type Schottky diode terminal structure, comprising the following steps:
提供第一导电类型衬底，形成第一导电类型外延层于所述第一导电类型衬底上；providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the first conductive type substrate;
形成第二导电类型注入区于所述第一导电类型外延层中；forming a second conductive type implanted region in the first conductive type epitaxial layer;
形成多个元胞区沟槽、多个终端区沟槽及一过渡区沟槽于所述第一导电类型外延层正面，所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽的底面均低于所述第二导电类型注入区的底面，所述过渡区沟槽位于所述元胞区沟槽与所述终端区沟槽之间，所述过渡区沟槽及所述终端区沟槽均上下贯穿所述第二导电类型注入区，且所述第二导电类型注入区的一端位于所述过渡区沟槽的开口范围内，使得所述过渡区沟槽仅一侧形成有所述第二导电类型注入区，相邻所述终端区沟槽之间均形成有所述第二导电类型注入区；forming a plurality of cell region trenches, a plurality of terminal region trenches and a transition region trench on the front surface of the first conductivity type epitaxial layer, the cell region trenches, the transition region trenches and the termination region The bottom surfaces of the region trenches are all lower than the bottom surface of the second conductivity type implantation region, the transition region trenches are located between the cell region trenches and the termination region trenches, the transition region trenches and The termination region trenches all penetrate the second conductivity type implantation region up and down, and one end of the second conductivity type implantation region is located within the opening range of the transition region trench, so that only one transition region trench is formed. The second conductive type implantation region is formed on the side, and the second conductive type implantation region is formed between adjacent trenches of the termination region;
对所述第二导电类型注入区进行推结，得到由所述终端区沟槽间隔的多个第二导电类型场限环结构；performing push junction on the implanted region of the second conductivity type to obtain a plurality of field confinement ring structures of the second conductivity type spaced by the trenches in the termination region;
形成栅介质层于所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽的内壁；forming a gate dielectric layer on the inner walls of the cell region trenches, the transition region trenches and the termination region trenches;
形成导电材料于所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽中；forming conductive material in the cell region trenches, the transition region trenches and the termination region trenches;
形成绝缘介质层于所述第一导电类型外延层上；forming an insulating dielectric layer on the first conductive type epitaxial layer;
形成开口于所述绝缘介质层中，所述开口上下贯穿所述绝缘介质层以暴露出所述元胞区沟槽结构的导电部分、所述过渡区沟槽结构的导电部分及至少一所述终端区沟槽结构的导电部分；An opening is formed in the insulating dielectric layer, and the opening penetrates the insulating dielectric layer up and down to expose the conductive portion of the cell region trench structure, the conductive portion of the transition region trench structure and at least one of the a conductive portion of the trench structure in the termination region;
形成正面肖特基阳极于所述绝缘介质层上，所述正面肖特基阳极填充进所述开口以与所述元胞区沟槽结构、所述过渡区沟槽结构及至少一所述终端区沟槽结构电连接；A front-side Schottky anode is formed on the insulating dielectric layer, and the front-side Schottky anode is filled into the opening to connect with the cell region trench structure, the transition region trench structure and at least one of the terminations The area trench structure is electrically connected;
形成背面阴极于所述第一导电类型衬底下方。A backside cathode is formed under the first conductivity type substrate.
可选地，所述第二导电类型场限环结构的底面高于所述终端区沟槽结构的底面；由多个所述第二导电类型场限环结构与多个所述终端区沟槽结构组成的交替排列结构的首尾两端中，至少有一端为所述第二导电类型场限环结构。Optionally, the bottom surface of the second conductivity type field limiting ring structure is higher than the bottom surface of the terminal area trench structure; a plurality of the second conductivity type field limiting ring structures and a plurality of the terminal area trenches are formed. At least one end of the first and last ends of the alternately arranged structure composed of the structure is the second conductive type field confinement ring structure.
可选地，所述终端区沟槽结构的宽度大于或等于所述元胞区沟槽结构的宽度；相邻所述终端区沟槽结构的间距小于或等于相邻所述元胞区沟槽结构的间距。Optionally, the width of the trench structure in the terminal area is greater than or equal to the width of the trench structure in the cell area; the spacing between the trench structures in the adjacent terminal area is less than or equal to the trench structure in the adjacent cell area Spacing of the structure.
可选地，所述正面肖特基阳极在水平面上的投影与所有所述终端区沟槽结构在水平面上的投影均有重叠部分。Optionally, the projection of the front Schottky anode on the horizontal plane overlaps with the projections of all the trench structures in the termination region on the horizontal plane.
如上所述，本发明的沟槽性肖特基二极管终端结构及其制作方法在终端位置引入P型注入区，利用沟槽阵列将P型注入区阻隔形成多个场限环结构，同时在终端位置将部分沟槽打开以与金属电极产生接触，形成极性场板与浮空场板的搭配组合，可以缓解沟槽型肖特基器件在终端区的电场变化梯度，从而降低了器件的反向漏电流，提高了器件的反向击穿电压。此外，本发明的沟槽型肖特基二极管终端结构可以使用更高的外延层浓度来实现与传统结构相同的耐压能力，有利于降低器件的导通电阻和正向电压Vf。As described above, in the trenched Schottky diode termination structure and its fabrication method of the present invention, a P-type implantation region is introduced at the termination position, and the P-type implantation region is blocked by a trench array to form a plurality of field limiting ring structures. The position opens part of the trench to make contact with the metal electrode, forming a combination of the polar field plate and the floating field plate, which can alleviate the electric field change gradient of the trench Schottky device in the terminal region, thereby reducing the reaction of the device. Leakage current increases the reverse breakdown voltage of the device. In addition, the trench Schottky diode termination structure of the present invention can use a higher epitaxial layer concentration to achieve the same withstand voltage capability as the conventional structure, which is beneficial to reduce the on-resistance and forward voltage Vf of the device.
附图说明Description of drawings
图1显示为本发明的沟槽型肖特基二极管终端结构的示意图。FIG. 1 is a schematic diagram of a trench Schottky diode termination structure of the present invention.
图2显示为本发明的沟槽型肖特基二极管终端结构的反向击穿电压与传统沟槽型肖特基二极管器件的反向击穿电压特性曲线示意图。FIG. 2 is a schematic diagram showing the reverse breakdown voltage of the trench Schottky diode termination structure of the present invention and the reverse breakdown voltage characteristic curve of a conventional trench Schottky diode device.
图3显示为形成第一导电类型外延层于所述第一导电类型衬底上，并形成第二导电类型注入区于所述第一导电类型外延层中的示意图。FIG. 3 is a schematic diagram of forming a first conductivity type epitaxial layer on the first conductivity type substrate, and forming a second conductivity type implantation region in the first conductivity type epitaxial layer.
图4显示为形成多个元胞区沟槽、多个终端区沟槽及一过渡区沟槽于所述第一导电类型外延层正面的示意图。FIG. 4 is a schematic diagram of forming a plurality of cell region trenches, a plurality of termination region trenches and a transition region trench on the front surface of the first conductivity type epitaxial layer.
图5显示为对所述第二导电类型注入区进行推结，得到由所述终端区沟槽间隔的多个第二导电类型场限环结构的示意图。FIG. 5 is a schematic diagram showing a plurality of second-conductivity-type field-confining ring structures separated by trenches of the termination region by pushing the junction of the second-conductivity-type implant region.
图6显示为形成栅介质层于所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽的内 侧壁与内底面的示意图。FIG. 6 is a schematic diagram illustrating the formation of a gate dielectric layer on the inner sidewalls and inner bottoms of the cell region trenches, the transition region trenches and the termination region trenches.
图7显示为形成导电材料于所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽中的示意图。7 is a schematic diagram showing the formation of conductive material in the cell region trenches, the transition region trenches and the termination region trenches.
图8显示为通过蚀刻工艺去除掉所述第一导电类型外延层上表面多余的介质层和多晶硅，露出所述第一导电类型外延层的硅面的示意图。FIG. 8 is a schematic diagram illustrating that the excess dielectric layer and polysilicon on the upper surface of the first conductivity type epitaxial layer are removed by an etching process to expose the silicon surface of the first conductivity type epitaxial layer.
图9显示为形成绝缘介质层于所述第一导电类型外延层上，并形成开口于所述绝缘介质层中的示意图。FIG. 9 is a schematic diagram of forming an insulating dielectric layer on the first conductive type epitaxial layer and forming openings in the insulating dielectric layer.
图10显示为形成正面肖特基阳极于所述绝缘介质层上的示意图。FIG. 10 shows a schematic diagram of forming a front-side Schottky anode on the insulating dielectric layer.
图11显示为形成背面阴极于所述第一导电类型衬底下方的示意图。FIG. 11 shows a schematic diagram of forming a backside cathode under the first conductivity type substrate.
元件标号说明Component label description
1                      第一导电类型衬底1 The first conductivity type substrate
2                      第一导电类型外延层2 The first conductivity type epitaxial layer
3                      元胞区沟槽结构3 Cell area groove structure
4                      终端区沟槽结构4 Termination trench structure
5                      过渡区沟槽结构5 Transition zone trench structure
6                      第二导电类型场限环结构6 Field-limited loop structure of the second conductivity type
7                      绝缘介质层7 Insulation dielectric layer
8                      开口8 openings
9                      正面肖特基阳极9 Front Schottky anode
10                     背面阴极10 Backside cathode
11                     导电材料11 Conductive materials
12                     栅介质层12 Gate dielectric layer
13                     第二导电类型注入区13 Second conductivity type injection region
14                     氧化物阻挡层14 Oxide Barrier
15                     注入窗口15 Injection window
16                     元胞区沟槽16 Cell area groove
17                     终端区沟槽17 Termination trenches
18                     过渡区沟槽18 Transition groove
19                     氧化物掩膜层19 Oxide mask layer
20                     蚀刻窗口20 Etched window
I                      元胞区I Cell area
II                     终端区II Terminal area
具体实施方式detailed description
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1至图11。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。See Figures 1 through 11. It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.
实施例一Example 1
本实施例中提供一种沟槽型肖特基二极管终端结构，请参阅图1，显示为该沟槽型肖特基二极管终端结构的示意图，包括第一导电类型衬底1、第一导电类型外延层2、多个元胞区沟槽结构3、多个终端区沟槽结构4、一过渡区沟槽结构5、多个第二导电类型场限环结构6、绝缘介质层7、开口8、正面肖特基阳极9及背面阴极10，其中，所述第一导电类型外延层2，位于所述第一导电类型衬底1上，并划分为元胞区I及终端区II；所述元胞区沟槽结构3位于所述第一导电类型外延层2中，并位于所述元胞区；所述终端区沟槽结构4位于所述第一导电类型外延层2中，并位于所述终端区；所述过渡区沟槽结构5位于所述第一导电类型外延层2中，并位于所述元胞区与所述终端区的交界处；所述第二导电类型场限环结构6位于所述第一导电类型外延层2中，并位于所述终端区，多个所述第二导电类型场限环结构6与多个所述终端区沟槽结构4在所述终端区中交替排列；所述绝缘介质层7位于所述第一导电类型外延层2上；所述开口8上下贯穿所述绝缘介质层7，并暴露出所述元胞区沟槽结构3的导电部分、所述过渡区沟槽结构5的导电部分及至少一所述终端区沟槽结构4的导电部分；所述正面肖特基阳极9位于所述绝缘介质层7上，并填充进所述开口8以与所述元胞区沟槽结构3、所述过渡区沟槽结构5及至少一所述终端区沟槽结构4电连接；所述背面阴极10位于所述第一导电类型衬底1下方。This embodiment provides a trenched Schottky diode termination structure, please refer to FIG. 1 , which is a schematic diagram of the trenched Schottky diode termination structure, including a first conductivity type substrate 1 , a first conductivity type Epitaxial layer 2 , multiple cell region trench structures 3 , multiple termination region trench structures 4 , a transition region trench structure 5 , multiple second conductivity type field confinement ring structures 6 , insulating dielectric layer 7 , opening 8 , front Schottky anode 9 and back cathode 10, wherein, the first conductivity type epitaxial layer 2 is located on the first conductivity type substrate 1, and is divided into a cell area I and a terminal area II; the The cell region trench structure 3 is located in the first conductive type epitaxial layer 2 and is located in the cell region; the terminal region trench structure 4 is located in the first conductive type epitaxial layer 2 and located in the cell region. the terminal area; the transition area trench structure 5 is located in the first conductivity type epitaxial layer 2 and at the junction of the cell area and the terminal area; the second conductivity type field confinement ring structure 6 is located in the first conductive type epitaxial layer 2 and is located in the termination region, and a plurality of the second conductive type field limiting ring structures 6 and a plurality of the termination region trench structures 4 are located in the termination region Alternately arranged; the insulating dielectric layer 7 is located on the first conductive type epitaxial layer 2 ; the opening 8 penetrates the insulating dielectric layer 7 up and down, and exposes the conductive portion, The conductive portion of the transition region trench structure 5 and the conductive portion of at least one of the termination region trench structures 4; the front Schottky anode 9 is located on the insulating dielectric layer 7 and filled into the opening 8 to be electrically connected to the cell region trench structure 3 , the transition region trench structure 5 and at least one of the termination region trench structures 4 ; the backside cathode 10 is located under the first conductive type substrate 1 .
作为示例，由多个所述第二导电类型场限环结构与多个所述终端区沟槽结构组成的交替排列结构的首尾两端中，至少有一端为所述第二导电类型场限环结构。本实施例中，由 多个所述第二导电类型场限环结构6与多个所述终端区沟槽结构4组成的交替排列结构优选采用两端均为所述第二导电类型场限环结构6的方案，性能更优。As an example, at least one end of the first and last ends of the alternately arranged structure composed of a plurality of the second conductivity type field limiting ring structures and a plurality of the termination region trench structures is the second conductivity type field limiting ring structure. In this embodiment, the alternately arranged structure composed of a plurality of the second conductivity type field limiting ring structures 6 and a plurality of the terminal region trench structures 4 preferably adopts both ends of the second conductivity type field limiting ring The scheme of structure 6 has better performance.
作为示例，所述第一导电类型衬底1包括N型硅衬底，所述第一导电类型外延层2包括N型硅外延层，所述第二导电类型场限环结构6的导电类型为P型，可通过在所述第一导电类型外延层2的预设位置进行P型离子注入并推结得到。As an example, the first conductivity type substrate 1 includes an N-type silicon substrate, the first conductivity type epitaxial layer 2 includes an N-type silicon epitaxial layer, and the conductivity type of the second conductivity type field limiting ring structure 6 is The P-type can be obtained by performing P-type ion implantation at a predetermined position of the first conductive type epitaxial layer 2 and pushing the junction.
作为示例，所述元胞区沟槽结构3、所述终端区沟槽结构4及所述过渡区沟槽结构5的沟槽宽度范围均为0.1μm～10μm，优选为1μm～3μm，所述元胞区沟槽结构3、所述终端区沟槽结构4及所述过渡区沟槽结构5的沟槽深度范围均为0.1μm～10μm，优选为1μm～4μm。本实施例中，所述终端区沟槽结构4的宽度优选为大于或等于所述元胞区沟槽结构3的宽度；相邻所述终端区沟槽结构4的间距优选为小于或等于相邻所述元胞区沟槽结构3的间距。As an example, the trench widths of the cell region trench structure 3 , the termination region trench structure 4 and the transition region trench structure 5 are all in the range of 0.1 μm˜10 μm, preferably 1 μm˜3 μm. The trench depths of the cell region trench structure 3 , the termination region trench structure 4 and the transition region trench structure 5 are all in the range of 0.1 μm˜10 μm, preferably 1 μm˜4 μm. In this embodiment, the width of the trench structures 4 in the termination region is preferably greater than or equal to the width of the trench structures 3 in the cell region; the spacing between adjacent trench structures 4 in the termination region is preferably smaller than or equal to the same width The spacing between the trench structures 3 adjacent to the cell region.
作为示例，所述第二导电类型场限环结构6的底面高于所述终端区沟槽结构4的底面。As an example, the bottom surface of the second conductivity type field limiting ring structure 6 is higher than the bottom surface of the termination region trench structure 4 .
作为示例，所述元胞区沟槽结构3、所述终端区沟槽结构4及所述过渡区沟槽结构5内部均填充有导电材料11，所述元胞区沟槽结构3、所述终端区沟槽结构4及所述过渡区沟槽结构5的沟槽内壁与所述导电材料11间设有栅介质层12。所述栅介质层12可采用氧化层，其厚度范围是0.01μm～5μm，优选为0.2μm～1μm，所述导电材料11可采用掺杂多晶硅，其掺杂浓度高于所述第一导电类型外延层2的掺杂浓度。As an example, the cell region trench structure 3 , the termination region trench structure 4 and the transition region trench structure 5 are all filled with conductive material 11 , the cell region trench structure 3 , the A gate dielectric layer 12 is provided between the inner walls of the trenches of the trench structure 4 in the termination region and the trench structure 5 in the transition region and the conductive material 11 . The gate dielectric layer 12 can be an oxide layer with a thickness ranging from 0.01 μm to 5 μm, preferably 0.2 μm to 1 μm, and the conductive material 11 can be doped polysilicon with a doping concentration higher than that of the first conductivity type Doping concentration of epitaxial layer 2 .
作为示例，所述绝缘介质层7的厚度范围是0.5μm～5μm。As an example, the thickness of the insulating dielectric layer 7 ranges from 0.5 μm to 5 μm.
作为示例，所述正面肖特基阳极9的材料包括Ti、Pt、Ni、Cr、W、Mo及Co中的任意一种。所述正面肖特基阳极9在水平面上的投影与所有所述终端区沟槽结构4在水平面上的投影均有重叠部分，也即所述正面肖特基阳极9未完全覆盖所述绝缘介质层7。As an example, the material of the front Schottky anode 9 includes any one of Ti, Pt, Ni, Cr, W, Mo and Co. The projection of the front Schottky anode 9 on the horizontal plane overlaps with the projection of all the trench structures 4 in the termination region on the horizontal plane, that is, the front Schottky anode 9 does not completely cover the insulating medium. Layer 7.
请参阅图2，显示为本实施例的沟槽型肖特基二极管终端结构(图中示为“本发明”)的反向击穿电压与传统沟槽型肖特基二极管器件(图中示为“传统沟槽SBD”)的反向击穿电压特性曲线示意图，与传统结构的沟槽型肖特基二极管相比较，本实施例的沟槽性肖特基二极管终端结构中，多个述第二导电类型场限环结构6与多个终端区沟槽结构4在终端区中交替排列，并且部分终端区沟槽结构4与正面肖特基阳极9产生接触，形成极性场板与浮空场板的搭配组合，能够缓解沟槽型肖特基器件在终端区的电场变化梯度，从而降低了器件的反向漏电流，提高了器件的反向击穿电压。因此，本实施例的沟槽性肖特基二极管终端结构可以使用更高的外延层浓度来实现与传统结构相同的耐压能力，降低了器件的导通电阻和正向电压Vf。Please refer to FIG. 2 , which shows the reverse breakdown voltage of the trench Schottky diode termination structure of the present embodiment (shown as “the present invention” in the figure) and the conventional trench Schottky diode device (shown in the figure). is a schematic diagram of the reverse breakdown voltage characteristic curve of a "traditional trench SBD"). The second conductivity type field confinement ring structure 6 and a plurality of terminal area trench structures 4 are alternately arranged in the terminal area, and some of the terminal area trench structures 4 are in contact with the front Schottky anode 9 to form a polar field plate and a floating The combination of the empty field plates can alleviate the electric field variation gradient of the trench Schottky device in the terminal region, thereby reducing the reverse leakage current of the device and increasing the reverse breakdown voltage of the device. Therefore, the trenched Schottky diode termination structure of this embodiment can use a higher epitaxial layer concentration to achieve the same withstand voltage capability as the conventional structure, and reduce the on-resistance and forward voltage Vf of the device.
实施例二 Embodiment 2
本实施例中提供一种沟槽型肖特基二极管终端结构的制作方法，包括以下步骤：This embodiment provides a method for fabricating a trench Schottky diode terminal structure, including the following steps:
如图3所示，提供第一导电类型衬底1，形成第一导电类型外延层2于所述第一导电类型衬底1上，并形成第二导电类型注入区13于所述第一导电类型外延层2中。As shown in FIG. 3, a first conductivity type substrate 1 is provided, a first conductivity type epitaxial layer 2 is formed on the first conductivity type substrate 1, and a second conductivity type implantation region 13 is formed on the first conductivity type type epitaxial layer 2.
作为示例，提供N型硅衬底，在所述N型硅衬底表面外延生长N型硅外延层，并通过化学气相沉积于所述N型硅外延层表面沉积一层氧化物阻挡层14，然后光刻，显影，在所述氧化物阻挡层14中蚀刻出一个注入窗口15。去掉光刻胶后，进行P型离子注入，注入剂量在1E12-1E16/CM 2，形成P型注入区。 As an example, an N-type silicon substrate is provided, an N-type silicon epitaxial layer is epitaxially grown on the surface of the N-type silicon substrate, and an oxide barrier layer 14 is deposited on the surface of the N-type silicon epitaxial layer by chemical vapor deposition, Then photolithography, development, and etching of an implant window 15 in the oxide barrier layer 14 are performed. After the photoresist is removed, P-type ion implantation is performed, and the implantation dose is 1E12-1E16/CM 2 to form a P-type implantation region.
如图4所示，形成多个元胞区沟槽16、多个终端区沟槽17及一过渡区沟槽18于所述第一导电类型外延层2正面，所述元胞区沟槽16、所述过渡区沟槽18及所述终端区沟槽17的底面均低于所述第二导电类型注入区13的底面，也即所述元胞区沟槽16、所述过渡区沟槽18及所述终端区沟槽17的沟槽深度均大于所述第二导电类型注入区13的注入深度。所述过渡区沟槽18位于所述元胞区沟槽16与所述终端区沟槽17之间，所述过渡区沟槽18和所述终端区沟槽17均上下贯穿所述第二导电类型注入区13，并延伸至所述第二导电类型注入区13下方的所述第一导电类型外延层2中，且所述第二导电类型注入区13的一端位于所述过渡区沟槽18的开口范围内，使得所述过渡区沟槽18仅一侧(位于终端区的一侧)形成有所述第二导电类型注入区，相邻所述终端区沟槽之间均形成有所述第二导电类型注入区。As shown in FIG. 4 , a plurality of cell region trenches 16 , a plurality of terminal region trenches 17 and a transition region trench 18 are formed on the front surface of the first conductivity type epitaxial layer 2 , the cell region trenches 16 , the bottom surface of the transition region trench 18 and the termination region trench 17 are lower than the bottom surface of the second conductivity type implantation region 13, that is, the cell region trench 16 and the transition region trench The trench depths of the trenches 18 and the termination region trenches 17 are both larger than the implantation depths of the second conductivity type implantation regions 13 . The transition region trenches 18 are located between the cell region trenches 16 and the termination region trenches 17 , and the transition region trenches 18 and the termination region trenches 17 both penetrate the second conductive region up and down. type implanted region 13 and extends into the first conductive type epitaxial layer 2 below the second conductive type implanted region 13 , and one end of the second conductive type implanted region 13 is located in the transition region trench 18 Within the opening range of the transition region trench 18, only one side of the transition region trench 18 (on one side of the termination region) is formed with the second conductivity type implantation region, and the second conductive type implantation region is formed between adjacent trenches in the termination region. The second conductivity type implantation region.
作为示例，首先去除所述氧化物阻挡层14，然后通过化学气相沉积工艺生长一层氧化物掩膜层19，厚度为0.1μm-2μm，并在所述氧化物掩膜层19中蚀刻出若干个蚀刻窗口20，然后通过蚀刻方式在所述第一导电类型外延层2中蚀刻出沟槽形貌，沟槽宽度为0.1μm～10μm，优选为1μm～3μm，沟槽深度为0.1μm～10μm，优选为1μm～4μm。本实施例中，所述终端区沟槽结构4的宽度优选为大于或等于所述元胞区沟槽结构3的宽度；相邻所述终端区沟槽结构4的间距优选为小于或等于相邻所述元胞区沟槽结构3的间距。As an example, the oxide barrier layer 14 is first removed, and then an oxide mask layer 19 is grown by a chemical vapor deposition process with a thickness of 0.1 μm-2 μm, and several oxide masks are etched in the oxide mask layer 19 There are etching windows 20, and then the trench morphology is etched in the first conductivity type epitaxial layer 2 by etching, the trench width is 0.1 μm˜10 μm, preferably 1 μm˜3 μm, and the trench depth is 0.1 μm˜10 μm , preferably 1 μm to 4 μm. In this embodiment, the width of the trench structures 4 in the termination region is preferably greater than or equal to the width of the trench structures 3 in the cell region; the spacing between adjacent trench structures 4 in the termination region is preferably smaller than or equal to the same width The spacing between the trench structures 3 adjacent to the cell region.
作为示例，沟槽区域需覆盖所述第二导电类型注入区13左侧的边界位置，所述第二导电类型注入区13右侧的边界位置可以被沟槽挖空，也可以留有一定尺寸不被沟槽挖空。其中，在所述第二导电类型注入区13右侧的边界位置被沟槽挖空的方案中，后续由多个所述第二导电类型场限环结构与多个所述终端区沟槽结构组成的交替排列结构的首尾两端中，靠近元胞区的一端为所述第二导电类型场限环结构，远离元胞区的一端为所述终端区沟槽结构。而在所述第二导电类型注入区13右侧的边界位置留有一定尺寸不被沟槽挖空的方案中，后续由多个所述第二导电类型场限环结构与多个所述终端区沟槽结构组成的 交替排列结构的首尾两端均为所述第二导电类型场限环结构6。As an example, the trench region needs to cover the boundary position on the left side of the second conductivity type implantation region 13 , and the boundary position on the right side of the second conductivity type injection region 13 may be hollowed out by the trench, or may be left with a certain size Not hollowed out by trenches. Wherein, in the solution in which the boundary position on the right side of the second conductivity type implantation region 13 is hollowed out by trenches, a plurality of the second conductivity type field confinement ring structures and a plurality of the termination region trench structures are subsequently formed. Among the head and tail ends of the alternately arranged structure, the end close to the cell region is the second conductivity type field confinement ring structure, and the end far from the cell region is the termination region trench structure. However, in the solution where a certain size is left on the right side of the second conductivity type implanted region 13 so as not to be hollowed out by the trench, a plurality of the second conductivity type field confinement ring structures and a plurality of the terminals are subsequently formed. The first and last ends of the alternately arranged structure composed of the area trench structures are both the second conductivity type field confinement ring structures 6 .
如图5所示，对所述第二导电类型注入区13进行推结，得到由所述终端区沟槽17间隔的多个第二导电类型场限环结构6。As shown in FIG. 5 , the second conductivity type implanted region 13 is pushed out to obtain a plurality of second conductivity type field confinement ring structures 6 separated by the trenches 17 in the termination region.
作为示例，通过高温退火工艺对所述第二导电类型注入区13进行推结，控制推结时间与温度，使所述第二导电类型注入区13与所述第一导电类型外延层2形成的PN结深度小于沟槽深度，即所述第二导电类型场限环结构6的底面高于所述终端区沟槽结构4的底面。As an example, the second conductivity type implanted region 13 is pushed through a high temperature annealing process, and the push junction time and temperature are controlled, so that the second conductivity type implantation region 13 and the first conductivity type epitaxial layer 2 are formed. The depth of the PN junction is less than the depth of the trench, that is, the bottom surface of the second conductive type field limiting ring structure 6 is higher than the bottom surface of the termination region trench structure 4 .
如图6所示，形成栅介质层12于所述元胞区沟槽16、所述过渡区沟槽18及所述终端区沟槽17的内壁，内壁包括内侧壁与内底面。As shown in FIG. 6 , a gate dielectric layer 12 is formed on the inner walls of the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 , and the inner walls include inner sidewalls and inner bottom surfaces.
作为示例，通过湿法氧化工艺于所述元胞区沟槽16、所述过渡区沟槽18及所述终端区沟槽17表面生长氧化层，氧化层厚度可为0.01μm～5μm，优选0.2μm～1μm。As an example, an oxide layer is grown on the surfaces of the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 by a wet oxidation process, and the thickness of the oxide layer may be 0.01 μm˜5 μm, preferably 0.2 μm. μm～1μm.
如图7所示，形成导电材料11于所述元胞区沟槽16、所述过渡区沟槽18及所述终端区沟槽17中。As shown in FIG. 7 , conductive material 11 is formed in the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 .
作为示例，利用CVD工艺于所述元胞区沟槽16、所述过渡区沟槽18及所述终端区沟槽17内填充浓掺杂多晶硅材料，并利用化学机械抛光(CMP)工艺将材料表面平坦化。As an example, the cell region trenches 16 , the transition region trenches 18 and the termination region trenches 17 are filled with a heavily doped polysilicon material by a CVD process, and a chemical mechanical polishing (CMP) process is used to remove the material. Surface flattening.
进一步的，如图8所示，通过蚀刻工艺去除掉所述第一导电类型外延层2上表面多余的介质层和多晶硅，露出所述第一导电类型外延层2的硅面。其中，所述元胞区沟槽16中的栅介质层12及导电材料11构成元胞区沟槽结构3，所述过渡区沟槽18中的栅介质层12及导电材料11构成过渡区沟槽结构5，所述终端区沟槽17中的栅介质层12及导电材料11构成终端区沟槽结构4。Further, as shown in FIG. 8 , the excess dielectric layer and polysilicon on the upper surface of the first conductivity type epitaxial layer 2 are removed by an etching process, and the silicon surface of the first conductivity type epitaxial layer 2 is exposed. The gate dielectric layer 12 and the conductive material 11 in the cell region trench 16 constitute the cell region trench structure 3 , and the gate dielectric layer 12 and the conductive material 11 in the transition region trench 18 constitute the transition region trench In the trench structure 5 , the gate dielectric layer 12 and the conductive material 11 in the termination region trench 17 constitute the termination region trench structure 4 .
如图9所示，形成绝缘介质层7于所述第一导电类型外延层2上，并形成开口8于所述绝缘介质层7中，所述开口8上下贯穿所述绝缘介质层7以暴露出所述元胞区沟槽结构3的导电部分、所述过渡区沟槽结构5的导电部分及至少一所述终端区沟槽结构4的导电部分。As shown in FIG. 9 , an insulating dielectric layer 7 is formed on the first conductive type epitaxial layer 2 , and an opening 8 is formed in the insulating dielectric layer 7 , and the opening 8 penetrates the insulating dielectric layer 7 up and down to expose The conductive portion of the cell region trench structure 3 , the conductive portion of the transition region trench structure 5 and the conductive portion of at least one of the termination region trench structures 4 are extracted.
作为示例，通过沉积工艺在图8所示结构上沉积所述绝缘介质层7，厚度为0.5μm～5μm，然后在所述绝缘介质层7表面进行涂胶、曝光、显影，并利用干法蚀刻工艺去除元胞区和终端区部分绝缘介质层7以得到所述开口8，最后去掉光刻胶。As an example, the insulating dielectric layer 7 is deposited on the structure shown in FIG. 8 by a deposition process, with a thickness of 0.5 μm˜5 μm, and then the surface of the insulating dielectric layer 7 is subjected to glue coating, exposure, development, and dry etching. The process removes part of the insulating dielectric layer 7 in the cell region and the terminal region to obtain the opening 8, and finally removes the photoresist.
如图10所示，形成正面肖特基阳极9于绝缘介质层7上，所述正面肖特基阳极9填充进所述开口8以与所述元胞区沟槽结构3、所述过渡区沟槽结构5及至少一所述终端区沟槽结构4电连接。As shown in FIG. 10 , a front-side Schottky anode 9 is formed on the insulating dielectric layer 7 , and the front-side Schottky anode 9 is filled into the opening 8 to connect with the cell region trench structure 3 and the transition region. The trench structure 5 and at least one of the trench structures 4 in the termination region are electrically connected.
作为示例，于所述第一导电类型外延层2、沟槽结构表面及所述绝缘介质层7表面生 长一层肖特基金属层，肖特基金属材料包括但不限于Ti、Pt、Ni、Cr、W、Mo或Co，退火形成肖特基结并于其表面生长厚金属层，作为所述正面肖特基阳极9。本实施例中，所述正面肖特基阳极9在水平面上的投影与所有终端区沟槽结构4在水平面上的投影均有重叠部分。As an example, a Schottky metal layer is grown on the first conductivity type epitaxial layer 2 , the surface of the trench structure and the surface of the insulating dielectric layer 7 , and the Schottky metal material includes but is not limited to Ti, Pt, Ni, Cr, W, Mo or Co, annealed to form a Schottky junction and grow a thick metal layer on its surface as the front Schottky anode 9 . In this embodiment, the projection of the front Schottky anode 9 on the horizontal plane overlaps with the projections of all the trench structures 4 in the termination region on the horizontal plane.
请参阅图11，形成背面阴极10于所述第一导电类型衬底1下方。Referring to FIG. 11 , a backside cathode 10 is formed under the first conductive type substrate 1 .
作为示例，减薄所述第一导电类型衬底1，并于所述第一导电类型衬底1背面形成阴极金属，作为背面阴极10。As an example, the first conductive type substrate 1 is thinned, and a cathode metal is formed on the back surface of the first conductive type substrate 1 to serve as the back surface cathode 10 .
至此，制作得到一沟槽性肖特基二极管终端结构，本实施例的方法在终端位置引入P型注入区，利用沟槽阵列将P型注入区阻隔形成多个场限环结构，同时在终端位置将部分沟槽打开以与金属电极产生接触，形成极性场板与浮空场板的搭配组合，可以缓解沟槽型肖特基器件在终端区的电场变化梯度，有利于降低器件的反向漏电流，并提高器件的反向击穿电压。So far, a trenched Schottky diode termination structure is fabricated. The method of this embodiment introduces a P-type implantation region at the termination position, and uses a trench array to block the P-type implantation region to form a plurality of field limiting ring structures. The position opens part of the trench to make contact with the metal electrode, forming a combination of polar field plate and floating field plate, which can alleviate the gradient of the electric field change in the terminal area of the trench Schottky device, which is conducive to reducing the reaction of the device. leakage current and increase the reverse breakdown voltage of the device.
综上所述，本发明的沟槽性肖特基二极管终端结构及其制作方法在终端位置引入P型注入区，利用沟槽阵列将P型注入区阻隔形成多个场限环结构，同时在终端位置将部分沟槽打开以与金属电极产生接触，形成极性场板与浮空场板的搭配组合，可以缓解沟槽型肖特基器件在终端区的电场变化梯度，从而降低了器件的反向漏电流，提高了器件的反向击穿电压。此外，本发明的沟槽型肖特基二极管终端结构可以使用更高的外延层浓度来实现与传统结构相同的耐压能力，有利于降低器件的导通电阻和正向电压Vf。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。To sum up, the trenched Schottky diode termination structure and its fabrication method of the present invention introduce a P-type implantation region at the termination position, and use the trench array to block the P-type implantation region to form a plurality of field confinement ring structures. The terminal position opens part of the trench to make contact with the metal electrode, forming a combination of polar field plate and floating field plate, which can alleviate the electric field change gradient of the trench Schottky device in the terminal region, thereby reducing the device's performance. The reverse leakage current increases the reverse breakdown voltage of the device. In addition, the trench Schottky diode termination structure of the present invention can use a higher epitaxial layer concentration to achieve the same withstand voltage capability as the conventional structure, which is beneficial to reduce the on-resistance and forward voltage Vf of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (10)

  1. 一种沟槽型肖特基二极管终端结构，其特征在于，包括：A trench-type Schottky diode termination structure, characterized in that it includes:
    第一导电类型衬底；a first conductivity type substrate;
    第一导电类型外延层，位于所述第一导电类型衬底上，并划分为元胞区及终端区；a first conductive type epitaxial layer, located on the first conductive type substrate, and divided into a cell area and a terminal area;
    多个元胞区沟槽结构，位于所述第一导电类型外延层中，并位于所述元胞区；a plurality of cell region trench structures located in the first conductivity type epitaxial layer and in the cell region;
    多个终端区沟槽结构，位于所述第一导电类型外延层中，并位于所述终端区；a plurality of terminal area trench structures located in the first conductive type epitaxial layer and located in the terminal area;
    一过渡区沟槽结构，位于所述第一导电类型外延层中，并位于所述元胞区与所述终端区的交界处；a transition region trench structure located in the first conductivity type epitaxial layer and at the junction of the cell region and the termination region;
    多个第二导电类型场限环结构，位于所述第一导电类型外延层中，并位于所述终端区，多个所述第二导电类型场限环结构与多个所述终端区沟槽结构在所述终端区中交替排列；a plurality of second conductivity type field limiting ring structures located in the first conductivity type epitaxial layer and located in the termination region, a plurality of the second conductivity type field limiting ring structures and a plurality of the termination region trenches structures are alternately arranged in the terminal area;
    绝缘介质层，位于所述第一导电类型外延层上；an insulating medium layer, located on the first conductivity type epitaxial layer;
    开口，上下贯穿所述绝缘介质层，所述开口暴露出所述元胞区沟槽结构的导电部分、所述过渡区沟槽结构的导电部分及至少一所述终端区沟槽结构的导电部分；an opening, penetrating the insulating medium layer up and down, the opening exposing the conductive portion of the trench structure in the cell region, the conductive portion of the trench structure in the transition region and at least one conductive portion of the trench structure in the termination region ;
    正面肖特基阳极，位于所述绝缘介质层上，并填充进所述开口以与所述元胞区沟槽结构、所述过渡区沟槽结构及至少一所述终端区沟槽结构电连接；a front Schottky anode, located on the insulating dielectric layer, and filled into the opening to be electrically connected to the cell region trench structure, the transition region trench structure and at least one of the termination region trench structures ;
    背面阴极，位于所述第一导电类型衬底下方。a back cathode, located under the first conductivity type substrate.
  2. 根据权利要求1所述的沟槽型肖特基二极管终端结构，其特征在于：所述第二导电类型场限环结构的底面高于所述终端区沟槽结构的底面；由多个所述第二导电类型场限环结构与多个所述终端区沟槽结构组成的交替排列结构的首尾两端中，至少有一端为所述第二导电类型场限环结构。The trench Schottky diode termination structure according to claim 1, wherein the bottom surface of the second conductivity type field limiting ring structure is higher than the bottom surface of the termination region trench structure; Among the head and tail ends of the alternately arranged structure composed of the second conductivity type field limiting ring structure and the plurality of the termination region trench structures, at least one end is the second conductivity type field limiting ring structure.
  3. 根据权利要求1所述的沟槽型肖特基二极管终端结构，其特征在于：所述元胞区沟槽结构、所述终端区沟槽结构及所述过渡区沟槽结构均填充有导电材料，所述元胞区沟槽结构、所述终端区沟槽结构及所述过渡区沟槽结构的沟槽内壁与所述导电材料间设有栅介质层。The trenched Schottky diode termination structure according to claim 1, wherein the cell region trench structure, the termination region trench structure and the transition region trench structure are all filled with conductive materials and a gate dielectric layer is provided between the inner walls of the trenches of the cell region trench structure, the terminal region trench structure and the transition region trench structure and the conductive material.
  4. 根据权利要求1所述的沟槽型肖特基二极管终端结构，其特征在于：所述终端区沟槽结构的宽度大于或等于所述元胞区沟槽结构的宽度。The trenched Schottky diode termination structure according to claim 1, wherein the width of the trench structure in the termination region is greater than or equal to the width of the trench structure in the cell region.
  5. 根据权利要求1所述的沟槽型肖特基二极管终端结构，其特征在于：相邻所述终端区 沟槽结构的间距小于或等于相邻所述元胞区沟槽结构的间距。The trenched Schottky diode termination structure according to claim 1, wherein the spacing between the adjacent trench structures in the termination region is less than or equal to the spacing between the adjacent trench structures in the cell region.
  6. 根据权利要求1所述的沟槽型肖特基二极管终端结构，其特征在于：所述正面肖特基阳极在水平面上的投影与所有所述终端区沟槽结构在水平面上的投影均有重叠部分。The trench Schottky diode termination structure according to claim 1, wherein the projection of the front Schottky anode on the horizontal plane overlaps the projection of all the termination region trench structures on the horizontal plane part.
  7. 一种沟槽型肖特基二极管终端结构的制作方法，其特征在于，包括以下步骤：A method for fabricating a trench Schottky diode terminal structure, characterized in that it comprises the following steps:
    提供第一导电类型衬底，形成第一导电类型外延层于所述第一导电类型衬底上；providing a first conductive type substrate, and forming a first conductive type epitaxial layer on the first conductive type substrate;
    形成第二导电类型注入区于所述第一导电类型外延层中；forming a second conductive type implanted region in the first conductive type epitaxial layer;
    形成多个元胞区沟槽、多个终端区沟槽及一过渡区沟槽于所述第一导电类型外延层正面，所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽的底面均低于所述第二导电类型注入区的底面，所述过渡区沟槽位于所述元胞区沟槽与所述终端区沟槽之间，所述过渡区沟槽及所述终端区沟槽均上下贯穿所述第二导电类型注入区，且所述第二导电类型注入区的一端位于所述过渡区沟槽的开口范围内，使得所述过渡区沟槽仅一侧形成有所述第二导电类型注入区，相邻所述终端区沟槽之间均形成有所述第二导电类型注入区；forming a plurality of cell region trenches, a plurality of terminal region trenches and a transition region trench on the front surface of the first conductivity type epitaxial layer, the cell region trenches, the transition region trenches and the termination region The bottom surfaces of the region trenches are all lower than the bottom surface of the second conductivity type implantation region, the transition region trenches are located between the cell region trenches and the termination region trenches, the transition region trenches and The termination region trenches all penetrate the second conductivity type implantation region up and down, and one end of the second conductivity type implantation region is located within the opening range of the transition region trench, so that only one transition region trench is formed. The second conductive type implantation region is formed on the side, and the second conductive type implantation region is formed between adjacent trenches of the termination region;
    对所述第二导电类型注入区进行推结，得到由所述终端区沟槽间隔的多个第二导电类型场限环结构；performing push junction on the implanted region of the second conductivity type to obtain a plurality of field confinement ring structures of the second conductivity type spaced by the trenches in the termination region;
    形成栅介质层于所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽的内壁；forming a gate dielectric layer on the inner walls of the cell region trenches, the transition region trenches and the termination region trenches;
    形成导电材料于所述元胞区沟槽、所述过渡区沟槽及所述终端区沟槽中；forming conductive material in the cell region trenches, the transition region trenches and the termination region trenches;
    形成绝缘介质层于所述第一导电类型外延层上；forming an insulating dielectric layer on the first conductive type epitaxial layer;
    形成开口于所述绝缘介质层中，所述开口上下贯穿所述绝缘介质层以暴露出所述元胞区沟槽结构的导电部分、所述过渡区沟槽结构的导电部分及至少一所述终端区沟槽结构的导电部分；An opening is formed in the insulating dielectric layer, and the opening penetrates the insulating dielectric layer up and down to expose the conductive portion of the cell region trench structure, the conductive portion of the transition region trench structure and at least one of the a conductive portion of the trench structure in the termination region;
    形成正面肖特基阳极于所述绝缘介质层上，所述正面肖特基阳极填充进所述开口以与所述元胞区沟槽结构、所述过渡区沟槽结构及至少一所述终端区沟槽结构电连接；forming a front-side Schottky anode on the insulating dielectric layer, the front-side Schottky anode is filled into the opening to be connected with the cell region trench structure, the transition region trench structure and at least one of the terminations The area trench structure is electrically connected;
    形成背面阴极于所述第一导电类型衬底下方。A backside cathode is formed under the first conductivity type substrate.
  8. 根据权利要求7所述的沟槽型肖特基二极管终端结构的制作方法，其特征在于：所述第二导电类型场限环结构的底面高于所述终端区沟槽结构的底面；由多个所述第二导电类型场限环结构与多个所述终端区沟槽结构组成的交替排列结构的首尾两端中，至少有一端为所述第二导电类型场限环结构。The method for fabricating a trenched Schottky diode termination structure according to claim 7, wherein the bottom surface of the second conductivity type field limiting ring structure is higher than the bottom surface of the trench structure in the termination region; Among the head and tail ends of the alternately arranged structure composed of the second conductivity type field limiting ring structure and a plurality of the termination region trench structures, at least one end is the second conductivity type field limiting ring structure.
  9. 根据权利要求7所述的沟槽型肖特基二极管终端结构的制作方法，其特征在于：所述终端区沟槽结构的宽度大于或等于所述元胞区沟槽结构的宽度；相邻所述终端区沟槽结构的间距小于或等于相邻所述元胞区沟槽结构的间距。The method for fabricating a trenched Schottky diode termination structure according to claim 7, wherein the width of the trench structure in the termination region is greater than or equal to the width of the trench structure in the cell region; The pitch of the trench structures in the termination region is less than or equal to the pitch of the trench structures in the adjacent cell regions.
  10. 根据权利要求7所述的沟槽型肖特基二极管终端结构的制作方法，其特征在于：所述正面肖特基阳极在水平面上的投影与所有所述终端区沟槽结构在水平面上的投影均有重叠部分。The method for fabricating a trenched Schottky diode termination structure according to claim 7, wherein the projection of the front Schottky anode on the horizontal plane is the projection of all the trench structures in the termination region on the horizontal plane There are overlapping parts.
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