CN117238770A - Trench gate MOSFET device and manufacturing method thereof - Google Patents
Trench gate MOSFET device and manufacturing method thereof Download PDFInfo
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Abstract
A trench gate MOSFET device and a method of manufacturing the same, the method of manufacturing comprising: performing first photoetching to synchronously form a first groove, a second groove and a third groove; forming a gate dielectric layer at least on the first trench; depositing a polysilicon layer of a first conductivity type; etching back the polysilicon layer; doping the front surface, forming a body region on the substrate, and forming a field limiting ring doping region at the same time; performing second photoetching, selectively doping the substrate, forming a source region on the body region, and forming a stop ring doped region at the same time; performing third photoetching, and performing patterning treatment on the front surface of the substrate to at least form a source electrode contact hole corresponding to the source region; forming a source electrode on the source contact hole, and forming a first metal layer on the front surface of the substrate; and carrying out photoetching for the fourth time, and carrying out patterning treatment on the first metal layer to obtain the first electrode. The application can provide effective field limiting rings and cutoff rings through four times of photoetching, and ensure the withstand voltage and reliability of the device.
Description
Technical Field
The application relates to the technical field of MOSFET devices, in particular to a trench gate MOSFET device and a manufacturing method thereof.
Background
In the manufacturing process of a semiconductor device, when etching and doping are needed, a photolithography process is needed to complete patterning or doping. Each lithography pattern requires a corresponding one-layer reticle, and the process cost difference between one more reticle and one less reticle is obvious in the manufacturing process of one device.
The number of layers of the mask is continuously compressed in the traditional trench gate MOSFET device, and the current mainstream technology is reduced to 4 layers, namely four times of photoetching is adopted in the device manufacturing process. Although the production cost is effectively reduced, adverse effects are brought, particularly, when the MOSFET is obtained by adopting a four-layer photoetching process and is applied to high breakdown voltage (such as more than 40V), the breakdown voltage BVDSS is degraded, and as the breakdown voltage of the device is raised, the breakdown voltage of the device is seriously degraded, so that the reliability of the device is seriously affected.
Currently, in order to solve the above problems, in the prior art, a field limiting ring is formed in a termination region of a device to improve withstand voltage, and if necessary, the number of times of photolithography is increased to form a stop ring, and thus the photolithography cost is increased.
Disclosure of Invention
The application mainly solves the technical problems that the withstand voltage of the trench gate MOSFET device is reduced and the reliability of the device is affected in the conventional four-layer photoetching process.
According to a first aspect, in one embodiment, a method for manufacturing a trench gate MOSFET device is provided, including:
providing a substrate, wherein part or all of the substrate is used as part or all of a drift region of the device, and the drift region is provided with a second conductivity type;
performing first photoetching, performing patterning treatment on the front surface of the substrate, and synchronously forming a first groove, a second groove and a third groove which respectively correspond to the groove gate, the field limiting ring and the stop ring on the substrate;
forming a gate dielectric layer at least on the first trench;
depositing a polysilicon layer of a first conductivity type on the first groove, the second groove and the third groove, and completely filling at least the first groove to obtain a grid electrode;
etching back the polysilicon layer, and removing polysilicon at least at the bottom of the second groove and the bottom of the third groove;
doping is carried out on the front surface, a body region is formed on the substrate, and meanwhile, a field limiting ring doped region is formed in the drift region through the second groove and the third groove, and the body region and the field limiting ring doped region are of a first conductivity type; the first groove, the second groove and the third groove all penetrate through the body region and part of the drift region;
performing second photoetching to selectively dope the substrate, forming a source region on the body region, and forming a stop ring doped region in the field limiting ring doped region below the source region through a third groove, wherein the source region and the stop ring doped region are both of a second conductivity type;
performing third photoetching, and performing patterning treatment on the front surface of the substrate to at least form a source electrode contact hole corresponding to the source region, wherein the source electrode contact hole penetrates through the source region and part of the body region;
forming a source electrode on the source contact hole, and forming a first metal layer on the front surface of the substrate;
performing fourth photoetching, and performing patterning treatment on the first metal layer to obtain a first electrode; the first electrode is electrically connected with the source electrode;
and forming a second electrode on the back surface of the substrate, or forming a drain region and a second electrode on the back surface of the substrate, wherein the second electrode is electrically connected with the drain region, and the first conductive type and the second conductive type belong to different semiconductor conductive types.
According to a second aspect, in one embodiment there is provided a trench gate MOSFET device comprising at least one cell comprising a trench gate, a body region and a source region, and a termination region comprising a field stop ring and a field stop ring;
the trench gate MOSFET device further comprises a first trench, a second trench and a third trench, wherein the first trench, the second trench and the third trench are positioned in a cell, the trench gate is formed in the first trench, the field limiting ring comprises a field limiting ring doping region formed at the bottom of the second trench, and the stop ring comprises a stop ring doping region formed at the bottom of the third trench;
the first groove, the second groove and the third groove are formed synchronously, and polysilicon in the first groove, the second groove and the third groove is formed synchronously, wherein the polysilicon has the first conductivity type; the side wall of the second groove reserves part of polysilicon to form a first side wall, and the side wall of the third groove reserves part of polysilicon to form a second side wall;
the body region and the field limiting ring doped region are synchronously doped and formed, and are of a first conductivity type, the field limiting ring doped region is formed under the masking of the first side wall, and the field limiting ring doped region is formed in the drift region of the device;
the source region and the stop ring doped region are synchronously doped and formed, the second conductive type is formed under the masking of the second side wall, the stop ring doped region is formed in the drift region of the device, the drift region has the second conductive type, and the first conductive type and the second conductive type belong to different semiconductor conductive types.
According to a third aspect, an embodiment provides a trench gate MOSFET device, characterized in that it is manufactured by the manufacturing method described in the first aspect.
According to the trench gate MOSFET device and the manufacturing method thereof of the embodiment, the forming sequence of the device structure is adjusted, and the second trench corresponding to the field limiting ring and the third trench corresponding to the cut-off ring are synchronously formed when the first trench corresponding to the trench gate is etched; polysilicon at the bottoms of the second groove and the third groove is removed by back etching, so that a field limiting ring doping region can be formed synchronously when a body region is formed; the cut-off ring doped region can be formed simultaneously when the source region doping is performed. Therefore, the MOSFET device manufactured by four times of photoetching still has an effective field limiting ring and a cutoff ring, and the withstand voltage and the reliability of the device are ensured.
Drawings
Fig. 1 is a schematic diagram of a trench gate MOSFET device of the prior art with four/five photolithography steps;
FIG. 2 is a process schematic diagram of a five photolithography process for the device of FIG. 1 (B);
fig. 3 is a flowchart of a method for manufacturing a trench gate MOSFET device according to an embodiment;
fig. 4 is a schematic structural diagram of a trench gate MOSFET device according to an embodiment;
FIG. 5 is a process diagram (I) of a manufacturing method according to one embodiment;
FIG. 6 is a schematic process diagram (II) of a manufacturing method according to an embodiment;
FIG. 7 is a process schematic (III) of a manufacturing method according to an embodiment;
FIG. 8 is a process diagram (IV) of a manufacturing method according to an embodiment;
FIG. 9 is a process diagram (fifth) of a manufacturing method according to an embodiment;
FIG. 10 is a process diagram (sixth) of a manufacturing method according to an embodiment;
FIG. 11 is a process schematic (seventh) of a manufacturing method according to an embodiment;
FIG. 12 is a process schematic (eighth) of a manufacturing method according to one embodiment;
FIG. 13 is a process diagram (nine) of a manufacturing method according to one embodiment;
fig. 14 is a schematic structural diagram of another trench-gate MOSFET device according to an embodiment.
Reference numerals: 1-a drift region; 11-a first trench; 12-a second trench; 13-a third trench; 2-body region; 3-trench gate; 30-a polysilicon layer; 31-gate dielectric layer; 32-gate; 4-field limiting rings; 41-field limiting ring doped region; 42-a first side wall; 5-a stop ring; 51-a cut-off ring doped region; 52-a second side wall; 53-a cutoff ring electrode; 54-a third electrode; 6-source region; 61-a source electrode; 7-a first electrode; 8-drain region; 9-a second electrode; 10-interlayer dielectric layer.
Detailed Description
The application will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, related operations of the present application have not been shown or described in the specification in order to avoid obscuring the core portions of the present application, and may be unnecessary to persons skilled in the art from a detailed description of the related operations, which may be presented in the description and general knowledge of one skilled in the art.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated.
In the present application, the first conductivity type and the second conductivity type belong to different semiconductor conductivity types, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type; when the first conductivity type is N-type, the second conductivity type is P-type, and vice versa. In the present application, the first conductivity type is P-type and the second conductivity type is N-type.
In the present application, the substrate of the MOSFET device is generally referred to as a silicon wafer, but other materials, such as silicon carbide, gallium nitride, etc., may be used depending on the actual device application. The substrate may be N-type, P-type, or undoped, starting materials or starting structural layers for the device fabrication process. When the substrate corresponds to different device types, after the device is manufactured, the substrate can be partially or completely used as a drain region, a buffer layer or a drift region of the device. The structure obtained by doping, epitaxy, thermal oxidation and the like of the substrate is also a sheet structure mainly made of monocrystalline silicon, and the appearance structure can be generally called a wafer or a silicon wafer or a substrate, and can also be continuously called a substrate in part. In mass production, multiple devices may be subjected to the same process using the same substrate, and therefore, a standardized base may be formed for production, without requiring substrate processing from scratch, and time may be saved.
As shown in fig. 1, the conventional trench gate MOSFET device includes a cell region, where one cell may include a source region, a source electrode, a body region, a trench gate, a drift region, and a drain region, and a termination region, which may include at least one field stop ring (or field stop ring). Wherein the first electrode is used for connecting source electrodes (or source electrodes) of a plurality of cells; the second electrode is used for connecting the drain regions of the plurality of cells and directly serves as a drain electrode (or called a drain electrode).
As shown in fig. 1 (a), some devices do not have a field limiting ring and a stop ring in the termination region, and may be formed by four photolithography processes, where four photolithography processes respectively correspond to trench etching of the trench gate, source region doping, source contact hole formation, and first electrode etching. In these four photolithographic processes, the body region is front side common.
As shown in (B) of fig. 1, some devices are provided with a field limiting ring and a stop ring in a termination region, and when the field limiting ring is implanted into a body region, photolithography is adopted to form the field limiting ring by doping in the termination region synchronously.
The applicant researches find that, as shown in fig. 2, the existing five times of photolithography process takes the drift region as an N type as an example, and as shown in (a) of fig. 2, the first time of photolithography is trench etching to form trenches corresponding to the trench gate and the stop ring; as shown in (B) of fig. 2, a dielectric layer is formed in the trench, and P-type polysilicon is deposited to obtain a trench gate and a stop ring; as shown in fig. 2 (C), the second photolithography, substrate selective doping, P-type doping, forming a body region and a field limiting ring; as shown in fig. 2 (D), the front surface of the substrate is selectively doped by third photolithography to form a source region; as shown in fig. 2 (E), a fourth photolithography is performed to selectively etch the contact hole of the source electrode and deposit metal to form the source electrode; as shown in fig. 2 (F), a metal layer corresponding to the first electrode is deposited, and a fifth photolithography is performed to obtain the first electrode. The back side process is performed subsequently to obtain the device shown in fig. 1 (B).
As described above, after the first photolithography is completed, as shown in fig. 2 (B), P-type polysilicon is deposited, the conductivity type of the polysilicon of the stop ring is P-type, the polysilicon of the stop ring is not doped N-type in the subsequent processing, and if selective N-type doping is required, one more photolithography is required, and six more photolithography is required, and the area except for the stop ring is required to be masked. That is, with the existing five photolithography process shown in fig. 2, the conductivity type (P-type) of the stop ring in the device is opposite to that of the drain/source region (N-type), and the stop ring cannot essentially function as the stop ring, such as the stop ring in fig. 1 (B), which is essentially a field limiting ring, is P-type, and has failed.
The applicant has further studied and found that the above-mentioned integral formation of the polysilicon shown in fig. 2 (B) results in the polysilicon of the cut-off ring being of P-type conductivity type, and being in actual use deactivated by the P-type body shield.
Therefore, as shown in fig. 1 (B) and fig. 2, one photolithography is added on the basis of the original four photolithography, the cut-off ring of the trench gate MOSFET device manufactured by the existing five photolithography processes fails, and as the breakdown voltage of the device is raised, the breakdown voltage of the device is seriously degraded, and the P-type trench MOSFET with the Breakdown Voltage (BVDSS) of 60V or above is particularly serious, the breakdown voltage of the device is reduced, and the reliability of the device and the application of the device are seriously affected.
In the embodiment of the application, the manufacturing method of the trench gate MOSFET device is improved, the forming sequence of the structural layers of the device is adjusted, a novel forming mode of the field limiting ring and the stop ring is provided, and finally, on the premise of using four times of photoetching, the stop ring doped region with the same conductive type as the source region/drain region is obtained, and the field limiting ring doped region with the same conductive type as the body region is obtained, so that the field limiting ring and the stop ring can play a role in reverse withstand voltage finally, and the reliability of the device is ensured.
As shown in fig. 3 and fig. 4, the embodiment of the present application provides a trench gate MOSFET device and a method for manufacturing the same, where the trench gate MOSFET device provided by the present application may be manufactured by using the method for manufacturing provided by the present application, or may be manufactured by using other available manufacturing methods.
As shown in fig. 3, the trench gate MOSFET device provided by the present application includes at least one cell and a termination region, wherein the cell includes a trench gate 3, a body region 2, and a source region 6, and the termination region includes a field limiting ring 4 and a stop ring 5; the cell area structure of the trench gate MOSFET device provided by the application can refer to the existing device structure, and the application aims at improving the structures of the field limiting ring 4 and the stop ring 5 and the manufacturing method.
As shown in fig. 6 and 12, the trench gate MOSFET device further includes a first trench 11, a second trench 12 in a termination region, and a third trench 13 in a cell, the trench gate 3 is formed in the first trench 11, the field stop ring 4 includes a field stop ring doped region 41 formed at the bottom of the second trench 12, and the stop ring 5 includes a stop ring doped region 51 formed at the bottom of the third trench 13.
Wherein the first trench 11, the second trench 12 and the third trench 13 are formed simultaneously, and polysilicon in the first trench 11, the second trench 12 and the third trench 13 is formed simultaneously, the polysilicon having the first conductivity type; the sidewalls of the second trench 12 remain partially polysilicon to form the first sidewall 42 and the sidewalls of the third trench 13 remain partially polysilicon to form the second sidewall 52.
As shown in fig. 10, the body region 2 and the field-limiting ring doped region 41 are formed by simultaneous doping, each having the first conductivity type, the field-limiting ring doped region 41 is formed under the masking of the first sidewall 42 and the second sidewall 52, and the field-limiting ring doped region 41 is formed in the drift region 1 of the device.
As shown in fig. 11, the source region 6 and the stop-ring doped region 51 are formed by simultaneous doping, each having the second conductivity type, the stop-ring doped region 51 is formed under the mask of the second sidewall 52, the stop-ring doped region 51 is formed in the drift region 1 of the device, and the portion of the field-limiting-ring doped region 41 under the third trench 13 is formed after doping.
In the present application, the field limiting ring doped region 41 is a functional structure of the field limiting ring 4, the first sidewall 42 in the second trench 12 provides a masking function for the ion implantation of the field limiting ring doped region 41, and the thickness or the height of the first sidewall 42 is not limited.
Similarly, the stop-ring doped region 51 is a functional structure of the stop-ring 5, the second sidewall 52 in the third trench 13 provides a masking function for ion implantation of the stop-ring doped region 51, and the thickness or height of the second sidewall 52 is not limited.
The description of the trench gate MOSFET device provided by the present application is provided above, and the following description is made with respect to the manufacturing method.
As shown in fig. 3, the following description describes a method for manufacturing a trench gate MOSFET device, in which the first conductivity type is P-type and the second conductivity type is N-type, and the method may include:
step 1, providing a substrate, part or all of which serves as part or all of a drift region 1 of the device, the drift region 1 having the second conductivity type. In some embodiments, a substrate may be used as the drain region 8, and an epitaxial layer may be epitaxially formed on the substrate as the drift region 1, that is, the substrate includes the drain region 8 and the drift region 1; in this case, the drift region 1 is a part of the substrate and the drain region 8 is a part, and when such a substrate is used, the preparation of the drain region 8 is not required in step 11. In some embodiments, a substrate is used as the drift region 1, followed by a back-side process to form the drain region 8.
In some embodiments, the method of manufacturing may further comprise:
in step 101, as shown in fig. 5, a pad oxide layer (not shown) is formed on a substrate, and a hard mask layer is formed on the pad oxide layer.
For example, the silicon dioxide grown 300A on the surface of the drift region 1 by using a thermal oxidation process is used as a pad oxide layer (or referred to as a sacrificial oxide layer), and can be used as a buffer layer when ion implantation or deposition of a hard mask layer is performed later, so that lattice damage caused by ion implantation can be prevented or stress caused by the hard mask layer can be reduced. 2000A of silicon dioxide was deposited on the pad oxide layer using a thin film process as a hard mask layer.
Step 2, as shown in fig. 6, performing a first photolithography process, performing a patterning process on the front surface of the substrate, and simultaneously forming a first trench 11, a second trench 12 and a third trench 13 corresponding to the trench gate 3, the field limiting ring 4 and the stop ring 5, respectively, on the substrate. As shown in fig. 10, the first trench 11, the second trench 12 and the third trench 13 all pass through the body region 2 and part of the drift region 1.
In some embodiments, the step 2 may include:
in step 201, a first photoresist layer covering the hard mask layer is formed, and after developing and photoresist removing, first openings corresponding to the first trench 11, the second trench 12 and the third trench 13 are formed.
Step 202, etching the hard mask layer and the pad oxide layer through the first opening, and etching the substrate under the masking of the first photoresist layer and the hard mask layer to form the first trench 11, the second trench 12 and the third trench 13 simultaneously.
The widths (left-right direction in fig. 6) of the second trenches 12 and the third trenches 13 are greater than or equal to three times the thickness of the polysilicon layer 30 deposited later (such as the thickness of the polysilicon layer 30 above the substrate in fig. 8), so as to ensure that the second trenches 12 and the third trenches 13 are not filled up during the subsequent deposition of polysilicon.
Step 203, removing the first photoresist layer, the hard mask layer and the pad oxide layer. For example, the hard mask layer and the pad oxide layer may be removed by CMP or wet etching.
Step 3, as shown in fig. 7, a gate dielectric layer 31 is formed at least on the first trench 11;
in some embodiments, the step 3 may include:
a silicon dioxide layer is formed on the substrate by a thermal oxidation process, and the silicon dioxide layer on the first trench 11 serves as a gate dielectric layer 31 of the trench gate 3. For example, the silicon oxide layer is directly formed by thermal oxidation, and the silicon oxide layer is formed on the surfaces of the first trench 11, the second trench 12, and the third trench 13. For another example, a thin film process may also be used to deposit the silicon dioxide layer.
Step 4, as shown in fig. 8, depositing a polysilicon layer 30 of the first conductivity type on the first trench 11, the second trench 12 and the third trench 13, and completely filling at least the first trench 11 to obtain a gate 32; the thickness of the polysilicon layer 30 may be 0.2 μm to 0.5 μm.
In some embodiments, the thickness of the polysilicon layer 30 is a first predetermined thickness, and the ratio of the width of the second trench 12 to the first predetermined thickness is greater than or equal to 3:1.
After depositing the polysilicon layer 30 of the first conductivity type over the second trench 12, the polysilicon layer 30 does not completely fill the second trench 12; and the thickness of the polysilicon layer 30 on the bottom of the second trench 12 is the same as the thickness of the polysilicon layer 30 on the substrate.
Similarly, the thickness of the polysilicon layer 30 is a first preset thickness, and the ratio of the width of the third trench 13 to the first preset thickness is greater than or equal to 3:1.
After depositing the polysilicon layer 30 of the first conductivity type on the third trench 13, the polysilicon layer 30 does not completely fill the third trench 13; and the thickness of the polysilicon layer 30 on the bottom of the third trench 13 is the same as the thickness of the polysilicon layer 30 on the substrate.
In the embodiment of the present application, after depositing the polysilicon layer 30 of the first conductivity type on the second trench 12/third trench 13, the polysilicon layer 30 does not completely fill the second trench 12/third trench 13; and the thickness of the polysilicon layer 30 at the bottom of the second trench 12/third trench 13 is the same as the thickness of the polysilicon layer 30 on the substrate, so that the polysilicon on the substrate is removed and the polysilicon at the bottom of the second trench 12/third trench 13 is removed at the same time when the polysilicon is etched back later, and the remaining polysilicon forms the first sidewall 42 and the second sidewall 52 respectively.
Step 5, as shown in fig. 9, etching back the polysilicon layer 30, at least removing the polysilicon at the bottom of the second trench 12 and the bottom of the third trench 13.
In some embodiments, the step 5 may include:
the polysilicon layer 30 is etched back by dry etching, the polysilicon layer 30 on the surface of the substrate, the bottom of the second trench 12 and the bottom of the third trench 13 is removed, the polysilicon filled in the first trench 11 remains, a portion of the polysilicon remains on the sidewall of the second trench 12 to form the first sidewall 42, and a portion of the polysilicon remains on the sidewall of the third trench 13 to form the second sidewall 52.
Step 6, as shown in fig. 10, doping is performed on the front surface, forming a body region 2 on the substrate, and forming a field limiting ring doped region 41 in the drift region 1 through the second trench 12 and the third trench 13, wherein the body region 2 has the first conductivity type; the first trench 11, the second trench 12 and the third trench 13 all penetrate the body region 2 and part of the drift region 1.
In the case that the first sidewall 42 and the second sidewall 52 serve as masking structures, the field-limiting ring doped region 41 is formed corresponding to the bottoms of the second trench 12 and the third trench 13, and the field-limiting ring doped region 41 has the same conductivity type and doping concentration as those of the body region 2.
Step 7, as shown in fig. 11, performing a second photolithography to selectively dope the substrate, forming a source region 6 on the body region 2, and forming a stop-ring doped region 51 in the field-limiting ring doped region 41 below the third trench 13, wherein the source region 6 and the stop-ring doped region 51 have the second conductivity type;
in some embodiments, the step 7 may include:
in step 701, a second photoresist layer is formed to cover the surface of the substrate, and after developing and photoresist removing, a second opening corresponding to the third trench 13 and the source region 6 is formed.
In step 702, ion implantation is performed on the field limiting ring doped region 41 under the third trench 13 through the second opening, so as to form the source region 6 and the stop ring doped region 51 simultaneously, wherein the stop ring doped region 51 is formed under the masking of the second photoresist layer and the second sidewall 52.
The stop-ring doped region 51 is formed under the masking of the second photoresist layer and the second sidewall 52, so as to reduce the first conductivity type doping concentration of the second sidewall 52 and increase the second conductivity type doping concentration.
For example, the region between the cell region and the stop ring 5 is covered by a photolithography process, in particular, to ensure that the third trench 13 of the stop ring 5 is not blocked by photoresist, then N-type doping ions are implanted and thermally treated to form the source region 6, at this time, N-type doping ions are also implanted into the bottom of the third trench 13, which is the same conductivity type as the drift region 1.
In addition, in the case of the P-type second sidewall 52 as a masking structure, the N-type dopant ions are doped, and the original P-type conductivity concentration is reduced, and is converted into one of P-, N-, and n+. That is, the degree to which the body region 2 shields the second side wall 52 can be reduced. So that the second sidewall 52 may be turned into N-type, specifically, according to factors such as the P-type concentration of the polysilicon layer 30 deposited at the beginning and the N-type doping concentration of the subsequent doped source region 6, but the second sidewall 52 has at least a reduced P-type concentration and an increased N-type concentration. So that the P-type body region 2 at least does not completely shield the second sidewall 52.
And 8, performing third photoetching, and performing patterning treatment on the front surface of the substrate to at least form a source contact hole corresponding to the source region 6, wherein the source contact hole penetrates through the source region 6 and part of the body region 2.
In some embodiments, the step 8 may include:
step 801, depositing an interlayer dielectric layer 10 on the substrate, wherein the interlayer dielectric layer 10 fills the second trench 12 and the third trench 13. The interlayer dielectric layer 10 may serve as a passivation layer of the device.
Step 802, forming a third photoresist layer covering the inter-layer dielectric layer 10, developing and photoresist removing to form a third opening corresponding to the source contact hole.
And 803, etching the substrate under the masking of the third photoresist layer to form a source electrode contact hole.
In step 804, ion implantation is performed through the third opening under the masking of the third photoresist layer, and an ohmic contact region (not shown) is formed at the bottom of the source contact hole.
In step 9, as shown in fig. 12, a source electrode 61 is formed on the source contact hole, and a first metal layer is formed on the front surface of the substrate.
For example, the source electrode 61 is obtained by filling the source contact hole with tungsten metal. And forming a first metal layer by adopting a surface metal process.
Step 10, as shown in fig. 13, performing a fourth photolithography to pattern the first metal layer, thereby obtaining a first electrode 7; the first electrode 7 is electrically connected to the source electrode 61.
Step 11, as shown in fig. 3, forming a second electrode 9 on the back surface of the substrate, or forming a drain region 8 and the second electrode 9 on the back surface of the substrate, where the second electrode 9 is electrically connected with the drain region 8, so as to complete the manufacture of the trench gate MOSFET device.
In some embodiments, to ensure that the potential of the doped region 51 is the same as the voltage potential of the drain region 8 in the stop-ring, an effective stop-ring 5 is formed, as in fig. 14, the device may further include a stop-ring electrode 53, and the step 8 may include:
step 810, depositing an interlayer dielectric layer 10 on the substrate, wherein the interlayer dielectric layer 10 fills the second trench 12 and the third trench 13.
Step 820, forming a third photoresist layer covering the inter-layer dielectric layer 10, developing and photoresist removing to form a third opening corresponding to the source contact hole and a fourth opening corresponding to the stop ring contact hole.
And 830, etching the substrate under the masking of the third photoresist layer, forming a source electrode contact hole through the third opening, and forming a stop ring contact hole through the fourth opening.
In step 840, ion implantation is performed through the third opening and the fourth opening under the masking of the third photoresist layer, so as to form ohmic contact regions at the bottom of the source contact hole and the bottom of the stop ring contact hole, respectively.
Correspondingly, the step 9 may include:
a source electrode 61 is formed on the source contact hole, a cut-off ring electrode 53 is formed on the cut-off ring contact hole, and a first metal layer is formed on the front surface of the substrate.
In step 10, it may include:
performing fourth photoetching, and performing patterning treatment on the first metal layer to obtain a first electrode 7 and a third electrode 54; the first electrode 7 is electrically connected to the source electrode 61; the second electrode 9 is electrically connected to the cutoff ring electrode 53.
It can be seen that the present application utilizes a 4-pass lithography process. The multi-ring structure can be formed in the terminal area, so that the problem of pressure resistance degradation of the device is solved on the premise of not increasing production cost, and the pressure resistance reliability and stability of the device are improved. The left graph is a common practice, after a multi-ring terminal structure is formed by adding the mask plate of the body region 2 and simultaneously a simulation reliability test is carried out, the problem of pressure resistance degradation is avoided, and the voltage resistance is still kept above-70V.
In summary, the manufacturing method provided by the application adjusts the manufacturing sequence of the structural layers through reasonable process optimization, and the stop ring 5 is formed after the body region 2 and is not affected by the common injection of the body region 2. The structure of the field limiting ring 4 and the stop ring 5 is also provided, polysilicon in the field limiting ring 4 and the stop ring 5 form polysilicon side walls (corresponding to the first side wall 42 and the second side wall 52) through back etching (no additional mask is needed for back etching), the field limiting ring doped region 41 is formed synchronously when the body region 2 is commonly injected by masking the first side wall 42, photoetching is not needed, and one photoetching step is saved. The cut-off ring doped region 51 is formed synchronously when the source region 6 is doped by masking the second side wall 52, and one mask plate is shared, so that one photoetching step is further saved, the field limiting ring doped region 41 of the trench gate MOSFET device provided by the application has the same conductivity type as the body region 2, the conductivity type of the cut-off ring doped region 51 is the same as the conductivity type of the source region 6, and the process cost is controlled by adopting four photoetching. That is, a device having an effective field limiting ring 4 and a cut-off ring 5 is obtained in a different manner from the existing manufacturing method shown in fig. 2. Therefore, although each substep of the manufacturing method provided by the application is a conventional process, through the ingenious structural design of the stop ring 5 and the stop ring 5, the four photoetching processes can be adjusted, the influence of common injection of the body region 2 is avoided, and the problem that the same conductivity types of the stop ring 5 and the trench gate 3 are caused by synchronously forming the P-type polycrystalline silicon is also avoided.
By the manufacturing method, the trench gate MOSFET device shown in fig. 3 or 14 can be obtained, the cut-off ring doped region 51 at the bottom of the cut-off ring 5 is the same as the source region 6 in the same conductivity type as the drift region 1, the ion implantation concentration of the source region 6 is far greater than that of the body region 2 and cannot be isolated by the body region 2, so that the purpose of equipotential is achieved, the voltage potential of the second electrode 9 at the bottom is equipotential with the cut-off ring doped region 51, the cut-off ring 5 is effectively formed, the interference of external impurity charges is isolated, the withstand voltage degradation is solved under the condition that the production cost is not increased by using a 4-layer mask process (namely four times photoetching), and the reliability of the device is improved. In step 7, the P-type polysilicon sidewall can change the doping concentration under the N-type doping to avoid the complete shielding of the body region 2, and in some embodiments, the polysilicon sidewall can be converted into N-, N-or n+ type to perform the function of auxiliary stop, and together with the stop ring doping region 51, the function of stopping the ring 5 is performed.
If necessary, as shown in fig. 14, the third electrode 54 and the cut-off ring electrode 53 may be formed, and the third electrode 54 and the second electrode 9 may be connected to the same potential, so that the potential of the cut-off ring doped region 51 is the same as that of the drain region 8 in the off state.
Reference is made to various exemplary embodiments herein. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope herein. For example, the various operational steps and components used to perform the operational steps may be implemented in different ways (e.g., one or more steps may be deleted, modified, or combined into other steps) depending on the particular application or taking into account any number of cost functions associated with the operation of the system.
While the principles herein have been shown in various embodiments, many modifications of structure, arrangement, proportions, elements, materials, and components, which are particularly adapted to specific environments and operative requirements, may be used without departing from the principles and scope of the present disclosure. The above modifications and other changes or modifications are intended to be included within the scope of this document.
The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes may be made without departing from the scope of the present disclosure. Accordingly, the present disclosure is to be considered as illustrative and not restrictive in character, and all such modifications are intended to be included within the scope thereof. Also, advantages, other advantages, and solutions to problems have been described above with regard to various embodiments. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, system, article, or apparatus. Furthermore, the term "couple" and any other variants thereof are used herein to refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and/or any other connection.
Those skilled in the art will recognize that many changes may be made to the details of the above-described embodiments without departing from the underlying principles of the application. Accordingly, the scope of the application should be determined only by the following claims.
Claims (10)
1. A method of fabricating a trench gate MOSFET device, comprising:
providing a substrate, part or all of which serves as part or all of a drift region (1) of the device, the drift region (1) having the second conductivity type;
performing first photoetching, and performing patterning treatment on the front surface of the substrate to synchronously form a first groove (11), a second groove (12) and a third groove (13) which respectively correspond to the groove gate (3), the field limiting ring (4) and the stop ring (5) on the substrate;
forming a gate dielectric layer (31) at least on the first trench (11);
depositing a polysilicon layer (30) of a first conductivity type over the first trench (11), the second trench (12) and the third trench (13), at least the first trench (11) being completely filled, resulting in a gate (32);
etching back the polysilicon layer (30) to remove at least polysilicon at the bottom of the second trench (12) and at the bottom of the third trench (13);
doping is carried out on the front surface, a body region (2) is formed on the substrate, meanwhile, a field limiting ring doping region (41) is formed in the drift region (1) through the second groove (12) and the third groove (13), and the body region (2) and the field limiting ring doping region (41) are of a first conductivity type; the first groove (11), the second groove (12) and the third groove (13) all penetrate through the body region (2) and part of the drift region (1);
performing a second photolithography to selectively dope the substrate, forming a source region (6) on the body region (2), and simultaneously forming a stop-ring doped region (51) in the field-limiting ring doped region (41) below the source region (6) through the third trench (13), wherein the source region and the stop-ring doped region (51) are both of a second conductivity type;
performing third photoetching, and performing patterning treatment on the front surface of the substrate to form at least a source contact hole corresponding to the source region (6), wherein the source contact hole penetrates through the source region (6) and part of the body region (2);
forming a source electrode (61) on the source contact hole, and forming a first metal layer on the front surface of the substrate;
carrying out photoetching for the fourth time, and carrying out patterning treatment on the first metal layer to obtain a first electrode (7); the first electrode (7) is electrically connected to the source electrode (61);
forming a second electrode (9) on the back surface of the substrate, or forming a drain region (8) and a second electrode (9) on the back surface of the substrate, wherein the second electrode (9) is electrically connected with the drain region (8), and the first conductive type and the second conductive type belong to different semiconductor conductive types.
2. The method of manufacturing of claim 1, wherein the thickness of the polysilicon layer (30) is a first predetermined thickness, and the ratio of the width of the second trench (12) to the first predetermined thickness is greater than or equal to 3:1;
-after depositing a polysilicon layer (30) of a first conductivity type on the second trench (12), the polysilicon layer (30) incompletely filling the second trench (12); and the thickness of the polysilicon layer (30) on the bottom of the second groove (12) is the same as the thickness of the polysilicon layer (30) on the substrate;
and/or the number of the groups of groups,
the thickness of the polysilicon layer (30) is a first preset thickness, and the ratio of the width of the third groove (13) to the first preset thickness is greater than or equal to 3:1;
-after depositing a polysilicon layer (30) of the first conductivity type on the third trench (13), the polysilicon layer (30) incompletely filling the third trench (13); and the thickness of the polysilicon layer (30) on the bottom of the third groove (13) is the same as the thickness of the polysilicon layer (30) on the substrate.
3. The method of manufacturing according to claim 1, wherein etching back the polysilicon layer (30) removes at least polysilicon at the bottom of the second trench (12) and at the bottom of the third trench (13), comprising:
and etching back the polysilicon layer (30), removing the polysilicon layer (30) on the surface of the substrate, the bottom of the second groove (12) and the bottom of the third groove (13), reserving the polysilicon filled on the first groove (11), reserving part of the polysilicon on the side wall of the second groove (12) to form a first side wall (42), and reserving part of the polysilicon on the side wall of the third groove (13) to form a second side wall (52).
4. A method of manufacturing as claimed in claim 3, characterized in that a second photolithography is performed to selectively dope the substrate, forming a source region (6) on the body region (2) while forming a stop-ring doped region (51) in the field-limiting ring doped region (41) therebelow through the third trench (13), comprising:
forming a second photoresist layer covering the surface of the substrate, developing and photoresist removing to form a second opening corresponding to the third groove (13) and the source region (6);
and performing ion implantation on the field limiting ring doped region (41) below the third groove (13) through the second opening to synchronously form a source region (6) and a stop ring doped region (51), wherein the stop ring doped region (51) is formed under the masking of the second photoresist layer and the second side wall (52).
5. The manufacturing method according to claim 1, characterized in that performing a third photolithography, patterning the front surface of the substrate, at least forming a source contact hole corresponding to the source region (6), comprises:
depositing an interlayer dielectric layer (10) on the substrate, wherein the interlayer dielectric layer (10) fills the second groove (12) and the third groove (13);
forming a third photoresist layer covering the interlayer dielectric layer (10), developing and photoresist removing to form a third opening corresponding to the source electrode contact hole;
etching the substrate under the masking of the third photoresist layer to form the source electrode contact hole;
and under the masking of the third photoresist layer, performing ion implantation through the third opening, and forming an ohmic contact region at the bottom of the source electrode contact hole.
6. The manufacturing method according to claim 1, wherein patterning the front surface of the substrate to form at least a source contact hole corresponding to the source region (6) comprises:
depositing an interlayer dielectric layer (10) on the substrate, wherein the interlayer dielectric layer (10) fills the second groove (12) and the third groove (13);
forming a third photoresist layer covering the interlayer dielectric layer (10), developing and removing photoresist to form a third opening corresponding to the source electrode contact hole and a fourth opening corresponding to the cutoff ring contact hole;
etching the substrate under the masking of the third photoresist layer, forming the source electrode contact hole through the third opening, and forming the stop ring contact hole through the fourth opening;
under the masking of the third photoresist layer, performing ion implantation through the third opening and the fourth opening to form ohmic contact areas at the bottoms of the source electrode contact hole and the stop ring contact hole respectively;
wherein forming a source electrode (61) on the source contact hole and forming a first metal layer on the front surface of the substrate comprises:
a source electrode (61) is formed on the source contact hole, a stop ring electrode (53) is formed on the stop ring contact hole, and a first metal layer is formed on the front surface of the substrate.
7. The method of manufacturing of claim 1, wherein prior to performing the first lithography, the method of manufacturing further comprises:
forming a pad oxide layer on a substrate, and forming a hard mask layer on the pad oxide layer;
performing first lithography, performing patterning treatment on the front surface of a substrate, and synchronously forming a first groove (11), a second groove (12) and a third groove (13) corresponding to the groove gate (3), the field limiting ring (4) and the stop ring (5) on the substrate, wherein the patterning treatment comprises the following steps:
forming a first photoresist layer covering the hard mask layer, developing and photoresist removing to form first openings corresponding to the first groove (11), the second groove (12) and the third groove (13);
etching the hard mask layer and the pad oxide layer through the first opening, and under the masking of the first photoresist layer and the hard mask layer, etching the substrate to form the first groove (11), the second groove (12) and the third groove (13) simultaneously;
and removing the first photoresist layer, the hard mask layer and the pad oxide layer.
8. The manufacturing method according to claim 1, wherein forming a gate dielectric layer (31) at least on the first trench (11) comprises:
and forming a silicon dioxide layer on the substrate by adopting a thermal oxidation process, wherein the silicon dioxide layer on the first groove (11) is used as a gate dielectric layer (31) of the groove gate (3).
9. A trench gate MOSFET device comprising at least one cell and a termination region, characterized in that the cell comprises a trench gate (3), a body region (2) and a source region (6), the termination region comprising a field limiting ring (4) and a cut-off ring (5);
the trench gate MOSFET device further comprises a first trench (11), a second trench (12) and a third trench (13) which are positioned in a cell, wherein the trench gate (3) is formed in the first trench (11), the field limiting ring (4) comprises a field limiting ring doping region (41) formed at the bottom of the second trench (12), and the stop ring (5) comprises a stop ring doping region (51) formed at the bottom of the third trench (13);
the first groove (11), the second groove (12) and the third groove (13) are formed synchronously, and polysilicon in the first groove (11), the second groove (12) and the third groove (13) is formed synchronously, wherein the polysilicon has a first conductivity type; the side wall of the second groove (12) reserves part of polysilicon to form a first side wall (42), and the side wall of the third groove (13) reserves part of polysilicon to form a second side wall (52);
the body region (2) and the field limiting ring doped region (41) are synchronously doped and formed, and each field limiting ring doped region has a first conductivity type, the field limiting ring doped region (41) is formed under the masking of the first side wall (42), and the field limiting ring doped region (41) is formed in the drift region (1) of the device;
the source region (6) and the stop-ring doped region (51) are synchronously doped and are respectively provided with a second conductivity type, the stop-ring doped region (51) is formed under the masking of the second side wall (52), the stop-ring doped region (51) is formed in a drift region (1) of the device, the drift region (1) is provided with the second conductivity type, and the first conductivity type and the second conductivity type belong to different semiconductor conductivity types.
10. A trench gate MOSFET device manufactured by the manufacturing method of any one of claims 1-8.
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