CN110400836A - A kind of power semiconductor and preparation method thereof - Google Patents
A kind of power semiconductor and preparation method thereof Download PDFInfo
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- CN110400836A CN110400836A CN201910805820.0A CN201910805820A CN110400836A CN 110400836 A CN110400836 A CN 110400836A CN 201910805820 A CN201910805820 A CN 201910805820A CN 110400836 A CN110400836 A CN 110400836A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000002360 preparation method Methods 0.000 title description 3
- 230000001413 cellular effect Effects 0.000 claims abstract description 51
- 210000000746 body region Anatomy 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 9
- 230000026267 regulation of growth Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The present invention relates to technical field of semiconductors; specifically disclose a kind of power semiconductor; including semiconductor substrate; semiconductor substrate is divided into cellular region and terminal protection area; wherein; semiconductor substrate includes the first conductivity type substrate and the first conductive type epitaxial layer, and the surface of the first conductive type epitaxial layer is provided with the second conductivity type body region；First kind groove is provided in the second conductivity type body region of cellular region, the channel bottom of first kind groove protrudes into first kind conductive type epitaxial layer；Position in second conductivity type body region in terminal protection area close to cellular region is provided at least one the second class groove；The trench depth of second class groove is less than the trench depth of first kind groove, and the groove opening width of the second class groove is less than the groove opening width of first kind groove.The invention also discloses a kind of production methods of power semiconductor.Power semiconductor provided by the invention improves the pressure-resistant reliability of power semiconductor.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of power semiconductors and power semiconductor
Production method.
Background technique
Power semiconductor generally includes setting for the active area of current flowing and is arranged for protecting active area
Terminal protection area.When power semiconductor work is in reverse blocking state, the side of active area can be alleviated in terminal protection area
Edge strong electrical field improves device pressure resistance, reduces the effect of device creepage.The structure in terminal protection area, on the one hand affects device
The height of pressure resistance；On the other hand the size of the chip area of device is also affected, i.e., the integrated level of cellular in influence active area.
It is as shown in Figure 1 the structure of existing conventional trench MOSFET, by taking N-type device as an example, on the section of MOS device,
MOS device terminal protection area includes the potential dividing ring of at least one groove structure, and the inner wall of groove is covered with insulating oxide, is covering
It is stamped filled with conductive polycrystalline silicon in the groove of insulating oxide, groove notch and notch two sides are provided with insulating medium layer, lead
Electric polysilicon is closed in groove by insulating medium layer, and the dividing groove in potential dividing ring is made to become floating state.
When device work is in reverse blocking state, grid connects zero potential with source electrode, floating conductive polycrystalline in groove
Silicon is sensed as high potential, and the voltage of device reverse blocking is higher, the floating conductive polycrystalline silicon sense in the groove of cellular region
The current potential that should go out is higher, since depletion layer understands the side wall bends upward along the groove near cellular region to silicon face, specifically comes
It says, trenched side-wall is the trenched side-wall adjacent to cellular region side, the position of the electric field concentration marked as shown in figure 1, therefore, depletion layer
The more original depletion width for being parallel to semiconductor substrate surface direction of width narrows many, causes on being located at trenched side-wall
Insulation formed strong electrical field on gate oxide surface, and floating conductive polycrystalline silicon in the groove of cellular region induces
Current potential it is higher, be formed by that electric field is stronger, due to the thinner thickness for the gate oxide that insulate, voltage endurance capability is limited, can reduce device
The pressure-resistant reliability of part.
Summary of the invention
The present invention provides the production methods of a kind of power semiconductor and power semiconductor, solve the relevant technologies
Present in power semiconductor pressure-resistant integrity problem.
As one aspect of the present invention, a kind of power semiconductor, including semiconductor substrate, the semiconductor are provided
Substrate is divided into cellular region and terminal protection area, and the cellular region is located at the center of the semiconductor substrate, the terminal
Protection zone is located at the outer ring of the cellular region and is arranged around the cellular region, wherein the semiconductor substrate is led including first
Electric type substrates and the first conductive type epitaxial layer in first conductivity type substrate, outside first conduction type
The surface for prolonging layer is provided with the second conductivity type body region；
First kind groove, the ditch of the first kind groove are provided in second conductivity type body region of the cellular region
Trench bottom protrudes into the first kind conductive type epitaxial layer；
Position in second conductivity type body region in the terminal protection area close to the cellular region is provided at least
A piece second class groove；
The trench depth of the second class groove is less than the trench depth of the first kind groove, the groove of the second class groove
Opening width is less than the groove opening width of the first kind groove.
Further, at least one third is provided in second conductivity type body region in the terminal protection area
Class groove, the third class groove are arranged around the second class groove；
The trench depth of the third class groove is not less than the trench depth of the first kind groove, the ditch of the third class groove
Channel opening width is not less than the groove opening width of the first kind groove.
Further, the inner wall of the first kind groove, the second class groove and third class groove has been respectively formed on grid oxide layer,
Conductive polycrystalline silicon is provided in the first kind groove, the second class groove and third class groove, in the first kind groove
Conductive polycrystalline silicon connects grid potential, and the equal floating of conductive polycrystalline silicon in the second class groove and the third class groove is set
It sets.
Further, 3 described are provided in second class conductivity type body region in the terminal protection area
Two class grooves and 3 third class grooves.
Further, at least one terminal is provided in second conductivity type body region in the terminal protection area
Groove, the terminal trenches are arranged around the second class groove；
The trench depth and groove opening width of the terminal trenches are identical as the first kind groove.
Further, 3 described are provided in second class conductivity type body region in the terminal protection area
Two class grooves and 4 terminal trenches.
Further, the surface positioned at second conductivity type body region of the cellular region is provided with the first conduction type
Source region, the surface positioned at the cellular region and second conductivity type body region in the terminal protection area are provided with insulation
Dielectric layer, the dielectric layer surface positioned at the cellular region are provided with source metal, the insulation positioned at the terminal protection area
Dielectric layer surface is provided with gate bus metal, and the source metal passes through the through-hole and described second on the insulating medium layer
Conductivity type body region and the first conduction type source contact.
Further, the power semiconductor includes N-type power semiconductor and p-type power semiconductor,
When the power semiconductor is the N-type power semiconductor, the first conduction type is N-type, the second conduction type
For p-type, when the power semiconductor is the P-type semiconductor device, the first conduction type is p-type, the second conductive-type
Type is N-type.
As another aspect of the present invention, a kind of production method of power semiconductor is provided, wherein the power
The production method of semiconductor devices includes:
The first conductivity type substrate is provided, one conductive type epitaxial layer of growth regulation in first conductivity type substrate；
The selective etch groove on first conductive type epitaxial layer forms first kind groove and the second class groove；
Thermally grown formation grid oxide layer；
Conductive polycrystalline silicon is deposited on the grid oxide layer, and is etched and retained in the first kind groove and the second class groove
Conductive polycrystalline silicon；
The second conductive type impurity and thermal annealing are injected, the second conductivity type body region is formed；
The first conductive type impurity of Selective implantation simultaneously activates, and forms the first conduction type source region；
Insulating medium layer is deposited, then selective etch goes out through-hole on insulating medium layer, and injects the second conductive type impurity；
Metal and selective etch metal are deposited, source metal and gate bus metal are formed.
Further, the production method of the power semiconductor further include:
While forming the first kind groove and the second class groove, selected on first conductive type epitaxial layer
Property etching groove, form third class groove or terminal trenches.
By above-mentioned power semiconductor and preparation method thereof, the second class groove in terminal protection area is located at by reducing
Trench depth and groove opening width reduce when power semiconductor is in reverse blocking state close to cellular region
Terminal trenches in conductive polycrystalline silicon on the current potential that induces, the insulation gate oxide table being located on trenched side-wall can be inhibited
Strong electrical field was formed on face, to improve the pressure-resistant reliability of power semiconductor.
Detailed description of the invention
The drawings are intended to provide a further understanding of the invention, and constitutes part of specification, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of power semiconductor in the prior art.
Fig. 2 is a kind of structural schematic diagram of embodiment of power semiconductor of the invention.
Fig. 3 is the structural schematic diagram of the another embodiment of power semiconductor of the invention.
Fig. 4 is the structural representation of one conductive type epitaxial layer of growth regulation in the first conductivity type substrate provided by the invention
Figure.
Fig. 5 is the structural schematic diagram provided by the invention for forming first kind groove, the second class groove and third class groove.
Fig. 6 is the structural schematic diagram provided by the invention for forming grid oxide layer.
Fig. 7 is deposit conductive polycrystalline silicon provided by the invention and the structural schematic diagram for forming the conductive polycrystalline silicon in groove.
Fig. 8 is the structural schematic diagram provided by the invention for forming the second conductivity type body region and the first conduction type source region.
Fig. 9 is that the structure of the second conductive type impurity of the through-hole provided by the invention for forming insulating medium layer and injection is shown
It is intended to.
Specific embodiment
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combine.The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
In order to make those skilled in the art more fully understand the present invention program, below in conjunction with attached in the embodiment of the present invention
Figure, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only this
The embodiment of a part is invented, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, should fall within the scope of the present invention.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein.In addition, term " includes " and " tool
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing a series of steps or units
Process, method, system, product or equipment those of are not necessarily limited to be clearly listed step or unit, but may include without clear
Other step or units listing to Chu or intrinsic for these process, methods, product or equipment.
A kind of power semiconductor is provided in the present embodiment, and Fig. 2 and Fig. 3 are provided according to embodiments of the present invention
The structural schematic diagram of power semiconductor, as shown in Figures 2 and 3, comprising: semiconductor substrate, the semiconductor substrate are drawn
It is divided into cellular region 01 and terminal protection area 02, the cellular region 01 is located at the center of the semiconductor substrate, and the terminal is protected
Shield area 02 is located at the outer ring of the cellular region 01 and is arranged around the cellular region 01, wherein the semiconductor substrate includes the
One conductivity type substrate 1 and the first conductive type epitaxial layer 2 in first conductivity type substrate 1, described first leads
The surface of electric type epitaxial layer 2 is provided with the second conductivity type body region 3；
First kind groove 4, the first kind groove are provided in second conductivity type body region 3 of the cellular region 01
3 channel bottom protrudes into the first kind conductive type epitaxial layer 2；
Position in second conductivity type body region 3 in the terminal protection area 02 close to the cellular region 01 is provided with
The second class of at least one groove 11；
The trench depth of the second class groove 11 is less than the trench depth of 4 slot of first kind ditch, the second class groove 11
Groove opening width be less than the first kind groove 4 groove opening width.
By above-mentioned power semiconductor, by reduce be located at the trench depth of the second class groove in terminal protection area with
And groove opening width reduces in the terminal trenches of cellular region when power semiconductor is in reverse blocking state
Conductive polycrystalline silicon on the current potential that induces, can inhibit to be formed on the insulation gate oxide surface being located on trenched side-wall too strong
Electric field, to improve the pressure-resistant reliability of power semiconductor.
As a kind of specifically embodiment of the present embodiment, as shown in Fig. 2, being located at the described of the terminal protection area 02
At least one third class groove 12 is provided in second conductivity type body region 3, the third class groove 12 is around second class
Groove 11 is arranged；
The trench depth of the third class groove 12 is not less than the trench depth of the first kind groove 4, the third class groove
12 groove opening width is not less than the groove opening width of the first kind groove 4.
Further specifically, the inner wall of the first kind groove 4, the second class groove 11 and third class groove 12 is respectively formed on
There is grid oxide layer 6, is provided with conductive polycrystalline silicon 7, institute in the first kind groove 4, the second class groove 11 and third class groove 12
It states conductive polycrystalline silicon 7 in first kind groove 4 and connects grid potential, in the second class groove 11 and the third class groove 12
The equal floating of conductive polycrystalline silicon 7 setting.
It should be understood that the meaning of " floating setting " is to be not connected to any current potential herein, i.e. the second class groove 11 and the
Conductive polycrystalline silicon in three classes groove 12 is not connected to any current potential.
Preferably, as shown in Fig. 2, being located at setting in second class conductivity type body region 3 in the terminal protection area 02
There are 3 second class grooves 11 and 3 third class grooves 12.
It should be understood that the second class groove 11 and third class groove 12 that are arranged in second conductivity type body region 3
Quantity can be configured according to demand, herein without limitation, Fig. 2 be only schematically show.
As another specific embodiment of the present embodiment, as shown in figure 3, being located at described the of the terminal protection area 02
At least one terminal trenches 5 are provided in two conductivity type body regions 3, the terminal trenches 5 are set around the second class groove 11
It sets；
The trench depth and groove opening width of the terminal trenches 5 are identical as the first kind groove 4.
It is understood that the side in the close cellular region 01 of original terminal trenches 5 increases the second class of at least one
Groove 11, this implementation are simple.
Preferably, as shown in figure 3, being located at setting in second class conductivity type body region 3 in the terminal protection area 02
There are 3 second class grooves 11 and 4 terminal trenches 5.
It should be understood that the number for the second class groove 11 and terminal trenches 5 being arranged in second conductivity type body region 3
Amount can be configured according to demand, and herein without limitation, Fig. 3 is only to schematically show.
It should be noted that in terminal protection area 02 can be equipped with a variety of different depths groove, as long as guarantee near
The depth of the groove of cellular region 01 is less than the depth of first kind groove 4, and the depth near the groove of cellular region 01 is smaller, reduces
The effect of the electric field on insulation gate oxide surface on trenched side-wall is better.
Specifically, the surface positioned at second conductivity type body region 3 of the cellular region 01 is provided with the first conductive-type
Type source region 8, the surface positioned at the cellular region 01 and second conductivity type body region 3 in the terminal protection area 02 are all provided with
It is equipped with insulating medium layer 9,9 surface of insulating medium layer positioned at the cellular region 01 is provided with source metal 10, is located at the end
9 surface of insulating medium layer of end protection zone 02 is provided with gate bus metal 13, and the source metal 10 is situated between by the insulation
Through-hole on matter layer 9 is contacted with second conductivity type body region 3 and the first conduction type source region 8.
Preferably, the power semiconductor includes N-type power semiconductor and p-type power semiconductor, when
When the power semiconductor is the N-type power semiconductor, the first conduction type is N-type, and the second conduction type is P
Type, when the power semiconductor is the P-type semiconductor device, the first conduction type is p-type, and the second conduction type is
N-type.
It should be noted that the present embodiment is said so that power semiconductor is N-type power semiconductor as an example
Bright.
Overall description is carried out below with reference to structure of the Fig. 2 to power semiconductor provided in this embodiment.
By taking N-type power device as an example, as shown in Fig. 2, including cellular region 01 and terminal protection area 02, the cellular region 01
In the center of device, the terminal protection area 02 is looped around around cellular region 01, and the cellular region 01 includes several yuan
Born of the same parents' unit, the cellular unit includes semiconductor substrate, and the semiconductor substrate includes N-type substrate 1 and is located in N-type substrate 1
N-type epitaxy layer 2,2 surface of N-type epitaxy layer be equipped with the area PXing Ti 3,3 surface of the area PXing Ti be equipped with first kind groove 4,
It is equipped with grid oxide layer 6 and conductive polycrystalline silicon 7 in the first kind groove 4, the bottom of the first kind groove 4 enters N-type epitaxy layer 2
In, 3 surface of the area PXing Ti is equipped with N-type source region 8, covers insulating medium layer 9, source metal 10 on 01 surface of cellular region
It is contacted by the through-hole on the insulating medium layer 9 with the area PXing Ti 3, N-type source region 8, the terminal protection area 02 includes semiconductor
Substrate, the semiconductor substrate include N-type substrate 1 and the N-type epitaxy layer 2 in N-type substrate 1,2 table of N-type epitaxy layer
Face is equipped with the area PXing Ti 3, is equipped with three second class grooves 11 and three third classes parallel to each other parallel to each other in P body area 3
Groove 12 is designed with grid oxide layer 6 and conductive polycrystalline silicon 7 in these two types of grooves, and all around cellular region 01, the second class groove
11 close to cellular region 01, and trench depth and groove opening width are both less than first kind groove 4, and the third class groove 12 is remote
From cellular region 01, and the second class groove 11 is surrounded, and trench depth and groove opening width are both greater than first kind groove 4.
The conductive polycrystalline silicon 7 in all grooves in terminal protection area 02 is all floating, all ditches in cellular region 01
Conductive polycrystalline silicon 7 in slot all connects grid potential.
As another embodiment of the present invention, a kind of production method of power semiconductor is provided, wherein extremely such as Fig. 4
Shown in Fig. 9, the production method of the power semiconductor includes:
As shown in figure 4, providing the first conductivity type substrate 1, one conduction type of growth regulation in first conductivity type substrate 1
Epitaxial layer 2；
As shown in figure 5, the selective etch groove on first conductive type epitaxial layer 2, forms first kind groove 4 and second
Class groove 11；
It should be noted that embodiment shown in fig. 5 is also formed simultaneously with third class groove 12, as the implementation arranged side by side with Fig. 5
Mode can also be formed simultaneously first kind groove 4, the second class groove 11 and terminal trenches 5.
As shown in fig. 6, thermally grown formation grid oxide layer 6；
As shown in fig. 7, deposit conductive polycrystalline silicon 7 on the grid oxide layer 6, and etches and retain the first kind groove 4 and described
Conductive polycrystalline silicon 7 in second class groove 11；
As shown in figure 8, the second conductive type impurity of injection and thermal annealing, form the second conductivity type body region 3；
As shown in figure 8, the first conductive type impurity of Selective implantation and activating, the first conduction type source region 8 is formed；
As shown in figure 9, deposit insulating medium layer 9, then selective etch goes out through-hole on insulating medium layer 9, and injects second
Conductive type impurity；
As shown in Fig. 2, deposit metal and selective etch metal, form source metal 10 and gate bus metal 13.
The power semiconductor obtained by the production method of above-mentioned power semiconductor is located at terminal by reducing
The trench depth and groove opening width of second class groove of protection zone are in reverse blocking state in power semiconductor
When, reduce the current potential induced on the conductive polycrystalline silicon in the terminal trenches of cellular region, can inhibit to be located at trenched side-wall
On insulation gate oxide surface on formed strong electrical field, to improve the pressure-resistant reliability of power semiconductor.In addition,
The advantage that there is the production method of power semiconductor provided in this embodiment simple process to be easily achieved.
It should be noted that Fig. 4 to Fig. 9 was illustrated so that power semiconductor is N-type power device as an example,
In the first conduction type be N-type, the second conduction type be p-type.
It should be understood that Fig. 4 to Fig. 9, which only illustrates production, obtains power semiconductor shown in Fig. 2, for Fig. 3
Shown in power semiconductor production it is identical as shown in Fig. 4 to Fig. 9, difference be only that Fig. 2 is simultaneously when forming groove
It forms first kind groove, the second class groove and third class groove, Fig. 3 and is simultaneously formed first kind groove, the second class groove and end
Hold groove.
The production method of power semiconductor provided in this embodiment and existing product technique are completely compatible, do not need volume
Outer increase photolithography plate, that is, not needing increase cost can be solved the pressure-resistant integrity problem at prior art center.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (10)
1. a kind of power semiconductor, including semiconductor substrate, the semiconductor substrate is divided into cellular region and terminal is protected
Area is protected, the cellular region is located at the center of the semiconductor substrate, and the terminal protection area is located at the outer ring of the cellular region
And it is arranged around the cellular region, which is characterized in that the semiconductor substrate includes the first conductivity type substrate and is located at described
The surface of the first conductive type epitaxial layer in first conductivity type substrate, first conductive type epitaxial layer is provided with second
Conductivity type body region；
First kind groove, the ditch of the first kind groove are provided in second conductivity type body region of the cellular region
Trench bottom protrudes into the first kind conductive type epitaxial layer；
Position in second conductivity type body region in the terminal protection area close to the cellular region is provided at least
A piece second class groove；
The trench depth of the second class groove is less than the trench depth of the first kind groove, the groove of the second class groove
Opening width is less than the groove opening width of the first kind groove.
2. power semiconductor according to claim 1, which is characterized in that positioned at described the of the terminal protection area
At least one third class groove is provided in two conductivity type body regions, the third class groove is set around the second class groove
It sets；
The trench depth of the third class groove is not less than the trench depth of the first kind groove, the ditch of the third class groove
Channel opening width is not less than the groove opening width of the first kind groove.
3. power semiconductor according to claim 2, which is characterized in that the first kind groove, the second class groove
Grid oxide layer has been respectively formed on the inner wall of third class groove, in the first kind groove, the second class groove and third class groove
It is provided with conductive polycrystalline silicon, the conductive polycrystalline silicon in the first kind groove connects grid potential, the second class groove and institute
State the equal floating setting of conductive polycrystalline silicon in third class groove.
4. power semiconductor according to claim 2, which is characterized in that positioned at described the of the terminal protection area
3 second class grooves and 3 third class grooves are provided in two class conductivity type body regions.
5. power semiconductor according to claim 1, which is characterized in that positioned at described the of the terminal protection area
At least one terminal trenches are provided in two conductivity type body regions, the terminal trenches are arranged around the second class groove；
The trench depth and groove opening width of the terminal trenches are identical as the first kind groove.
6. power semiconductor according to claim 5, which is characterized in that positioned at described the of the terminal protection area
3 second class grooves and 4 terminal trenches are provided in two class conductivity type body regions.
7. power semiconductor as claimed in any of claims 1 to 6, which is characterized in that be located at the cellular
The surface of second conductivity type body region in area is provided with the first conduction type source region, is located at the cellular region and the end
The surface of second conductivity type body region of protection zone is held to be provided with insulating medium layer, the insulation positioned at the cellular region is situated between
Matter layer surface is provided with source metal, and the dielectric layer surface positioned at the terminal protection area is provided with gate bus metal,
The source metal passes through the through-hole and second conductivity type body region and first conduction on the insulating medium layer
Type source contact.
8. power semiconductor as claimed in any of claims 1 to 6, which is characterized in that the power is partly led
Body device includes N-type power semiconductor and p-type power semiconductor, when the power semiconductor is the N-type
When power semiconductor, the first conduction type is N-type, and the second conduction type is p-type, when the power semiconductor is institute
When stating P-type semiconductor device, the first conduction type is p-type, and the second conduction type is N-type.
9. a kind of production method of power semiconductor, which is characterized in that the production method packet of the power semiconductor
It includes:
The first conductivity type substrate is provided, one conductive type epitaxial layer of growth regulation in first conductivity type substrate；
The selective etch groove on first conductive type epitaxial layer forms first kind groove and the second class groove；
Thermally grown formation grid oxide layer；
Conductive polycrystalline silicon is deposited on the grid oxide layer, and is etched and retained in the first kind groove and the second class groove
Conductive polycrystalline silicon；
The second conductive type impurity and thermal annealing are injected, the second conductivity type body region is formed；
The first conductive type impurity of Selective implantation simultaneously activates, and forms the first conduction type source region；
Insulating medium layer is deposited, then selective etch goes out through-hole on insulating medium layer, and injects the second conductive type impurity；
Metal and selective etch metal are deposited, source metal and gate bus metal are formed.
10. the production method of power semiconductor according to claim 9, which is characterized in that the power semiconductor
The production method of device further include:
While forming the first kind groove and the second class groove, selected on first conductive type epitaxial layer
Property etching groove, form third class groove or terminal trenches.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113937150A (en) * | 2020-07-13 | 2022-01-14 | 苏州东微半导体股份有限公司 | Semiconductor power device and method for manufacturing the same |
| CN114068668A (en) * | 2020-08-03 | 2022-02-18 | 华润微电子（重庆）有限公司 | Groove type Schottky diode terminal structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814528A (en) * | 2010-05-04 | 2010-08-25 | 无锡新洁能功率半导体有限公司 | Semiconductor element with improved terminal and manufacturing method thereof |
| CN107403839A (en) * | 2017-07-25 | 2017-11-28 | 无锡新洁能股份有限公司 | Suitable for the power semiconductor device structure and manufacture method of deep trench |
| CN108133965A (en) * | 2018-01-30 | 2018-06-08 | 无锡新洁能股份有限公司 | A kind of power semiconductor of deep trench and preparation method thereof |
| CN210272369U (en) * | 2019-08-29 | 2020-04-07 | 无锡新洁能股份有限公司 | Power semiconductor device |
-
2019
- 2019-08-29 CN CN201910805820.0A patent/CN110400836A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101814528A (en) * | 2010-05-04 | 2010-08-25 | 无锡新洁能功率半导体有限公司 | Semiconductor element with improved terminal and manufacturing method thereof |
| CN107403839A (en) * | 2017-07-25 | 2017-11-28 | 无锡新洁能股份有限公司 | Suitable for the power semiconductor device structure and manufacture method of deep trench |
| CN108133965A (en) * | 2018-01-30 | 2018-06-08 | 无锡新洁能股份有限公司 | A kind of power semiconductor of deep trench and preparation method thereof |
| CN210272369U (en) * | 2019-08-29 | 2020-04-07 | 无锡新洁能股份有限公司 | Power semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113937150A (en) * | 2020-07-13 | 2022-01-14 | 苏州东微半导体股份有限公司 | Semiconductor power device and method for manufacturing the same |
| CN114068668A (en) * | 2020-08-03 | 2022-02-18 | 华润微电子（重庆）有限公司 | Groove type Schottky diode terminal structure and manufacturing method thereof |
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