CN114496755A - Shielding gate MOSFET device and manufacturing method thereof - Google Patents
Shielding gate MOSFET device and manufacturing method thereof Download PDFInfo
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- CN114496755A CN114496755A CN202210008434.0A CN202210008434A CN114496755A CN 114496755 A CN114496755 A CN 114496755A CN 202210008434 A CN202210008434 A CN 202210008434A CN 114496755 A CN114496755 A CN 114496755A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 147
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- 238000000034 method Methods 0.000 claims abstract description 21
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- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 58
- 238000005530 etching Methods 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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Abstract
The application discloses a shielded gate MOSFET device and a manufacturing method thereof, and belongs to the field of semiconductor devices and manufacturing. The method comprises the following steps: after the thick medium layer of the shielding grid is formed, a polysilicon generating area of the shielding grid is formed by photoresist with equal height, the position of the photoresist is deposited to form polysilicon of the shielding grid after the photoresist is removed, and meanwhile, the polysilicon of the shielding grid is deposited to form the polysilicon of the grid close to the side wall of the groove above the thick medium layer of the shielding grid, so that the polysilicon of the shielding grid and the polysilicon of the grid are deposited in the next step under the condition of not increasing the photoetching process, the deposition times of the polysilicon are reduced, and the cost problem caused by more photoetching times in the related technology is solved; in addition, under the new structure and the new process, the overlapping capacitance between the two layers of polysilicon, namely the shielding grid polysilicon and the grid polysilicon, is reduced, and further the input capacitance is reduced.
Description
Technical Field
The application relates to the field of semiconductor devices and manufacturing, in particular to a shielded gate MOSFET device and a manufacturing method thereof.
Background
With the increasing demand of consumer electronics, MOSFETs are increasingly in demand, for example in applications such as drivers, electronic communication devices, power devices, etc. The MOSFET device controls the drain current through the grid voltage, has the characteristics of small driving power, small driving current, high input impedance, high switching speed, good thermal stability and the like, and is widely applied.
In the related art, as the design and manufacturing method of MOSFET devices are continuously improved, and as the market competition is increased, the requirement for cost control is higher and higher, and how to reduce the manufacturing cost without reducing the device performance is an important research direction at present.
For controlling the manufacturing cost, the main direction is related to the number of times of photolithography, the deposition of polysilicon is performed using a photolithography plate, and in the related art, the number of times of polysilicon deposition is increased, which requires increasing the number of times of photolithography plate.
Disclosure of Invention
The application provides a shielded gate MOSFET device and a manufacturing method thereof, which can solve the cost problem caused by more photoetching times in the related technology.
In one aspect, an embodiment of the present application provides a method for manufacturing a shielded gate MOSFET device, including:
providing a substrate etched with a groove, and depositing a shielding grid thick dielectric layer on the inner wall and the bottom of the groove;
filling photoresist in the groove and removing part of the photoresist from the upper part, wherein the top of the photoresist with the residual thickness in the groove is lower than that of the shielding grid thick dielectric layer;
etching the shielding grid thick dielectric layer along the side wall of the groove until the top of the shielding grid thick dielectric layer is flush with the top of the photoresist with the residual thickness;
removing the hard mask layer above the substrate and the photoresist with the residual thickness in the groove;
forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the groove;
forming polycrystalline silicon simultaneously by one-step deposition to form gate polycrystalline silicon and shield gate polycrystalline silicon, wherein the gate polycrystalline silicon is formed above the shield gate thick dielectric layer, and the shield gate polycrystalline silicon is formed in the shield gate thick dielectric layer groove;
forming traps on two sides of the gate dielectric layer, and forming a source electrode above the traps;
depositing a contact hole dielectric layer on the upper surfaces of the source electrode, the well, the gate polysilicon and the shielding gate polysilicon;
etching the contact hole dielectric layer to form a contact hole above the trap, the gate polysilicon and the shielding gate polysilicon;
and forming back metal on the back of the substrate, and filling front metal in the contact hole.
Optionally, the forming of the gate polysilicon 4 and the shielding gate polysilicon 10 by simultaneously forming polysilicon through one-step deposition includes:
depositing polycrystalline silicon 301 in the groove 101 and on the top of the substrate 1, wherein a thin layer of polycrystalline silicon is formed at the flat part above the shielding gate thick dielectric layer 2 and on the top of the substrate 1, and thick layers of polycrystalline silicon are formed in the groove of the shielding gate thick dielectric layer 2 and close to the side wall of the gate dielectric layer 3;
and etching the polysilicon 301, and reserving the gate polysilicon 4 and the shielding gate polysilicon 10, wherein the gate polysilicon (4) is not arranged above the shielding gate polysilicon (10).
Optionally, the etching the polysilicon 301 includes:
and etching the thin-layer polysilicon formed at the flat part above the shielding gate thick dielectric layer 2 and at the top of the substrate 1, and reserving the gate polysilicon 4 above the shielding gate thick dielectric layer 2 and the shielding gate polysilicon 10 in the trench of the shielding gate thick dielectric layer 2.
Optionally, the providing the substrate 1 etched with the trench 101 includes:
providing the substrate 1, and forming a hard mask layer 102 on the upper surface of the substrate 1;
and etching the hard mask layer 102 by a photoetching process to determine a gate forming area, and etching the substrate 1 by taking the hard mask layer 102 as a mask to form the groove 101.
In another aspect, an embodiment of the present application provides a shielded gate MOSFET device, including:
a substrate 1 provided with a trench 101; a shield gate polysilicon 10 formed in the trench 101; the side wall and the bottom of the shielding grid polysilicon 10 are provided with shielding grid thick dielectric layers 2 tightly attached to the inner wall of the groove 101, wherein the top of the shielding grid polysilicon 10 is flush with the top of the shielding grid thick dielectric layer 2; the contact hole dielectric layer 7 covers the top of the shielding gate polysilicon 10 and the top of the shielding gate thick dielectric layer 2, and the shielding gate thick dielectric layer 7 is filled in the groove 101;
the gate polysilicon 4 is formed above the shielding gate thick dielectric layer 2; a gate dielectric layer 3 is arranged on the side wall of the gate polycrystalline silicon 4; the trap 5 is formed on two sides of the gate dielectric layer 3; a source electrode 6 is arranged above the trap 5; a back metal 8 formed on the back surface of the substrate 1; and the front metal 9 is filled in the contact holes 701 above the trap 5, the gate polysilicon 4 and the shielding gate polysilicon 10.
Optionally, the gate polysilicon 4 is located above the shield gate thick dielectric layer 2, and the shield gate polysilicon 10 is located in the trench of the shield gate thick dielectric layer 2.
Optionally, the substrate 1 is a silicon substrate, and an epitaxial layer is disposed on the silicon substrate.
The technical scheme at least comprises the following advantages:
after the thick medium layer of the shielding grid is formed, a polysilicon generating area of the shielding grid is formed by photoresist with equal height, the position of the photoresist is deposited to form polysilicon of the shielding grid after the photoresist is removed, and meanwhile, the polysilicon of the shielding grid is deposited to form the polysilicon of the grid close to the side wall of the groove above the thick medium layer of the shielding grid, so that the polysilicon of the shielding grid and the polysilicon of the grid are deposited in the next step under the condition of not increasing the photoetching process, the deposition times of the polysilicon are reduced, and the cost problem caused by more photoetching times in the related technology is solved; in addition, under the new structure and the new process, the overlapping capacitance between the two layers of polysilicon, namely the shielding grid polysilicon and the grid polysilicon, is reduced, and further the input capacitance is reduced.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flow chart of a method of fabricating a shielded gate MOSFET device according to an exemplary embodiment of the present application;
fig. 2-10 are schematic diagrams illustrating the formation of a shielded gate MOSFET device according to an exemplary embodiment of the present application.
Detailed Description
The technical solution of 9 in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for fabricating a shielded gate MOSFET device according to an exemplary embodiment of the present application is shown, the method comprising:
Optionally, the content of the substrate etched with the trench is provided in step 101, including but not limited to the following content.
Firstly, a substrate is provided, and a hard mask layer is formed on the upper surface of the substrate.
Secondly, the hard mask layer 102 is etched through a photoetching process to determine a gate forming area, and then the substrate 1 is etched by taking the hard mask layer 102 as a mask to form the groove 101.
Referring to fig. 2, there is shown a schematic cross-sectional view of a trench formed at the substrate and a thick shield gate dielectric layer deposited within the trench. Exemplarily, as shown in fig. 2, a substrate 1 is provided, and further, the substrate 1 is a silicon substrate and is formed with an epitaxial layer; when forming the trench 101, first, a hard mask layer 102 is formed on the upper surface of the substrate 1, then a gate forming region of the trench 101 is defined by using a photolithography process, and then the hard mask layer 102 and the substrate 1 are sequentially etched to form the trench 101.
Further, after forming trench 101, as shown in fig. 3, a cross-sectional view of a thick dielectric layer of a shield gate is deposited. In fig. 3, a shield gate thick dielectric layer 2 is deposited on the inner wall and the bottom of the trench 101, and optionally, the shield gate thick dielectric layer 2 may also be formed by oxidation.
And 102, filling photoresist in the groove and removing the photoresist with partial thickness from the top, wherein the top of the photoresist with residual thickness in the groove is lower than that of the shielding grid thick dielectric layer.
Referring to fig. 4, fig. 4 shows a schematic cross-sectional view after photoresist fill. Illustratively, as shown in fig. 4, the trench 101 is filled with a photoresist 103, and after the filling, a part of the thickness of the photoresist 103 is removed from above, and due to the underexposure near the region above the shield gate thick dielectric layer 2 in the trench 101, the photoresist 103 is still left after the development, wherein the top of the remaining thickness of the photoresist 103 is lower than the top of the shield gate thick dielectric layer 2, i.e. the photoresist 103 is left above the bottom of the trench 101.
And 103, etching the shielding grid thick dielectric layer along the side wall of the groove until the top of the shielding grid thick dielectric layer is flush with the top of the photoresist with the residual thickness.
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of the etched thick dielectric layer of the shield gate. Illustratively, as shown in fig. 5, after the shield gate thick dielectric layer 2 is etched, the top of the remaining portion is flush with the top of the remaining portion of the photoresist 103.
And 104, removing the hard mask layer above the substrate and the photoresist with the residual thickness in the groove.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of the hard mask layer and the photoresist after being removed. Illustratively, as shown in fig. 6, the hard mask layer 102 above the substrate 1 is removed, and the photoresist 103 in the trench 101 is removed without a residual portion, and only the shield gate thick dielectric layer 2 remains at the bottom of the trench 101.
And 105, forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the groove.
Referring to fig. 7, fig. 7 is a schematic cross-sectional view of a gate dielectric layer. Illustratively, as shown in fig. 7, the shielding gate thick dielectric layer 2 is located at the bottom of the trench 101, gate dielectric layers 3 are formed at the upper surfaces of both sides of the shielding gate thick dielectric layer 2, and each gate dielectric layer 3 is tightly attached to the inner wall of the trench 101.
And 106, simultaneously forming polycrystalline silicon by one-step deposition to form gate polycrystalline silicon and shield gate polycrystalline silicon, wherein the gate polycrystalline silicon is formed above the shield gate thick dielectric layer, and the shield gate polycrystalline silicon is formed in the shield gate thick dielectric layer groove.
Optionally, the content provided in step 106 includes, but is not limited to, the following.
Depositing polycrystalline silicon in the groove and on the top of the substrate, wherein a thin layer of polycrystalline silicon is formed at the flat part above the thick shielding gate dielectric layer and on the top of the substrate, and thick layers of polycrystalline silicon are formed in the groove of the thick shielding gate dielectric layer and at the position close to the side wall of the gate dielectric layer.
And secondly, etching the polysilicon to leave gate polysilicon and shield gate polysilicon, wherein no gate polysilicon is arranged above the shield gate polysilicon.
In one possible implementation mode, the thin layer of polycrystalline silicon formed on the flat part above the shielding gate thick dielectric layer and on the top of the substrate is removed, gate polycrystalline silicon above the shielding gate thick dielectric layer and shielding gate polycrystalline silicon in the shielding gate thick dielectric layer groove are left, and no gate polycrystalline silicon is arranged above the shielding gate polycrystalline silicon.
Continuing with fig. 7, illustratively, as shown in fig. 7, polysilicon 301 is deposited along the interior of trench 101 and along the top of substrate 1. Wherein, a thin layer of polysilicon is left at the flat position at the moment, and comprises a flat position above the shielding grid thick dielectric layer 2 and a flat position at the top of the substrate 1; in addition, a thick layer of polysilicon is left in the trench of the shield gate thick dielectric layer 2 and close to the side wall of the gate dielectric layer 3.
Further, as shown in fig. 8, fig. 8 shows a schematic cross-sectional view of the gate polysilicon and the shield gate polysilicon. In order to form the gate polysilicon 4 and the shield gate polysilicon 10, the thin polysilicon layers formed at the flat part above the shield gate thick dielectric layer 2 and at the top of the substrate 1 are removed, so that the gate polysilicon 4 above the shield gate thick dielectric layer 2 and the shield gate polysilicon 10 in the trench of the shield gate thick dielectric layer 2 are left.
Schematically, as shown in fig. 9, a process diagram of etching polysilicon is shown. In the first figure from the left of fig. 9, a schematic view of the substrate 1 is shown, the second figure from the left shows a schematic view after the formation of the polysilicon 301, and the third figure from the left shows a schematic view of the gate polysilicon after the etching of the polysilicon 301 and the remaining sidewall.
And step 107, forming a trap at two sides of the gate dielectric layer, and forming a source electrode above the trap.
And step 108, depositing a contact hole dielectric layer on the upper surfaces of the source electrode, the well, the gate polysilicon and the shielding gate polysilicon.
And step 109, etching the contact hole dielectric layer to form a contact hole above the trap, the gate polysilicon and the shielding gate polysilicon.
Referring to fig. 10, fig. 10 shows a cross-sectional view of the product after steps 107 to 110. As shown in fig. 10, after the gate polysilicon and the shield gate polysilicon are formed, a well 5 and a source 6 are injected into both sides of the gate dielectric layer 3, wherein the source 6 is located above the well 5; further, the contact hole dielectric layer 7 is etched to form a contact hole 701, as shown in fig. 10, the contact hole 701 is formed above the well 5, the gate polysilicon 4 and the shield gate polysilicon 10.
Further, a metal layer is deposited on the substrate 1, wherein a back metal 8 is formed on the back surface of the substrate 1, and a front metal 9 is filled in the contact holes 701 at each position, so that the metallization processing is performed on the front surface and the back surface of the substrate.
In summary, the present invention provides a method for manufacturing a shielded gate MOSFET, including: after the thick medium layer of the shielding grid is formed, a polysilicon generating area of the shielding grid is formed by photoresist with equal height, the position of the photoresist is deposited to form polysilicon of the shielding grid after the photoresist is removed, and meanwhile, the polysilicon of the shielding grid is deposited to form the polysilicon of the grid close to the side wall of the groove above the thick medium layer of the shielding grid, so that the polysilicon of the shielding grid and the polysilicon of the grid are deposited in the next step under the condition of not increasing the photoetching process, the deposition times of the polysilicon are reduced, and the cost problem caused by more photoetching times in the related technology is solved; in addition, under the new structure and the new process, the overlapping capacitance between the two layers of polysilicon, namely the shielding grid polysilicon and the grid polysilicon, is reduced, and further the input capacitance is reduced.
Referring to fig. 10, a cross-sectional view of a shielded gate MOSFET device according to an exemplary embodiment of the present application is shown, the device being fabricated by any of the above method embodiments, the device comprising:
a substrate 1 provided with a trench 101; a shield gate polysilicon 10 formed in the trench 101; the side wall and the bottom of the shielding grid polysilicon 10 are provided with a shielding grid thick dielectric layer 2 tightly attached to the inner wall of the groove 101, wherein the top of the shielding grid polysilicon 10 is flush with the top of the shielding grid thick dielectric layer 2; and the contact hole dielectric layer 7 covers the top of the shield gate polysilicon 10 and the top of the shield gate thick dielectric layer 2, and the shield gate thick dielectric layer 7 is filled in the groove 101.
Optionally, the substrate 1 is a silicon substrate, and an epitaxial layer is disposed on the silicon substrate.
The gate polysilicon 4 is formed above the shielding gate thick dielectric layer 2; a gate dielectric layer 3 is arranged on the side wall of the gate polycrystalline silicon 4; the trap 5 is formed on two sides of the gate dielectric layer 3; a source electrode 6 is arranged above the trap 5; a back metal 8 formed on the back surface of the substrate 1; and the front metal 9 is filled in the contact hole 701 above the trap 5, the gate polysilicon 4 and the shield gate polysilicon 10.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A method for manufacturing a shielded gate MOSFET device, comprising:
providing a substrate etched with a groove, and depositing a shielding grid thick dielectric layer on the inner wall and the bottom of the groove;
filling photoresist in the groove and removing part of the photoresist from the upper part, wherein the top of the photoresist with the residual thickness in the groove is lower than that of the shielding grid thick dielectric layer;
etching the shielding grid thick dielectric layer along the side wall of the groove until the top of the shielding grid thick dielectric layer is flush with the top of the photoresist with the residual thickness;
removing the hard mask layer above the substrate and the photoresist with the residual thickness in the groove;
forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the groove;
forming polycrystalline silicon simultaneously by one-step deposition to form gate polycrystalline silicon and shield gate polycrystalline silicon, wherein the gate polycrystalline silicon is formed above the shield gate thick dielectric layer, and the shield gate polycrystalline silicon is formed in the shield gate thick dielectric layer groove;
forming traps on two sides of the gate dielectric layer, and forming a source electrode above the traps;
depositing a contact hole dielectric layer on the upper surfaces of the source electrode, the well, the gate polysilicon and the shielding gate polysilicon;
etching the contact hole dielectric layer to form a contact hole above the trap, the gate polysilicon and the shielding gate polysilicon;
and forming back metal on the back of the substrate, and filling front metal in the contact hole.
2. The method of claim 1, wherein forming the gate polysilicon and the shield gate polysilicon simultaneously by a single deposition step comprises:
depositing polycrystalline silicon in the groove and on the top of the substrate, wherein thin-layer polycrystalline silicon is formed at the flat part above the thick shielding gate dielectric layer and on the top of the substrate, and thick-layer polycrystalline silicon is formed in the groove of the thick shielding gate dielectric layer and close to the side wall of the gate dielectric layer;
and etching the polysilicon to leave the gate polysilicon and the shield gate polysilicon, wherein the gate polysilicon is not arranged above the shield gate polysilicon.
3. The method of claim 2, wherein said etching said polysilicon comprises:
and etching the thin polysilicon formed at the flat part above the thick shielding gate dielectric layer and at the top of the substrate, and reserving the gate polysilicon above the thick shielding gate dielectric layer and the shielding gate polysilicon in the groove of the thick shielding gate dielectric layer.
4. The method of claim 1, wherein providing the substrate etched with the trench comprises:
providing the substrate, and forming a hard mask layer on the upper surface of the substrate;
and etching the hard mask layer by a photoetching process to determine a grid forming area, and etching the substrate by taking the hard mask layer as a mask to form the groove.
5. A shielded gate MOSFET device, comprising:
a substrate (1) provided with a trench (101); a shield gate polysilicon (10) formed in the trench (101); a shielding grid thick dielectric layer (2) tightly attached to the inner wall of the groove (101) is arranged on the side wall and the bottom of the shielding grid polycrystalline silicon (10), wherein the top of the shielding grid polycrystalline silicon (10) is flush with the top of the shielding grid thick dielectric layer (2); the contact hole dielectric layer (7) covers the top of the shielding grid polysilicon (10) and the top of the shielding grid thick dielectric layer (2), and the shielding grid thick dielectric layer (7) is filled in the groove (101);
forming gate polysilicon (4), wherein a gate dielectric layer (3) is arranged on the side wall of the gate polysilicon (4); the trap (5) is formed on two sides of the gate dielectric layer (3); a source electrode (6) is arranged above the trap (5); a back metal (8) formed on the back surface of the substrate (1); and the front metal (9) is filled in the contact hole (701) above the trap (5), the gate polysilicon (4) and the shielding gate polysilicon (10).
6. The device according to claim 5, wherein the gate polysilicon (4) is located above the shield gate thick dielectric layer (2), and the shield gate polysilicon (10) is located in a shield gate thick dielectric layer (2) trench.
7. Device according to claim 5, characterized in that the substrate (1) is a silicon substrate on which an epitaxial layer is provided.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116130522A (en) * | 2023-04-14 | 2023-05-16 | 江苏临德半导体有限公司 | Low grid charge shielding grid semiconductor device capable of reducing manufacturing cost and manufacturing method |
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116130522A (en) * | 2023-04-14 | 2023-05-16 | 江苏临德半导体有限公司 | Low grid charge shielding grid semiconductor device capable of reducing manufacturing cost and manufacturing method |
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
| CN117410173B (en) * | 2023-12-15 | 2024-03-08 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
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