CN110993693A - Groove type power MOSFET and process method thereof - Google Patents
Groove type power MOSFET and process method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 80
- 229920005591 polysilicon Polymers 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims description 110
- 238000002347 injection Methods 0.000 claims description 24
- 239000007924 injection Substances 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000000407 epitaxy Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a groove type power MOSFET, which is characterized in that a semiconductor substrate is provided with a plurality of first grooves, and a first dielectric layer is filled in the first grooves; forming 3 second grooves in the first dielectric layer, wherein the second grooves comprise a source control gate groove in the middle and polysilicon gate grooves on two sides of the source control gate, and the depth of the source control gate groove is greater than that of the polysilicon gate groove; second dielectric layers are arranged in the grooves of the source control grid and the grooves of the polysilicon grid, and the second dielectric layers are attached to the inner side walls and the bottoms of the grooves; and the source control gate trench and the polysilicon gate trench are filled with polysilicon. According to the invention, the second dielectric layer is added between the source control gate and the polysilicon gate, so that the thickness of the gate dielectric layer is not limited between the source control gate and the polysilicon gate, and the electric leakage caused by the undersize interval between the source control gate and the polysilicon gate is effectively improved.
Description
Technical Field
The invention relates to the field of semiconductor devices and manufacturing, in particular to a trench type power MOSFET and a process method thereof.
Background
With the increasing demand of consumer electronics, the demand of power MOSFETs is increasing, for example, in disk drives, automotive electronics, and power devices. The Trench type M0S (Trench M0S) has higher integration level, lower on-resistance, lower gate-drain charge density and larger current capacity, so that the Trench type M0S has lower switching loss and higher switching speed, and is widely applied to the field of low-voltage power.
As shown in fig. 1, a trench is formed in a silicon substrate or an epitaxial layer 1 of an existing trench type power MOSFET with a shield gate, where the trench includes a source control gate trench and a polysilicon gate trench, the polysilicon gate trench is located on two sides of the source control gate trench, and has a depth smaller than that of the source control gate trench, and the source control gate and the polysilicon gate are isolated from each other by a dielectric layer. The MOSFET is characterized in that a well region and a source injection region positioned in the well region are further arranged in the substrate or the upper layer of the epitaxial layer, an interlayer medium is further arranged on the surface of the substrate or the epitaxial layer, a metal layer is further arranged on the surface of the interlayer medium, a conducting wire is formed after the metal layer is patterned, and the metal layer penetrates through the interlayer medium through a contact hole to be in contact with a corresponding contact region in the substrate to lead out each electrode of the MOSFET.
As shown in fig. 1, the thickness of the dielectric layer between the source control gate and the polysilicon gate is determined by the growth process of the gate dielectric layer, and is limited by the thickness of the gate dielectric layer, and the source control gate and the polysilicon gate are prone to leakage due to the generally thin thickness of the gate dielectric layer.
Disclosure of Invention
The present invention is directed to a trench type trench power MOSFET, and a process method of the trench type power MOSFET is also provided.
To solve the above problems, the present invention provides a trench power MOSFET, comprising: the semiconductor substrate is provided with a plurality of first grooves, and a first dielectric layer is filled in the first grooves.
And 3 second grooves are formed in the first dielectric layer, each second groove comprises a source control gate groove positioned in the middle and polysilicon gate grooves positioned on two sides of the source control gate, and the depth of the source control gate groove is greater than that of the polysilicon gate groove.
And second dielectric layers are arranged in the grooves of the source control grid and the polycrystalline silicon grid and are attached to the inner side walls and the bottoms of the grooves.
And the source control gate trench and the polysilicon gate trench are filled with polysilicon.
The epitaxy between the first trenches is also provided with a well injection region, and the well injection region is also provided with a source injection region.
Furthermore, the first dielectric layer and the second dielectric layer are oxide layers.
Furthermore, the epitaxial surface is also provided with a layer of interlayer medium, the surface of the interlayer medium is covered with a layer of metal layer, and the metal layer is patterned to form a lead.
The metal layer also leads out the trap injection region, the polysilicon gate and the source control gate through a contact hole penetrating through the interlayer medium.
Furthermore, the back surface of the epitaxy is also provided with a back metal layer, and the drain electrode of the groove type power MOSFET is led out.
In order to solve the above problems, the process method of the trench type power MOSFET of the present invention comprises the following process steps:
the method comprises the steps of firstly, providing a semiconductor substrate, depositing a silicon oxide layer on the semiconductor substrate, then forming a layer of photoresist, defining a groove area by the photoresist, and etching the silicon oxide layer and the semiconductor substrate to form a plurality of first grooves.
And secondly, oxidizing the whole body to form a first dielectric layer.
And thirdly, integrally depositing a second dielectric layer.
And fourthly, depositing polycrystalline silicon in the first groove, filling the first groove with the polycrystalline silicon, and then etching back the polycrystalline silicon.
And fifthly, removing the second dielectric layer above the substrate.
And sixthly, etching the first dielectric layer by adopting a wet etching process to form a second groove for filling the polycrystalline silicon.
And seventhly, growing a thin gate dielectric layer, filling the polysilicon and etching back to form the polysilicon gate.
And eighthly, completing well injection, performing ion injection of a heavy doping contact leading-out region in the formed well, depositing an interlayer medium and a metal layer, etching to form a contact hole, and performing back metallization to form a back electrode.
Further, in the first step, the semiconductor substrate is a silicon substrate or a silicon epitaxial layer.
Further, in the second step, the integrally deposited first dielectric layer covers the side wall and the bottom of the first trench and is integrated with the silicon oxide on the surface of the semiconductor substrate, and the first dielectric layer is a silicon oxide layer.
Further, in the third step, the deposited second dielectric layer covers the surface of the first dielectric layer, and further fills the first trench, so that the internal space of the first trench is reduced.
Further, in the fourth step, the deposited polysilicon is etched back until the upper surface of the polysilicon in the first trench is flush with the surface of the semiconductor substrate, and the rest part of the polysilicon is completely removed.
Further, in the fifth step, a wet etching process is adopted to remove all the second dielectric layer above the upper surface of the polysilicon in the first trench.
Further, in the sixth step, the first dielectric layer in the first trench is etched downwards by a wet method until the space formed by etching the first dielectric layer below the surface of the semiconductor substrate can meet the requirement of forming a polysilicon gate.
Further, in the seventh step, the deposited polysilicon is etched back until the upper surface of the polysilicon in the polysilicon gate trench is flush with the surface of the semiconductor substrate until the entire device surface is flat.
According to the trench type power MOSFET, the second dielectric layer is additionally arranged between the source control gate and the polysilicon gate, so that the source control gate is not isolated from the polysilicon gate only by the gate dielectric layer and is not limited by the thickness of the gate dielectric layer.
Drawings
Fig. 1 is a schematic diagram of a device structure of a conventional trench power MOSFET.
FIGS. 2 to 9 are schematic views of the process steps of the present invention.
FIG. 10 is a process flow diagram of the present invention.
Description of the reference numerals
The structure comprises a semiconductor substrate 1, a source control gate 2, a well contact lead-out 3, a back metal 4, a well region 5, a source injection region 6, an interlayer dielectric ILD 7, a front metal 8, a polysilicon gate 9, a first dielectric layer 10, a polysilicon gate dielectric layer 11 and a second dielectric layer 12.
Detailed Description
As shown in fig. 9, the trench power MOSFET of the present invention includes: a semiconductor substrate 1, which is generally a silicon substrate or a silicon epitaxial layer, in this embodiment a silicon epitaxial layer. The semiconductor substrate has a plurality of first trenches filled with a first dielectric layer 10.
And 3 second grooves are formed in the first dielectric layer 10, each second groove comprises a source control gate groove positioned in the middle and polysilicon gate grooves positioned on two sides of the source control gate, and the depth of the source control gate groove is greater than that of the polysilicon gate groove.
Second dielectric layers 12 are further arranged in the grooves of the source control gate and the polycrystalline silicon gate and attached to the inner side walls and the bottoms of the grooves; the first dielectric layer and the second dielectric layer are generally silicon oxide layers.
And filling polysilicon in the source control gate trench and the polysilicon gate trench to form corresponding source control gate and polysilicon gate.
The epitaxy between the first trenches is also provided with a well injection region, and the well injection region is also provided with a source injection region.
The epitaxial surface is also provided with a layer of interlayer medium 7, the surface of the interlayer medium is covered with a layer of front metal layer 8, the metal layer is patterned to form a lead, and the trap injection region 3, the polysilicon gate and the source control gate are led out through a contact hole penetrating through the interlayer medium 7.
And a back metal layer is arranged on the back of the epitaxy, and a drain electrode of the groove type power MOSFET is led out by 4.
Compared with the structure of the traditional groove type power MOSFET, the structure of the invention adds the second dielectric layer between the polysilicon gate and the source control gate, and because the source control gate and the polysilicon gate of the traditional groove type power MOSFET are isolated only by the gate dielectric layer 11 of the polysilicon gate, the invention is limited by the thickness of the gate dielectric layer, and the isolation effect between the source control gate and the polysilicon gate is poor, and the invention improves the isolation distance between the source control gate and the polysilicon gate by utilizing the added second dielectric layer 12, so that the isolation effect is better, and the electric leakage is not easy to generate.
The process method of the trench type power MOSFET comprises the following process steps (each step corresponds to the accompanying drawings 2-9) with reference to the accompanying drawings 2-9:
in a first step, a semiconductor substrate, typically a silicon substrate or a silicon epitaxy, is provided. Depositing a silicon oxide layer on the semiconductor substrate, then forming a photoresist layer, defining a groove region by the photoresist, and etching the silicon oxide layer and the semiconductor substrate to form a plurality of first grooves.
And secondly, oxidizing the whole body to form a first dielectric layer, such as a silicon oxide layer. The first dielectric layer covers the side wall and the bottom of the first groove and is integrated with the silicon oxide on the surface of the semiconductor substrate.
And thirdly, integrally depositing a second dielectric layer which covers the surface of the first dielectric layer, namely completely covering the first dielectric layer in the first groove, including the side wall and the bottom, and integrally covering the surface of the semiconductor substrate with the second dielectric layer.
And fourthly, depositing polycrystalline silicon in the first groove, wherein the polycrystalline silicon fills the first groove, and then etching back the polycrystalline silicon until the upper surface of the polycrystalline silicon in the first groove is basically flush with the upper surface of the substrate. And the polysilicon in the rest first trench forms a source control gate, and the rest polysilicon is completely removed.
And fifthly, removing all the second dielectric layers above the upper surface of the polycrystalline silicon in the first groove by adopting a wet etching process.
And sixthly, etching the first dielectric layer by adopting a wet etching process until the space formed from the position below the surface of the semiconductor substrate to the two sides of the source control gate can meet the requirement of forming the polysilicon gate.
And seventhly, growing a thin gate dielectric layer, filling polycrystalline silicon and etching back to be flush with the surface of the semiconductor substrate to form the polycrystalline silicon gate.
And eighthly, completing well injection, performing ion injection of a heavy doping contact leading-out region in the formed well, depositing an interlayer medium and a metal layer, etching to form a contact hole, and performing back metallization to form a back electrode, so that the whole device is manufactured.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. A trench power MOSFET comprising a semiconductor substrate, wherein: the semiconductor substrate is provided with a plurality of first grooves, and first dielectric layers are filled in the first grooves;
forming 3 second grooves in the first dielectric layer, wherein the second grooves comprise a source control gate groove in the middle and polysilicon gate grooves on two sides of the source control gate, and the depth of the source control gate groove is greater than that of the polysilicon gate groove;
second dielectric layers are arranged in the grooves of the source control grid and the grooves of the polysilicon grid, and the second dielectric layers are attached to the inner side walls and the bottoms of the grooves;
the source control gate trench and the polysilicon gate trench are filled with polysilicon;
a well injection region is further arranged in the extension between the first grooves, and the injection junction depth of the well injection region exceeds the depth of the grooves of the polysilicon gate;
and the upper surface in the well injection region is also provided with a layer of source injection region, and the doping type of the source injection region is opposite to that of the well injection region.
2. The trench power MOSFET of claim 1 wherein: the first dielectric layer and the second dielectric layer are silicon oxide layers.
3. The trench power MOSFET of claim 1 wherein: the surface of the semiconductor substrate is also provided with a layer of interlayer medium, the surface of the interlayer medium is covered with a layer of metal layer, and the metal layer forms a lead after patterning;
the metal layer also leads out the trap injection region, the polysilicon gate and the source control gate through a contact hole penetrating through the interlayer medium.
4. The trench power MOSFET of claim 1 wherein: the back surface of the epitaxy is also provided with a back metal layer, and the drain electrode of the groove type power MOSFET is led out.
5. A process method for fabricating a trench power MOSFET as claimed in claim 1 wherein: comprises the following process steps:
the method comprises the steps of firstly, providing a semiconductor substrate, depositing a silicon oxide layer on the semiconductor substrate, then forming a layer of photoresist, defining a groove area by the photoresist, and etching the silicon oxide layer and the semiconductor substrate to form a plurality of first grooves;
secondly, oxidizing the whole body to form a first dielectric layer;
thirdly, integrally depositing a second dielectric layer;
fourthly, depositing polycrystalline silicon in the first groove, filling the first groove with the polycrystalline silicon, and then etching back the polycrystalline silicon;
fifthly, removing the second dielectric layer above the substrate;
sixthly, etching the first dielectric layer by adopting a wet etching process to form a second groove for filling the polycrystalline silicon;
seventhly, growing a thin gate dielectric layer, filling polycrystalline silicon and etching back to form a polycrystalline silicon gate;
and eighthly, completing well injection, performing ion injection of a heavy doping contact leading-out region in the formed well, depositing an interlayer medium and a metal layer, etching to form a contact hole, and performing back metallization to form a back electrode.
6. The process of claim 5, wherein: in the first step, the semiconductor substrate is a silicon substrate or a silicon epitaxial layer.
7. The process of claim 6, wherein: in the second step, the integrally deposited first dielectric layer covers the side wall and the bottom of the first groove and is integrated with the silicon oxide on the surface of the semiconductor substrate, and the first dielectric layer is a silicon oxide layer.
8. The process of claim 6, wherein: in the third step, the deposited second dielectric layer covers the surface of the first dielectric layer, and the first groove is further filled, so that the internal space of the first groove is reduced.
9. The process of claim 6, wherein: and in the fourth step, the deposited polycrystalline silicon is etched back until the upper surface of the polycrystalline silicon in the first groove is flush with the surface of the semiconductor substrate, and the rest part of the polycrystalline silicon is completely removed.
10. The process of claim 6, wherein: and in the fifth step, removing all the second dielectric layer on the upper surface of the polycrystalline silicon in the first groove by adopting a wet etching process.
11. The process of claim 6, wherein: and in the sixth step, the first dielectric layer in the first groove is etched downwards by a wet method until the etching reaches the space formed below the surface of the semiconductor substrate, so that the polysilicon gate can be formed.
12. The process of claim 6, wherein: and in the seventh step, etching back the deposited polysilicon until the upper surface of the polysilicon in the polysilicon gate trench is flush with the surface of the semiconductor substrate, so that the whole device surface is kept flat.
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| CN201911297111.2A CN110993693A (en) | 2019-12-16 | 2019-12-16 | Groove type power MOSFET and process method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113078067A (en) * | 2021-03-30 | 2021-07-06 | 电子科技大学 | Manufacturing method of trench separation gate device |
| CN113224151A (en) * | 2021-04-29 | 2021-08-06 | 厦门吉顺芯微电子有限公司 | Manufacturing method of trench type SGT-MOS device with low electric leakage and high stability |
| WO2023284210A1 (en) * | 2021-07-13 | 2023-01-19 | 苏州东微半导体股份有限公司 | Semiconductor power device and control method therefor |
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| CN113078067A (en) * | 2021-03-30 | 2021-07-06 | 电子科技大学 | Manufacturing method of trench separation gate device |
| CN113224151A (en) * | 2021-04-29 | 2021-08-06 | 厦门吉顺芯微电子有限公司 | Manufacturing method of trench type SGT-MOS device with low electric leakage and high stability |
| WO2023284210A1 (en) * | 2021-07-13 | 2023-01-19 | 苏州东微半导体股份有限公司 | Semiconductor power device and control method therefor |
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