CN113327858A - Shielded gate field effect transistor and method of manufacturing the same - Google Patents

Shielded gate field effect transistor and method of manufacturing the same Download PDF

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CN113327858A
CN113327858A CN202010679116.8A CN202010679116A CN113327858A CN 113327858 A CN113327858 A CN 113327858A CN 202010679116 A CN202010679116 A CN 202010679116A CN 113327858 A CN113327858 A CN 113327858A
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polysilicon
region
gate
oxide layer
effect transistor
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CN113327858B (en
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刘龙平
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GTA Semiconductor Co Ltd
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SHANGHAI ADVANCED SEMICONDUCTO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

The invention discloses a shielded gate field effect transistor and a manufacturing method thereof. A plurality of ring region grooves which are sequentially nested are manufactured on a semiconductor substrate, and a first ring region groove surrounds a cell region; manufacturing and generating a shield grid polysilicon; arranging a target area on a semiconductor substrate, and eliminating an active area thick oxide layer in the target area; and manufacturing the shield grid polysilicon. By adopting a low-cost and high-compatibility polysilicon etching process and a new layout design scheme, the problem of short circuit caused by polysilicon residue of a grid electrode and a source electrode is solved.

Description

Shielded gate field effect transistor and method of manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a manufacturing method thereof.
Background
With the rapid development of electronic information and the rapid development of portable products, the demand of power devices such as shielded gate field effect transistors (SGT MOSFETs) is increasing. The SGT MOSFET is a novel groove MOSFET adopting a charge balance technical mode, and realizes charge balance by integrating a shielding electrode, so that the epitaxial impedance related to the critical component of on-resistance and drain-source breakdown voltage in the MOSFET is reduced. Meanwhile, the shielding electrode positioned below the grid electrode converts most grid-drain capacitance at the bottom of the traditional trench MOSFET into grid-source capacitance, so that the grid-drain capacitance is effectively reduced, the switching loss is reduced, the efficiency is improved, and conditions are created for higher-frequency work.
As shown in fig. 1, fig. 1 of a trench field oxide etching layout of a cell region under a medium voltage SGT polysilicon CMP (Chemical Mechanical Polishing) process in the prior art includes a cell region trench 1, a shield gate metal via 2, a control gate metal via 3, a source region metal via 4, a cell region 5, a first ring region trench 6, a ring region 7, and an original target region 8-1 partially surrounded and formed by a dotted line. In a conventional shielded gate field effect transistor, a thick oxygen step in an active region between trench field oxygen and a trench in a region defined by a cell region is etched. As shown in fig. 2 and fig. 3, which are schematic cross-sectional views of the shielded gate field effect transistor in the direction of the tangent line 1 and the direction of the switch 2 in fig. 1, it can be seen from the drawings that a thick oxygen step outside the region is retained, and a thick oxide layer 15 step appears at the active region boundary of the region where the control gate and the shielded gate are located, as shown in fig. 4, a polysilicon residue is formed in the cell region trench field oxygen etching layout definition boundary region in the subsequent control gate polysilicon etching process, which causes a short circuit between the source and the gate, resulting in device failure.
Disclosure of Invention
The invention provides a shielded gate field effect transistor and a manufacturing method thereof, aiming at overcoming the defect that in the prior art, polysilicon residue is formed in the process of controlling gate polysilicon etching, so that a source electrode and a gate electrode are short-circuited to cause device failure.
The invention solves the technical problems through the following technical scheme:
in a first aspect, the present invention provides a method for manufacturing a shielded gate field effect transistor, the method comprising:
manufacturing a plurality of sequentially nested ring region grooves on a semiconductor substrate, wherein a first ring region groove surrounds a cell region and is the innermost ring region groove;
manufacturing and generating a shield grid polysilicon;
arranging a target area on the semiconductor substrate, and eliminating an active area thick oxide layer in the target area; the target region comprises the cell region and an epitaxial region, wherein the epitaxial region is an annular region formed by extending a preset width from the boundary of the cell region to the first annular region groove;
and manufacturing and generating the control gate polysilicon.
Preferably, the step of providing a target area on the semiconductor substrate and eliminating the active area thick oxide layer in the target area includes:
and removing the thick oxide layer steps corresponding to the transition regions among all the grooves in the target region.
Preferably, the step of manufacturing the formation control gate polysilicon includes:
carrying out back etching on the shielding grid polysilicon;
growing a gate oxide layer on the inner wall of the groove where the shield gate polycrystalline silicon is located after back etching;
depositing a gate on the bottom of the gate oxide layer to generate the control gate polysilicon; the control gate polysilicon is isolated from the shield gate polysilicon by an oxide layer.
Preferably, the step of etching back the shield gate polysilicon includes:
and wet etching is performed on the field oxide layers on two sides above the inner wall of the groove where the shield grid polycrystalline silicon is located, and the thickness of the field oxide layers is reduced.
Preferably, the manufacturing method further comprises:
carrying out polycrystalline silicon precipitation in the ring region groove to form ring region polycrystalline silicon; and a thick oxide layer covers the upper part of one side of the ring region polysilicon far away from the target region.
Preferably, the cross-sectional area of the control gate polysilicon is larger than that of the shield gate polysilicon.
Preferably, the field oxide layer and the gate oxide layer are SiO2。
Preferably, the shield grid polysilicon is interconnected with metal through holes of the shield grid.
Preferably, the control gate polysilicon is interconnected by metal through holes. In a second aspect, the present invention provides a shielded gate field effect transistor, which is manufactured by using the manufacturing method of the shielded gate field effect transistor of the first aspect.
The positive progress effects of the invention are as follows: the invention provides a shielded gate field effect transistor and a manufacturing method thereof. A plurality of ring region grooves which are sequentially nested are manufactured on a semiconductor substrate, and a first ring region groove surrounds a cell region; manufacturing and generating a shield grid polysilicon; arranging a target area on a semiconductor substrate, and eliminating an active area thick oxide layer in the target area; and manufacturing the shield grid polysilicon. By adopting a low-cost and high-compatibility polysilicon etching process and a new layout design scheme, the problem of short circuit caused by polysilicon residue of a grid electrode and a source electrode is solved.
Drawings
Fig. 1 is a schematic diagram of a layout design of trench field oxygen etching of a cell region under a medium-voltage SGT polysilicon CMP process in the prior art.
Fig. 2 is a cross-sectional view of the shielded gate field effect transistor along the direction of the tangent line 1 in fig. 1.
Fig. 3 is a cross-sectional view of the shielded gate field effect transistor of fig. 1 along the direction of the tangent line 2.
Fig. 4 is a cross-sectional view of the shielded gate field effect transistor of fig. 1 taken along line 3.
Fig. 5 is a flowchart of a method for manufacturing a shielded gate field effect transistor according to embodiment 1 of the present invention.
Fig. 6 is a layout diagram of trench field oxygen etching in the cell region under the medium-voltage SGT polysilicon CMP process in embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional view of the shielded gate field effect transistor in step S4 of fig. 5.
Fig. 8 is a second cross-sectional view of the shielded gate field effect transistor in step S4 of fig. 5.
Fig. 9 is a flowchart of step S4 of the method for manufacturing the shielded gate field effect transistor according to embodiment 1 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The present embodiment provides a method for manufacturing a shielded gate field effect transistor, and referring to fig. 5, the method includes:
step S1, a plurality of sequentially nested ring region trenches are formed on the semiconductor substrate, the first ring region trench 6 surrounds the cell region 5, and the first ring region trench 6 is the innermost ring region trench.
In the manufacturing process of various semiconductor devices, etching of a trench is required to form a trench structure. Generally, in the trench etching method, a photoresist is coated and is subjected to photolithography, then a hard mask is etched by using a photoresist pattern, and finally a trench is etched by using the etched hard mask pattern. One dimension may be present after the photoresist is etched and another dimension may be present after the hard mask is etched, both dimensions defining the final dimensions of the trench. A plurality of ring region grooves are sequentially manufactured on a semiconductor substrate, each ring region groove surrounds each other from large to small, the ring region groove 6 at the innermost side comprises the whole cell region 5, and a plurality of cell region grooves 1, a plurality of shielding grid polycrystalline silicon 9 and a plurality of control grid polycrystalline silicon 12 can be arranged in the cell region 5.
Step S2, the shield gate polysilicon 9 is produced.
The shielded gate field effect transistor (SGT) is widely applied to the field of medium and low voltage switching devices due to the low on-resistance of the SGT. And depositing a shielding grid in the trench 1 of the cell region, wherein the shielding grid is made of polysilicon and is in short circuit with the source electrode, and after the growth of the shielding grid is finished, the shielding grid can be etched back according to the preset depth of the shielding grid, so that the depth of the shielding grid is reduced.
In this embodiment, a plurality of shield gate polysilicon 9 are fabricated in the cell region trench 1, and every two shield gate polysilicon 9 are distributed on the upper and lower sides of the cell region trench 1, but the number of the shield gate polysilicon 9 is not specifically limited. Therefore, the number of the shield gate polysilicon 9 can be set by those skilled in the art according to the specific application.
Further, the shield gate polysilicon 9 can be interconnected with metal through the shield gate metal via 2.
Step S3 is to provide a target region 8-2 on the semiconductor substrate and to eliminate the active region thick oxide layer 15 in the target region 8-2. The target region 8-2 includes a cell region 5, and the target region 8-2 further includes an epitaxial region, which is an annular region formed by extending a predetermined width from the boundary of the cell region 5 to the first annular region trench 6.
Referring to fig. 6, a layout of trench field oxide etching in the cell region under the medium-voltage SGT polysilicon CMP process in this embodiment is shown, where fig. 6 includes a target region 8-2 partially surrounded by a dotted line. As can be seen from a comparison of FIG. 1, the area of the target region 8-2 is larger than the original target region 8-1 in the prior art, including the entire cell region 5, and the boundary of the target region 8-2 is located at the middle of the innermost ring region trench 6.
In this embodiment, after the target region 8-2 is set, the active region thick oxide layer 15 in the target region 8-2 is removed. The target region 8-2 includes a cell region 5 and an epitaxial region located in the ring region trench 6, the epitaxial region is formed by extending from the boundary of the cell region 5 to the first ring region trench 6 by a predetermined width, which may be half the width of the ring region trench. It is understood that the dimension of the preset width can be set by a person skilled in the art according to specific process requirements, and will not be described herein again.
Wherein, step S3 further includes: and removing the steps of the thick oxide layer 15 corresponding to the transition regions between all the trenches in the target region 8-2.
Referring to fig. 7, which is a schematic cross-sectional view of the shielded gate field effect transistor corresponding to the direction of the tangent line 1 in fig. 6, in fig. 7, every two pieces of shielded gate polysilicon 9 are connected through the shielded gate metal vias 2, and then are interconnected through metal, and the source region 11 is located between the shielded gate metal vias 2. The thick oxide layer 15 in the target region 8-2 is completely removed, so that no residue is left in the subsequent polysilicon etching process for manufacturing the control gate, and finally the source 11 and the gate are electrically separated to meet the requirements of the device, while the thick oxide layer 15 covered outside the target region 8-2 is retained. The field oxide layers 13 on both sides of the trench where the shield gate polysilicon 9 is located are partially etched, the polysilicon is oxidized at the same time in the gate oxidation process step to form an oxide layer, and the remaining gap is filled into the control gate polysilicon 12 manufactured later.
And step S4, manufacturing and generating the control gate polysilicon 12.
Referring to fig. 8, the control gate polysilicon 12 is formed above the shield gate polysilicon 9, and usually, after the shield gate polysilicon 9 and the control gate polysilicon 12 are deposited, a chemical mechanical polishing process is used, which can complete the polishing of the polysilicon in the active region except the trench, and can also polish the thick oxide layer 15 in the active region grown simultaneously with the field oxide in the trench. In step S3, after removing the thick oxide layer 15 in the target region 8-2, the control gate polysilicon 12 is formed over part of the shield gate polysilicon 9.
It should be noted that the cross-sectional area of the control gate polysilicon 12 formed after etching is larger than that of the shield gate polysilicon 9. The gate oxide layer 14 is regrown on both sides of the control gate polysilicon 12, and the field oxide layers 13 on both sides of the shield gate polysilicon 9 are etched back, so that the original thickness of the field oxide layers 13 is reduced.
Further, in fig. 8, metal interconnection between the control gate polysilicon 12 can be performed through the control gate metal via 3.
Wherein, the polysilicon deposition is carried out in the ring region groove 6 to form ring region polysilicon; wherein, the side of the ring region polysilicon far from the target region 8-2 is covered with a thick oxide layer 15.
The embodiment provides a manufacturing method of a shielded gate field effect transistor, which comprises the steps of manufacturing a plurality of sequentially nested ring region grooves on a semiconductor substrate, wherein a first ring region groove surrounds a cell region; manufacturing and generating a shield grid polysilicon; arranging a target area on a semiconductor substrate, and eliminating an active area thick oxide layer in the target area; and manufacturing the shield grid polysilicon. By adopting a low-cost and high-compatibility polysilicon etching process and a new layout related scheme, the problem of short circuit caused by polysilicon residue of a grid electrode and a source electrode is solved.
Example 2
As shown in fig. 9, the method for manufacturing a shielded gate field effect transistor according to this embodiment is further expanded on the basis of embodiment 1, and step S4 of the method for manufacturing a shielded gate field effect transistor according to this embodiment further includes:
step S41, etching back the shield gate polysilicon 9.
Wherein, step S41 includes:
and wet etching the field oxide layers 13 on two sides above the inner wall of the groove where the shield grid polysilicon 9 is positioned, and thinning the thickness of the field oxide layers 13.
And step S42, growing a gate oxide layer 14 on the inner wall of the trench where the shield gate polysilicon 9 is positioned after etching back.
Step S43, depositing a gate on the bottom of the gate oxide layer 14 to create the control gate polysilicon 12. Wherein the control gate polysilicon 12 is isolated from the shield gate polysilicon 9 by the oxide layer.
In this embodiment, the control gate polysilicon 12 is formed above the plurality of shield gate polysilicon 9 in the cell region 5, a field oxide layer 13 is formed between the control gate polysilicon 12 and the shield gate polysilicon 9, electrical insulation is realized by the field oxide layer 13, and a short circuit phenomenon does not occur, which meets the requirements of the manufacturing process of the shield gate field effect transistor.
In this embodiment, the field oxide layer 13 and the gate oxide layer 14 are SiO 2.
The embodiment provides a manufacturing method of a shielded gate field effect transistor, which comprises the steps of manufacturing a plurality of sequentially nested ring region grooves on a semiconductor substrate, wherein a first ring region groove surrounds a cell region; manufacturing and generating a shield grid polysilicon; arranging a target area on a semiconductor substrate, and eliminating an active area thick oxide layer in the target area; and manufacturing the shield grid polysilicon. By adopting a low-cost and high-compatibility polysilicon etching process and a new layout related scheme, the problem of short circuit caused by polysilicon residue of a grid electrode and a source electrode is solved.
Example 3
The present embodiment provides a shielded gate field effect transistor, which is manufactured by using the manufacturing method of the shielded gate field effect transistor in embodiment 1 or embodiment 2.
In the field effect transistor with the shielded gate provided by this embodiment, the shape of the trench in which the control gate is located in the cell region is not changed, and the shape of the field oxide in the trench outside the first ring region and the shape of the polysilicon and the field oxide in the trenches outside the first ring region are not changed. The requirements of high electric field strength resistance and high voltage resistance are met, the electrical performance and reliability of the device are not affected, and the performance requirements of device manufacturing are met.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (10)

1. A method for fabricating a shielded gate field effect transistor, the method comprising:
manufacturing a plurality of sequentially nested ring region grooves on a semiconductor substrate, wherein a first ring region groove surrounds a cell region and is the innermost ring region groove;
manufacturing and generating a shield grid polysilicon;
arranging a target area on the semiconductor substrate, and eliminating an active area thick oxide layer in the target area; the target region comprises the cell region and an epitaxial region, wherein the epitaxial region is an annular region formed by extending a preset width from the boundary of the cell region to the first annular region groove;
and manufacturing and generating the control gate polysilicon.
2. The method of fabricating a shielded gate field effect transistor according to claim 1 wherein said providing a target area on said semiconductor substrate, said removing an active area thick oxide layer in said target area comprising:
and removing the thick oxide layer steps corresponding to the transition regions among all the grooves in the target region.
3. The method of fabricating a shielded gate field effect transistor according to claim 1 wherein said step of fabricating a grown control gate polysilicon includes:
carrying out back etching on the shielding grid polysilicon;
growing a gate oxide layer on the inner wall of the groove where the shield gate polycrystalline silicon is located after back etching;
depositing a gate on the bottom of the gate oxide layer to generate the control gate polysilicon; the control gate polysilicon is isolated from the shield gate polysilicon by an oxide layer.
4. The method of claim 3, wherein said back etching said shield gate polysilicon comprises:
and wet etching is performed on the field oxide layers on two sides above the inner wall of the groove where the shield grid polycrystalline silicon is located, and the thickness of the field oxide layers is reduced.
5. The method of fabricating a shielded gate field effect transistor according to claim 1, wherein the method of fabricating further comprises:
carrying out polycrystalline silicon precipitation in the ring region groove to form ring region polycrystalline silicon; and a thick oxide layer covers the upper part of one side of the ring region polysilicon far away from the target region.
6. The method of claim 1 wherein the control gate polysilicon has a cross-sectional area greater than the cross-sectional area of the shield gate polysilicon.
7. The method of claim 4, wherein said shielded gate field effect transistor is formedThe field oxide layer and the gate oxide layer are SiO2。
8. The method of claim 1, wherein said shield gate polysilicon is metal interconnected by shield gate metal vias.
9. The method of claim 1 wherein said control gate polysilicon is metal interconnected by control gate metal vias.
10. A shielded gate field effect transistor produced using the method of any one of claims 1 to 9.
CN202010679116.8A 2020-07-15 2020-07-15 Shielded gate field effect transistor and method of manufacturing the same Active CN113327858B (en)

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US20190348510A1 (en) * 2018-05-08 2019-11-14 Ipower Semiconductor Shielded trench devices
CN110676312A (en) * 2019-11-07 2020-01-10 苏州凤凰芯电子科技有限公司 Shielding grid MOS device terminal structure with step-type oxide layer and manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114334663A (en) * 2022-03-15 2022-04-12 广州粤芯半导体技术有限公司 Power device and preparation method thereof
CN114334663B (en) * 2022-03-15 2022-05-17 广州粤芯半导体技术有限公司 Power device and preparation method thereof

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